Allegro

PCB Editor User Guide:

Completing the Design
Series XL and GXL
Product Version 16.0
June 2007
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Allegro PCB Editor User Guide: Completing the Design
June 2007 3 Product Version 16.0
Preface............................................................................................................................ 5
1
Renaming Reference Designators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
The Auto Ref Des Rename Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Setting Automatic Rename Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Executing the Rename Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Backannotating the Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Renaming from a Batch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Attaching the AUTO_RENAME Property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Editing the Placement Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Locating Rows and Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting Grids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2
Meeting DFA Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Using Real-Time DFA Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Using Batch-Mode DFA Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Dening Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Prioritizing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Saving Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Selecting the Audits To Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Performing the Audit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Viewing Violations and Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Completing the Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DFA Audit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Component Assembly Clearance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Component Orientation and Mounting Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Lead Span . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Orphan Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Contents
Allegro PCB Editor User Guide: Completing the Design
June 2007 4 Product Version 16.0
Hole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Hanging Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3
Extracting Allegro PCB Editor Views . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Extract Command File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Property Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Group Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Multiple Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SORT Data Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Baseview Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Baseview File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
The extracta Output File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
A Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
J Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
S Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Sample Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4
Extract Data Dictionary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Data Fields and Legal Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Data Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5
Generating Test Coupons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Coupon Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Allegro PCB Editor User Guide: Completing the Design
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Preface
The design completion stage of a design owmay involve tasks related to renaming reference
designators, running audits, extracting information from your design, and generating
coupons. The following chapters cover these aspects of design completion.
Backannotating your design to a schematic capture tool is frequently done at this stage, but
that information is covered in the Logic section of the documentation.
The following gure illustrates the design completion stage in a design ow.
Allegro PCB Editor User Guide: Completing the Design
Preface
June 2007 6 Product Version 16.0
Renaming Reference Designators in a Design Flow
LIBRARY DEVELOPMENT
Create custom pad shapes
Define library padstacks
Define unique packages
Define mechanical elements
LIBRARY DEVELOPMENT
Create custom pad shapes
Define library padstacks
Define unique packages
Define mechanical elements
LOGIC DATA TRANSFER
Create design database
Associate schematic or create and
enter third-party netlist
LAYOUT PREPARATION
Define design rules (properties and
constraints)
Define layers (cross section)
Create mechanical elements
(outline, keepins, keepouts)
DESIGN LAYOUT
Placement (automatic/interactive)
Routing (automatic/interactive)
DESIGN COMPLETION
Rename reference designators
Backannotate
Add power and ground planes
Run Design Rule Checking (DRC)
MANUFACTURING OUTPUT
Generate pen plots
Create artwork
Generate numerical control output
Design
completion
tasks
DESIGN ANALYSIS
Signal integrity analysis
EMI Compliance
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1
Renaming Reference Designators
This chapter describes how to rename reference designators using Allegro PCB Editor
automatic renaming feature, LogicAuto Rename RefDes.
After you place and route a new design or rearranged components on an existing design,
reference designators must normally be renamed to aid accurate testing and assembly on the
actual board.
The automatic renaming process in Allegro PCB Editor lets you rename every component on
a design in a single operation without having to attach the AUTO_RENAME property to each
component. Renaming occurs on both sides of the board in a single operation.
Note: When you choose this method, the prexes stored in the symbol denition are used in
the new reference designators. In addition, separate counters run for components with
different prexes.
You can also elect to rename individual components by attaching the AUTO_RENAME
property to them or by renaming components on one side of the board only.
Renaming is controlled by placement grid line locations only (user-dened or default
selection) or by sequential renaming within grid blocks. With grid-based renaming, you can
designate the direction (horizontal or vertical) and order (left-right, right-left, upwards-
downwards) of the renaming process. Additionally, you can dene grid descriptions by alpha
characters and/or integers.
All of these options are accessed by selections on a graphical user interface, dened in detail
in this chapter.
The Auto Ref Des Rename Flow
The automatic renaming function in Allegro PCB Editor is a straight-forward, easy to
implement feature. Figure 1-1 illustrates the steps necessary to perform this operation.
Allegro PCB Editor User Guide: Completing the Design
Renaming Reference Designators
June 2007 8 Product Version 16.0
Figure 1-1 : The Automatic Renaming Flow
Setting Automatic Rename Options
The options available in the automatic reference designator (auto refdes) in Allegro PCB
Editor rename feature are available only through the Rename Ref Des dialog boxes. There
are two dialog boxes:
I Rename Ref Des
Complete set-up dialog boxes
Edit placement grid
Execute
Select area to rename
No
Yes
Will
grids result in
proper
renaming?
Attach AUTO_RENAME
property to those components
you want to rename.
Yes
No
Rename all components
automatically?
(No property attachment
required)
Yes
Backannotate
Customizegrids
using Edit
command
Allegro PCB Editor User Guide: Completing the Design
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This dialog box is accessed through the menu bar. It lets you choose whether to rename
all the design components or to choose specic components for renaming. It also lets
you choose a placement grid conguration.
I Rename Ref Des Set Up
The Set Up dialog box is accessed through the Rename Ref Des dialog box and contains
the balance of the options available in automatic rename, including layer options,
reference designator format, and renaming method.
Options can be set in any order; that is, the options, format, renaming methods, and so on in
the Set Up dialog box can be chosechose before the options available in the main dialog box.
For procedural information, see Logic Auto Rename RefDes Rename (rename
param command) in the Allegro PCB and Package Physical Layout Command
Reference.
Executing the Rename Function
Once you set up all options in the rename dialog boxes, you execute the rename process in
a particular area.
1. Select the portion of the design to be renamed.
LogicAuto Rename RefDesDesign (rename area design command) that
is, the entire board.
LogicAuto Rename RefDesRoom (rename area room command) opens a
ll-in that requires you to enter a room name.
LogicAuto Rename RefDesWindow (rename area window command) lets
you choose a dened area of the design.
LogicAuto Rename RefDesList (rename area list command) opens a
window that displays what area is currently active.
2. From the Rename menu, click OK.
The status line in Allegro PCB Editors console window prompt displays the message
Auto Rename of Reference Designators IN PROGRESS.
As the operation proceeds, various warning or error messages may appear at the
console window prompt. When the operation nishes, the status line reads:
Auto Rename of Refdes COMPLETE. x components renamed.
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June 2007 10 Product Version 16.0
Backannotating the Database
After you rename reference designators in the design, communicate those database changes
back to the schematic through backannotation. For details on performing backannotation, see
Transferring Native Logic.
The rename.log File
The automatic rename operation generates a log le that lets you review the results of the
operation. It provides information on each component processed and the result of the
renaming. A truncated sample rename.log le is shown in Figure 1-2.
Allegro PCB Editor User Guide: Completing the Design
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June 2007 11 Product Version 16.0
Figure 1-2 : Sample rename.log File
Renaming from a Batch Command
Allegro PCB Editor running on a UNIX workstation provides a batch program called reftxt
that uses a text le to rename reference designators. In the text le, you can indicate changes
anywhere on the design and allow the reference designator to have any number of
characters. You run this program after components are placed.
( )
( RENAME REFDES )
( )
( Drawing : design.brd )
( Date/Time : Wed Jun 12 14:32:22 1996 )
( )
(------------------------------------------------------------)
Renaming components on BOTH_SIDES on entire BOARD
Extents: (-10100.0,-15300.0) (33900.0,18700.0)
Sequencing the Reference Designators by ROW AND COLUMN.
Rows : to the RIGHT, Columns : DOWN.
Processing TOP of board, C13 has AUTO_RENAME property but is on
BOTTOM, component ignored.
Processing TOP of board, C4 has AUTO_RENAME property but is on
BOTTOM, component ignored.
Processing TOP of board, C1 has AUTO_RENAME property but is on
BOTTOM, component ignored.
Allegro PCB Editor User Guide: Completing the Design
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June 2007 12 Product Version 16.0
Creating a Rename Text File
The rename text le that you create with a text editor is a was/is list of reference designators.
Each line describes one reference designator to be changed, followed by at least one space
or tab, then the reference designator to be substituted. Reference designators can be listed
in any order, and previous ones do not affect those further down the list. A sample list might
appear as follows:
U1 U12
R3 R45
U41 R45
U10 U9
The reftxt command can also be used to accommodate reference designators that might
otherwise be too long for the automatic rename function. For example, reftxt can be used
to change reference designators to include part numbers or other company-dened
information. Below is a sample text le for this type of situation:
Z1 A007421
Z2 A007422
C1 A443011
C2 A443012
If you plan to change to lengthy designators, make sure that the symbols have been built with
a reference designator placement that accommodates them.
Attaching the AUTO_RENAME Property
When you run the rename process on an individual component or on one group of
components at a time, you must dene the components to be renamed by attaching the
AUTO_RENAME property to them individually.
Note: When you are renaming groups of reference designators, you do not want to include
certain components in the renaming process. To prevent these components from being
renamed, attach the HARD_LOCATION property to them.
Editing the Placement Grid
Allegro PCB Editor denes the placement of components within rows and columns based on
their relationship to placement grid lines. As you rename a group of components, you may
need to edit the grid to a size appropriate for those components.
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June 2007 13 Product Version 16.0
Locating Rows and Columns
When you rename components by row only, Allegro PCB Editor numbers themconsecutively
across each row in the direction you specied in the Rename Ref Des Set Up dialog box;
right-to-left or left-to-right, as shown in Figure 1-3.
Figure 1-3 : Components Renumbered by Row
When the components are renamed by column only, Allegro PCB Editor numbers them
consecutively in the direction you specied in the Rename Ref Des Set Up dialog box: either
down or up, as shown in Figure 1-4.
Figure 1-4 : Components Renumbered by Column
On some large designs, you may want to locate the components to be renamed by both row
and column. For example, you can do this by specifying a letter in the row eld and a number
in the column eld. This appears as shown in Figure 1-5.
U1 U2 U3 U4
U4 U3 U2 U1
or
U1
U2 U3
U4
U4
U3 U2
U1
or
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June 2007 14 Product Version 16.0
Figure 1-5 : Components Renumbered by Row and Column
Allegro PCB Editor denes rows and columns as the area between adjacent lines. In Figure
1-6, components with the reference designator U* are being renamed. On this design, the
components line up in orderly rows and columns.
Figure 1-6 : A Layout with Uniformly Arranged Components
In situations where the components are not arrayed neatly, Allegro PCB Editor uses the
component origin dened in the Set Up dialog box to determine in which row or column it
belongs. The following description assumes the default, Body Center, to make the point most
clearly. In the case of columns, if its body center falls directly on a vertical line, Allegro PCB
Editor attaches it to the column on the right. For rows, if its body center falls directly on a
horizontal line, it is attached to the row above the grid. If the grid itself needs to be adjusted,
use the Move option to relocate grid lines.
A unique case arises when more than one component occupies a grid square. Figure 1-7
illustrates the case where you are renaming by both column and row so you can see the use
of sufxes.
UA1 UA2 UA3 UA4
UC1
UB1 UB2 UB3 UB4
UC2 UC3 UC4
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June 2007 15 Product Version 16.0
When you rename by both column and row and more than one component falls within a grid
square, Allegro PCB Editor considers them to have the same reference designator. To
guarantee that each component has a unique reference designator, Allegro PCB Editor
appends a sufx to each. They are incremented by one (UE3, UE3-1, and so on), using the
direction guidelines established in the parameter dialog box. In Figure 1-7 the dened
directions are Right and Down.
Figure 1-7 : A Layout Where Component Assignments Include a Sufx
Note: You can usually avoid the need for sufx character(s) by adjusting the grid lines so
multiple components do not fall within the same grid square.
Setting Grids
Before executing the rename command, examine the grids in the assigned area to ensure
appropriate results. The established placement grid may work, but you might have to
manually alter the grid, or dene a new grid. If you are renaming a variety of different sized
components, you may need to resize the grid for each different set of components.
To create a grid:
1. Create a package keepin area large enough to contain the area of the grid.
2. From the menu bar on Allegro PCB Editor, choose Place Autoplace Top Grids
(place set topgrid command) or Place Autoplace Bottom Grids (place
set bottomgrid command).
The place set grid dialog box appears for the selected grid type.
3. In the dialog box eld, enter an x coordinate, then click OK. (See Creating a Non-Etch
Grid for Interactive Placement in Preparation for Placing Elements for details.)
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The Place Set Grid dialog box for the y coordinate appears.
4. Enter a y coordinate, then click OK.
5. Enter the grid point where you want the grid to originate.
You can indicate this by a mouse pick, or by entering explicit x,y coordinates inside the
placement keepin.
You can customize grid lines by choosing Edit Move (move command), Edit Copy
(copy command), and Edit Delete (delete command).
For additional information on working with grids, see Setting Placement Grids in Preparation
for Placing Elements.
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2
Meeting DFA Requirements
This chapter describes Design For Assembly (DFA) real-time DRC for package-to-package
clearance checks. During interactive placement, designers can understand component-
clearance requirements using the rules-driven DFA Constraints Dialog spreadsheet, whose
values can be associated with an Allegro PCB Editor design.
It also outlines the use of batch-mode DFA analysis audits on a printed circuit board, detailing
the individual audits provided with Allegro PCBEditor, the constraints available for each audit,
and how to dene and prioritize them if necessary.
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Meeting DFA Requirements
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Using Real-Time DFA Checking
Dynamic DFA checks in Allegro PCB Editor support package-to-package clearance
modeling. By implementing rules-driven design techniques, constraints identied during
system design control the physical layout. Real-time DFA analysis occurs as you manually
place components.
You can apply an external DFA rules table owned by manufacturing that represents corporate
DFA standards to a design, then edit or override the table values using the DFA Constraints
Dialog spreadsheet, which denes component side-side (S-S); side-end (S-E), end-end (E-
E) spacing values in one view that supports top and bottom sides of the PCB separately.
Conversely, use the Read-only eld on the DFA Constraints Dialog spreadsheet to prevent
users from overriding corporate DFA rule standards. The DFA Constraints Dialog
spreadsheet is available by choosing Setup Constraints DFA Constraint
Spreadsheet (dfa_spreadsheet command).
These values in the DFA rules table drive real-time DRC feedback during placement. For
example, a DRC ags too-small part-to-part spacing during part placement and updates it in
real time. All assembly checks occur in the same environment in which you designed the
board, to preclude juggling between Allegro PCB Editor and third-party tools for fabrication
checks.
Allegro PCB Editor User Guide: Completing the Design
Meeting DFA Requirements
June 2007 19 Product Version 16.0
Figure 2-1 Real-time DFA process
Grouping symbol denitions with the DFA_DEV_CLASS property
You can group symbol denitions that share the same clearance values by assigning the
DFA_DEV_CLASSproperty to them. The DFA_DEV_CLASSproperty classies components
according to the Design for Assembly (DFA) package-to-package spacing values dened in
the DFA Constraints Dialog spreadsheet, available by choosing Setup Constraints DFA
Constraint Spreadsheet (dfa_spreadsheet command).
You use the DFA Classication Editor dialog box to add or remove symbol denitions from
user-dened classes. (The DFA Classication Editor is available by clicking Show symbol
classifications... on the DFA Constraints Dialog spreadsheet.) Allegro PCB Editor treats
these classes as components comprised of symbols to which the DFA spacing values
dened for the class default.
For example, fty versions of an 0805 package symbol may exist, all complying to the same
Run dfa_update to add DFA place-bounds to library symbols.
Enable DFA DRC on the DFA Constraints Dialog.
Choose Place - Manually to place components using values from
the DFA Constraints Dialog spreadsheet.
Apply the DFA rules table to the PCB Editor design.
Use the graphical feedback provided by the spacing circles
during placement to assess potential DFA rule violations.
Open the DFA Constraints Dialog by running Setup - DFA
Constraint Spreadsheet and classify symbols that share common
spacing values into classes using the DFA_DEV_CLASS property
on the DFA Classication Editor.
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DFA rule set. A single class line entry in the spreadsheet assumes the rules for each
instance of the 0805 class of package symbols.
Clicking Update on the DFA Classication Editor dialog box assigns the DFA_DEV_CLASS
property to the symbol denitions in the classes you specied.
DRC for DFA
The DRC marker (D-C) for DFA veries DFA spacing rules prior to and after symbol
placement either interactively or in batch mode. When violations occur during manual
placement, the D-C marker and DFA extents appear in the color assigned to DFA DRC in the
Color dialog box. DFA DRCs appear in Constraint Manager in the DRC workbook under the
Design worksheet. DFA DRC supports alternate symbols.
For example, a DFA DRC error appears in error reports as:
DIP14-DIP14 violated 100:200:100 rule.
DFA DRC determines the correct rule set by checking:
I Dened DFA rules in the DFA Constraints Dialog spreadsheet for the associated symbol
denition
I The DFA_DEV_CLASS property assigned to symbol denitions and DFA rules in the
DFA tables
You can choose to enable or disable DFA rules checking independently of existing package-
to-package rules checking on the Design Constraints dialog box, accessed by running (cns
design command) in Allegro PCB Editor. DFA DRC occurs in conjunction with batch
package-to-package DRCs if you:
I Enable DFA checking on the DFA Constraints Dialog spreadsheet
I Create DFA place-bounds for the symbol, enable DFA checking, and an entry exists in
the DFA Constraints Dialog spreadsheet
Note: When one or both symbol denitions lack DFA place-bounds, DRC uses the
existing place-bound and generates a warning. You can generate DFA place-bounds for
legacy symbols automatically using dfa_update.
I Assign the HEIGHT property to either package
During manual placement, as a dynamic component approaches placed components DFA
place-bound extents, DRC runs based on the correct S-S, E-E, S-E value in the DFA
Constraints Dialog spreadsheet. Spacing circles appear on screen between the components
to show the actual spacing value visually, and to highlight potential DFA DRC errors in the
color you assigned for DRCs.
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If a violation occurs, Allegro PCB Editor calculates the DFA extent on all placed components
that come within the range of potential DFA DRC errors, and a DRC marker displays there.
Note: To remove the butterfy fromappearing with the spacing circles, use Setup User
Preferences (enved command) and enable the no_dfa_drc_marker variable.
This DRC and DFA place-bound extents remain highlighted until you move the component
from the violation extent area; the spacing circles then disappear as well. If you move
components, DRCs become out of date for DFA errors.
DFA place-bounds
You can create DFA place-bound shapes in Symbol mode as you do place-bound shapes
using the package_bound command. Place-bound rectangles are lled rectangles that
dene the package boundary and govern placement restrictions. Placement tools use these
rectangles for overlapping and mechanical restraints. DRC also uses them to check for
violations of package-to-package keepin areas and keepout areas. For legacy symbols, you
can add the DFA place-bound to the symbol denition, with dfa_update.
A rectangular-shaped DFA place-bound differs from a place-bound in that the former has
differentiating edges and ends to comply with DFAspacing rules. For circles or polygons, DFA
DRC uses the largest, or most conservative, value specied in the DFA Constraints Dialog
spreadsheet for that symbol if three values exist. Unlike current place-bounds, which allow
you to concatenate multiple shapes, each layer allows only one shape for a DFA place-bound.
Allegro PCB Editor determines the DFA place-bound end, which comprises the shorter sides
of the extent at a zero degree rotation; side as the longer sides of the extent.
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Figure 2-2 DFA place-bound Description
In the example below, the DFA place-bound surrounds the package pins, but with respect to
the assembly outline in blue.
Figure 2-3 DFA place-bound: SOIC
0 rotation angle
END
SIDE
DFA place-bound
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In the example below, the red outline surrounds the package pins, including ducials.
Figure 2-4 DFA place-bound: BGA
DFA place-bounds, created on DFA_BOUND_TOP and DFA_BOUND_BOTTOM layers of
the PACKAGE GEOMETRY class, follow the symbol rotation as Figure 2-5 on page 24
shows.
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Figure 2-5 DFA place-bound Rotation Rules
S
S
S
S
S
S
E E
E
E
E
E
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Using Batch-Mode DFA Analysis
Allegro PCB Editor provides batch-mode DFA analysis on a printed circuit board with a set of
audits for which you can specify constraints, and dene and prioritize them if necessary.
DFA allows you to run the following audits:
I Component clearance
I Component orientation and mounting layer
I Lead span
I Hole
I Testability
I Orphan via
I Hanging trace
Running these audits enables you to verify that your design adheres to a particular set of
constraints. After performing the audits, you can viewthe violations written back to the design
as DRCs; you can cross-probe and highlight the violations in Allegro PCB Editor using the
markers utility.
Figure 2-6 depicts the typical use model of batch-mode DFA. Batch-mode DFA can be
performed anytime after placing components on your design.
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Figure 2-6 Overview of Batch-Mode DFA Analysis
Define constraints for
assembly/fabrication
techniques.
Save sets of constraints
to apply to designs.
Choose audits to run on
your design.
Perform the audits.
View violations
Violations
present?
No
Yes
DRCs
dfa.mkr
dfa.msg
Correct violations.
Process complete
Prioritize constraints.
Add, delete, or restore
constraint set values.
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Dening Constraints
Constraints are dened in the DFA Audit Setup dialog box, and constraint sets must be
dened for each audit as the rst step in the DFA process. For details, see Creating
Specialized Constraints for DFA Check in the Allegro PCB and Package Physical Layout
Command Reference.
Prioritizing Constraints
Allegro PCB Editor provides a default for the audits that support prioritization. Details are
provided for all audits. Typically, you assign generalthat is, non-specializedconstraint
values to the default set (also known as a child item). In the case of the Component
Assembly Clearance audit, for instance, the constraints written against the default child item
apply to all components in your design. The default constraint set, therefore, represents the
highest evaluated level of constraints within an audit. Additional child items that you create
from the default (or current) child item should have more specialized constraints associated
with them.
During an audit, Allegro PCB Editor evaluates specialized constraint sets before less
stringent constraints in a bottom-to-top order. You can maintain this progression of less
stringent to more stringent constraints by inserting new or modied constraint sets between
existing ones.
Each child item in an audit can be considered a place holder for the constraints associated
with it. The most general constraintdefaultmust be at the top of the list of child items in
audits that require prioritization of constraints because Allegro PCB Editor evaluates
constraints from bottom to top. When Allegro PCB Editor nds a match for a specialized
constraint, higher levelmore generalizedconstraints are not evaluated. The audits that
require prioritization are:
I Component Assembly Clearance
I Component Orientation and Mounting Layer
I Lead Span
I Hole Audit
I Test Point Audit
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Saving Constraints
After you have dened a new set of constraints in the DFA Audit Setup dialog box, save the
constraint set by clicking the Save button in the main dialog box (Design For Assembly).
Clicking Save opens a constraint le browser.
The information entered in the Audit Setup dialog box can be written to a newor existing.par
le and is read when future audits of that constraint set are performed.
Note: Clicking the OK button in the Audit Setup dialog box saves the modied constraints in
the directory pointed to by the browser, then closes the dialog box. Clicking Cancel closes
the dialog box, discarding the changes made in that session.
All the DFA constraint les are ASCII les, thus they can be edited; however, we recommend
that changes made to constraints be performed in the Audit Setup dialog box. Constraint les
are structured in the following format:
STARTENV DFA
STARTRULE component_orientation_layer_audit
PARAM SELECTOR_TYPE_ "Component"
PARAM SELECTOR_NUMBER_ 1
PARAM PARAMETER_TYPES_ "S" , "S" , "S" , "NL"
PARAM PARAMETER_WIDGETS_ "P" , "E"
PARAM PARAMETER_POPUPS_ "POPUP_LAYER"
PARAM CONSTRAINTS "Constraint_1" , "smd2smd" , "Default"
PARAM SELECT_BY1 "Symbol" , "Property" , "Any"
PARAM VALUE1 "ocs" , "DFA_DEV_CLASS=ALL" , "*"
PARAM LAYER "BOTTOM" , "TOP" , "Either"
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PARAM ORIENTATION "90" , "0" , "0 90 180 270"
ENDRULE
STARTRULE test_point_audit
PARAM MIN_SIZE 50
PARAM MAX_SIZE 100
ENDRULE
ENDENV
The sample above denes the:
I Environment in which the le is to be used
I Constraints and their values
I Prioritization of constraints (where supported)
The default dfa_constraints.par le exists in $CDS_INST_DIR/share/pcb/
assembly.
Selecting the Audits To Run
Choose the audit and the child item(if prioritization is supported) in the Setup dialog box. The
lower portion of the dialog box displays the constraint values associated with your selection.
For details, see the dfa command in the Allegro PCB and Package Physical Layout
Command Reference.
Performing the Audit
Run the audit(s) from Allegro PCB Editor with the dfa command. Make sure you have set
all parameters to your satisfaction, and you have chose the appropriate audit(s) to run.
When you run an audit on a constraint set, the following les are created in the design
directory:
I dfa.msg
I dfa.log
I dfa.mkr
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The message, log, and marker les are updated automatically and contain the violations that
were generated during the most recent audit. Move/copy or rename les generated earlier for
purposes of comparisons with more recent runs.
Viewing Violations and Reports
DFA assumes a default value of 200 violations. You can reset the maximum by assigning a
specic number as a property value, or by entering a value in the DFA dialog box.
You can view violations in two ways: on the board itself as DRCs or from the dfa.mkr le
through the markers utility (when you click the Explore Violations button in the DFA dialog
box). Clicking on a violation in the markers window highlights the violation in Allegro PCB
Editors working area. All DFADRCs are cleared fromthe board at the beginning of each audit
session.
Clicking the Report button in the DFA dialog box lets you view the dfa.msg le containing
details of every violation. The dfa.log le provides details of the audit process.
Completing the Process
If violations are present after running the audit, make the necessary corrections, then run the
audit again. Perform this step until your board is free of violations.
DFA Audit Descriptions
This section contains information on each of the DFA audits. The accompanying illustrations
depict the Audit Setup dialog box as congured for the separate audits.
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Component Assembly Clearance
This audit checks the spacing between the components to accommodate assembly,
inspection, and repair. A group of components can be chosen by dening a selection criteria
using the Select By and Value elds. These values are described in Allegro PCB Editor
online Help.
The Component Assembly Clearance audit supports prioritization of constraints. Distance is
calculated in user-dened design units.
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Example
Two child items, Default and ResToIC, exist in the Component Assembly Clearance Audit in
the order shown. The value of each eld in the constraints section of the Audit Setup dialog
box is
:
In the example, the minimum distance between any two components on any layer is 1200
design units. The minimum distance between any resistor component with a reference
designator (refdes) Rand any ICwith a reference designator Uon the top layer is 1000 design
units.
When you run the audit, DFA checks for a minimum spacing of 1000 design units between
resistors and ICs on the top layer. All other elements are checked for a minimum spacing of
1200 design units. If the priority is reversedif ResToIC is moved to the topthe audit rst
checks for a minimum spacing of 1200 design units between any two components, and the
ResToIC constraint is never checked.
Error Messages
The error message generated by the audit is:
ERROR (component_clearance_audit)
Clearance between components U23 and C32 : 50
Minimum clearance required : 100
Categories used are category1: RefDes * category 2: RefDes *
ERROR (component_clearance_audit)
Clearance between components C32 and U23 : 50
Minimum clearance required : 100
Categories used are category1: RefDes * category 2: RefDes *
ERROR (component_clearance_audit)
Clearance between components U12 and U21 : 25
Child
Item
Comp1 Value1 Edge1 Comp2 Value2 Edge2 Layer Spacing
Default All * Any All * Any Any 1200
ResToIC RefDesR * Any RefDesU * Any Top 1000
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Minimum clearance required : 100
Categories used are category1: RefDes * category 2: RefDes *
ERROR (component_clearance_audit)
Clearance between components U21 and U12 : 25
Minimum clearance required : 100
Categories used are category1: RefDes * category 2: RefDes *
Component Orientation and Mounting Layer
This audit checks that component orientation is correct for the soldering process used, and
that components are mounted only on allowed layers.
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A group of components can be chosen by dening a selection criteria. Refer to the Allegro
PCB and Package Physical Layout Command Reference for descriptions of eld
selection values and criteria. Prioritization of constraints is supported.
Example
The audit has two child items: Default and Resistor. The value of each eld in the constraints
section of the Audit Setup dialog box is
:
All resistors on the bottom layer should have an orientation of 90 or 270 degrees. Any
component on the top layer should have an orientation of 0 or 180 degrees. The parameters
of this audit specify that only resistors are allowed on the bottom layer.
If the two items were reversed, all components should be present on the top layer with allowed
orientations of 0 or 180 degrees. Resistors on the bottom layer generate error messages.
The error messages generated by the audit are:
"ERROR : Component mounted on the wrong layer "
Component : 'R1'
Layer : TOP
Allowed Layer : BOTTOM
Constraint name : Constraint_1
ERROR : Component has wrong orientation"
Component :'U2'
Orientation : 0
Allowed Orientation : 90 180
Constraint name : Default
Child Item Select By Value Layer Orientation
Default All * Top 0
Resistor RefDesR * Bottom 90
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Lead Span
Axial components must be able to t into the holes at the span dened in the symbol. This
audit veries the span values for components. Allowed span values can be specied by list
or by equation.
The value list is entered on a separate formfor both the options; that is, selecting span values
by list, or by equation (shown above). Refer to the online Help for descriptions of eld
selection values and criteria. Prioritization of constraints is supported.
If span value checking is by list, the component span is the distance between the two pads of
the component. With this method, you enter a space-separated list in the span value list eld.
The actual component span should match one in the list.
If the span value is calculated by equation, the equation used for determining the span values
is
:X*Body Length + Y * LEAD_DIAMETER + Z
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where X, Y, Z are constants which can be customized. The Base-Increment value list eld
has a space separated list of base increment pairs in the format base:increment. The actual
span value is checked against the base:increment pair.
Example
Assume that X=Y =1 and Z=100 mils. Base: Increment = 300:100. Let the component span
evaluate to 750 mils. The allowable span values are 300, 400, 500, 700, 700, 800 etc. Since
750 >700 and 750 < 800, the allowable span value is 800. So the actual pad-to- pad distance
is checked against this value.
The audit is applied only to axial components where axial components are dened as
package symbols with attached property DFA_DEV_CLASS and two pins with attached
property LEAD_DIAMETER (when span values are chosen by equation).
The error message generated by the rule is:
"ERROR : Component does not have standard span value"
"ERROR (lead_span_audit)
Allowed span value(s) : 200
Component : 'C91'
Span Value : 140
Body Length : 170
Span value specified : By Equation
Constraint name : Default
ERROR (lead_span_audit)
Allowed span value(s) : 205 220 220
Component : 'C94'
Span Value : 140
Body Length : 170
Span value specified : By List
Constraint name : Default
Orphan Via
Choose this audit to report on vias that meet both of the following criteria:
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I The via has no clines connected to it.
I The via is not on a net.
Hole
This audit:
I Veries all pads have the minimum annular ring width
I Allows only permissible drill sizes in the design
I Checks minimum/maximum via size and whether duplicate holes are present in the
same location
The audit reports the number of unique drill sizes in the design.
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Refer to the Allegro PCB and Package Physical Layout Command Reference for details
of eld parameter values.
The error messages generated by this rule are:
INFO (hole_audit)
Maximum via size : 2
Following vias violate this criteria:
VIA1@(1000.0 2260.0) 14
VIA1@(800.0 2540.0) 14
VIA1@(1920.0 2560.0) 14
VIA1@(2120.0 2260.0) 14
INFO (hole_audit)
Minimum via size : 30
Following vias violate this criteria:
VIA1@(1000.0 2260.0) 14
VIA1@(800.0 2540.0) 14
VIA1@(1920.0 2560.0) 14
VIA1@(2120.0 2260.0) 14
ERROR (hole_audit)
Preferred plated hole size(s) : 5 6 7.
The following vias violate this criteria:
VIA1@(1000.0 2260.0) 14
VIA1@(800.0 2540.0) 14
VIA1@(1920.0 2560.0) 14
VIA1@(2120.0 2260.0) 14
ERROR (hole_audit)
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Preferred plated hole size(s) : 5 6 7.
The following pins violate this criteria:
R1.2 14
R2.2 14
R2.1 14
R1.1 14
ERROR (hole_audit)
Minimum annular ring size for pads is 8.
The following vias violates this criteria:
VIA1@(1000.0 2260.0) 3
VIA1@(800.0 2540.0) 3
VIA1@(1920.0 2560.0) 3
VIA1@(2120.0 2260.0) 3
ERROR (hole_audit)
Minimum annular ring size for pads is 8 .
The following pins violates this criteria:
R1.2 3
R2.2 3
R2.1 3
R1.1 3
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Testability
This audit checks for test points under components, the minimum/maximum size of test
points, and tented test points (test points covered by solder mask).
A test point is dened as a pin/via with the attached property TESTPOINT and a value ETCH/
<SUBCLASS> placed on it, where <SUBCLASS> can be either top or bottom.
The error messages generated by this rule are:
ERROR(test_point_audit): Test point found under component
The following components have test points under them:
U1 via1(70,85)
U2 via2(30,908)
ERROR(test_point_audit):Test point size less than minimum
Minimum test point size : 30
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Following vias violate this criteria:
VIA1@(1000.0 2260.0) 3
VIA1@(800.0 2540.0) 3
VIA1@(1920.0 2560.0) 3
ERROR(test_point_audit):Test point covered by Solder Mask
The following test points are covered by solder mask:
VIA1@(1000.0 2260.0)
VIA1@(800.0 2540.0)
Hanging Trace
Choose this audit to report on cline segments that do not have a net assigned to them.
Note: Cline segments assigned to dummy nets are not considered hanging traces, and this
audit does not report them.
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3
Extracting Allegro PCB Editor Views
Allegro PCB Editors extracta command reads binary representations of Allegro PCB
Editor designs, then translates that data into ASCII text les. These les contain database
information you can sort and format for reporting and analyzing.
The extracta command is specic to the Allegro PCB Editor database; however, it
produces data in a formthat standard processing programs can use. Figure 3-1 illustrates the
ow of data in the extract process.
You control extracta by creating an extract command le that extracta uses as input. In
the extract command le, you list those data elds you want extracted from the Allegro PCB
Editor database and establish selection criteria for certain data values. The information you
provide is called a view. The extracta command provides predened views from which
you can choose (baseview les). You can also customize views, and extract multiple views.
The extracta command creates an output le of the information you specied in the
command le. The output le is composed of many text record representations of the
database that you specied to extracta. You can rerun extracta, specifying other
database elements to obtain a different view of the database.
In addition to the output le, extracta creates a log le named extracta.log, which
contains a copy of the control le, as well as any error messages.
Although the extract command can be run any time during the design process, normally you
run it on a completed design. Extracting data views involves the following tasks:
I Creating an extract command le
I Running extracta
I Formatting the output le
See the extracta command in the Allegro PCB and Package Physical Layout
Command Reference for information on these procedures.
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Figure 3-1 Data Flow for the extracta Command
Important
In versions prior to 14.2, the extracta program was called extract. If you are
operating on a UNIX platform, Cadence provides a link to the old extract name so
you do not need to change your scripts.
This is not the case on Windows platforms. If you are operating on a Windows
system, you must create new scripts for use with extracta.
Extract Command File Format
The extract command le contains a number of records. Each record is a line of the text le
(terminated by an end-of-line character). The following rules apply:
I extracta ignores blank lines.
I extracta ignores preceding or trailing white space, as well as white space around the
selection record operator (= or !).
I You can enclose eld names or values in single or double quotes.
I Field names, view names, and the OR and END keywords can be in uppercase or
lowercase.
The case of eld values is left unchanged.
<command.txt>
Allegro PCB Ed-
itor design
database
(.brd file)
extracta
<output.txt>
<extract.log>
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I Two successive single (or double) quotes means a null string.
A null string is needed to choose records that have a data eld with a null (non-existent)
value.
For example, the x and y coordinates of a components symbol are written as a null value
if the component is not placed.
Table 3-1 Record Types
Comment Records Lines that start with a pound sign (#). Comments are not
processed but are written to the log le.
Viewname Record The rst line in the leor following an END recordthat is not
a comment record or blank line. The record contains the name
of the view that denes the type of element to be extracted. For
example:
COMPONENT
The view name is edit checked. Descriptions of the view are
provided later in this chapter.
Data Field Record Each line that is not a comment, viewname, selection, or OR
and END record contains the name of a data eld in the
database. For example:
COMP_CLASS
SYM_NAME
Each occurrence of a data eld record causes a eld to be
written to the text le for each entity. The names of the data
elds specied are included in the rst header record of the
output le. The data eld name is checked for validity. See
Extract Data Dictionary for legal data eld names.
Selection Records Any record that contains an equal sign (=) is a selection record.
The format of the selection record is <data_eld> <operator>
<data_value>, where <operator> is either = (equal) or != (not
equal). Do not include a space between the ! and =. Multiple
selection records are implicitly treated as an AND, that is, a
record is chosen only if all selection statements are TRUE.
For example, to specify legal class and subclass values for a
lter, type the following:
CLASS = DRAWING FORMAT
SUBCLASS = TITLE_BLOCK
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Property Names
Property names can be added to command les in the form of data eld records when you
want to extract a property from any element that might have that property, or from a specic
element type in the view. In your command le, you can specify a property to be extracted by
I Specifying the property name alone (Example 1)
I Combining the property with an object type (Example 2)
Example 1: Property extract
The following example command le requests extracta to write out the MIN_LINE_WIDTH
property value, a property that may be attached either to clines or nets. With only this
information, extracta looks for the property on both the cline and the net that owns the
cline, searching in that order. The cline property supercedes the net property in the output.
Example 2: Object type property extract
Specifying <object_type> and <property_name> causes extracta to look for the
property only on that object type, where <object_type> is BOARD, SYM, COMP, FUNC,
GEO, NET, PIN, or VIA and <property_name> is the name of the property to be extracted.
OR Record A record with only the word OR. The OR record is used to make
choose statements connected with an OR rather than the
implicit AND. If an entity does not satisfy the selection criteria of
the choose statement(s) before the OR, then those after the
ORand before the next ORare evaluated.
#ExtractMIN_LINE_WIDTH,
#wherever it may be:
GEOMETRY
CLASS
SUBCLASS
RECORD_TAG
GRAPHIC_DATA_NAME
GRAPHIC_DATA_NUMBER
GRAPHIC_DATA_1
GRAPHIC_DATA_2
MIN_LINE_WIDTH
END
Property extract
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This example asks for the net MIN_LINE_WIDTH property. In this case, extracta extracts
the property only if it is attached to the net:
For more information on properties and their denitions, see the Allegro Platform
Properties Reference.
Property Search Hierarchy
When looking for a property that does not have an <object_type> qualier in the command
(and therefore may be found on any object in the view), extracta searches the view objects
fromthe bottomup. It rst looks for the property on objects owned by the view object, then on
the view object itself.
Table 3-2 shows the hierarchical order extracta uses when searching for a property. It also
shows the prex you attach to a property name in the command le when you want the
property to be found only on a particular element types. The extracta program searches
for the property from the top of the list.
Table 3-2 Hierachical Order the extract Command Uses
Element Type Prex Name
1. Standalone Pin
PIN_
2. Symbol Pin
PIN_
3. Function Pin Instance
PIN_
4. Function Pin Denition
PIN_
5. Component Pin Denition
PIN_
# Extract MIN_LINE_WIDTH if attached to the net
GEOMETRY
CLASS
SUBCLASS
RECORD_TAG
GRAPHIC_DATA_NAME
GRAPHIC_DATA_NUMBER
GRAPHIC_DATA_1
GRAPHIC_DATA_2
NET_MIN_LINE_WIDTH
END
Net property extract
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Group Properties
You can extract the properties attached to groups by adding a GRP_ prex to the property
name and including the eld in one of the base views. For example:
NET
GRP_TOTAL_ETCH_LENGTH
END
This extracts a record for every net in the design and indicate which nets belong to a group
that has a TOTAL_ETCH_LENGTH property attached.
6. Via
VIA_
7. Line
GEO_
8. Cline
GEO_
9. Void
GEO_
10. Shape
GEO_
11. Rectangle
GEO_
12. Filled Rectangle
GEO_
13. Figure
GEO_
14. Text
GEO_
15. Net
NET_
16. Group
GRP_
17. Symbol Instance
SYM_
18. Symbol Denition
SYM_
19. Function Instance
FUNC_
20. Function Denition
FUNC_
21. Component Instance
COMP_
22. Component Denition
COMP_
23. Board
BOARD_
Element Type Prex Name
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Multiple Views
You can extract multiple views by using multiple END records in the extract command le.
The END record delimits multiple extracts from a single command le. An END causes the
extracta program to be started with the current view and elds. After completion, it reads
the next line in the command le.
Note: Succeeding data acquired fromthe database with the extracta command is written
to the corresponding output le from the command line. Therefore, when extracting multiple
views, you must specify multiple output le names.
The following is a sample extract le using multiple views:
# Note:
# This command file contains two views:
# component and component_pin
#
COMPONENT
#
COMP_PACKAGE
COMP_DEVICE_TYPE
COMP_VALUE
COMP_TOL
REFDES_SORT
REFDES
#
END
#
# component pin view for the pin data
#
COMPONENT_PIN
#
REFDES !=
NET_NAME !=
#
NET_NAME_SORT
NET_NAME
REFDES_SORT
REFDES
PIN_NUMBER_SORT
PIN_NUMBER
#
END
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SORT Data Fields
You can sort extracted data les with these data elds:
I FUNC_DES_SORT
I NET_NAME_SORT
I PIN_NUMBER_SORT
I REFDES_SORT
The extracta command derives each of these data elds from its corresponding original
data eld (for example, FUNC_DES_ SORT fromFUNC_DES) by separating the eld into an
alphabetic and numeric subeld, and expanding the numeric subeld to a wide, right-justied
eld. This assures that a standard sort of the le results in a reasonable sort order. For
example, the function designators FUNC1, FUNC2, FUNC3, and FUNC10 sort to:
I FUNC1
I FUNC10
I FUNC2
I FUNC3
Note: When using the standard ASCII sort command, all 1s in each column must precede
all 2s, and so on. The _SORT data elds overcome this problemby transforming the function
designators: FUNC1 to FUNC 00000001, FUNC2 to FUNC 00000002, FUNC3 to FUNC
00000003, FUNC10 to FUNC 00000010, and so on. This results in a sort to:
I FUNC 00000001
I FUNC 00000002
I FUNC 00000003
I FUNC 00000010
Use the _SORT elds by putting both the data elds _SORT and the data eld name itself
in your command le. Make sure to put the _SORT data eld name rst, so that it controls
the sort ordering. You can then read the corresponding (untransformed) FUNC_DES data
eld itself for display and printing.
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Baseview Files
Allegro PCB Editor provides a number of text les that contain chosen data elds, called
baseview les. Baseview (_bv) les are located at \cds\share\pcb\text\views in
the install directory of Allegro PCB Editor.
Baseview les can assist you in writing a command le since, typically, only one type of data
is extracted from your design. For example, all component reference designators or all
symbol pin x-y coordinates. As baseview les contain all the basic data elds associated with
a particular view, you can include any number of data elds related to an element by simply
copying part or all of a .bv le and pasting it into your command le. You can then enter
specic values for the data elds (pins with pin number = 1, drill size =.029, and so on). You
can also combine selection records.
You can extract data using any one of these predened views:
Extract Data Dictionary contains all the data elds that you can extract and the views in which
they are available.
VIEW BASEVIEW FILE
BOARD board_bv.txt
COMPONENT comp_bv.txt
CONNECTIVITY conn_bv.txt
COMPOSITE_PAD cpad_bv.txt
COMPONENT_PIN cpin_bv.txt
FULL_GEOMETRY fgeo_bv.txt
FUNCTION func_bv.txt
GEOMETRY geo_bv.txt
LAYER layer_bv.txt
LOGICAL_PIN lpin_bv.txt
NET net_bv.txt
RAT_PIN rat_bv.txt
SYMBOL sym_bv.txt
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Baseview File Contents
The following sections show the contents of the baseview les in Allegro PCB Editor.
BOARD
This view extracts the basic data about the design extents and scaling. extracta supplies
the data automatically as the second J record of every extraction, so you usually do not need
to extract the data with a separate view le.
#
# board_baseview - basic fields for the BOARD view
#
BOARD
BOARD_NAME
BOARD_ACCURACY
BOARD_UNITS
BOARD_EXTENTS_X1
BOARD_EXTENTS_Y1
BOARD_EXTENTS_X2
BOARD_EXTENTS_Y2
BOARD_LAYERS
BOARD_THICKNESS
BOARD_DRC_STATUS
BOARD_SCHEMATIC_NAME
BOARD_BOARD_THICKNESS
END
COMPONENT
This view extracts components in the design. The basic identier of each record is the
reference designator of the component.
COMPONENT
REFDES_SORT
REFDES
COMP_CLASS
COMP_PACKAGE
COMP_DEVICE_TYPE
COMP_VALUE
COMP_TOL
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COMP_MAX_POWER_DISS_DEVICE
COMP_MAX_POWER_DISS_INSTANCE
COMP_ALT_SYMBOLS
COMP_AUTO_RENAME
COMP_COMPONENT_WEIGHT
COMP_DENSE_COMPONENT
COMP_DEVICE_LABEL
COMP_FIX_ALL
COMP_HARD_LOCATION
COMP_HEIGHT
COMP_INSERTION_CODE
COMP_MAX_POWER_DISS
COMP_NO_MOVE
COMP_NO_PIN_ESCAPE
COMP_NO_ROUTE
COMP_NO_SWAP_COMP
COMP_NO_SWAP_GATE
COMP_NO_SWAP_GATE_EXT
COMP_NO_SWAP_PIN
COMP_PART_NUMBER
COMP_PIN_ESCAPE
COMP_PLACE_TAG
COMP_ROOM
COMP_TERMINATOR_PACK
COMP_VOLTAGE
COMP_VOLT_TEMP_MODEL
COMP_WIRE_BOND
END
COMPONENT_PIN
This view extracts pins of components in the drawing. The basic identier of each record is
the reference designator and pin number of the component pin. The difference between the
COMPONENT_PIN view and the LOGICAL_PIN view (described later in this chapter) is that
the COMPONENT_PIN view does not include pins of functions not yet assigned to
components. Also, common pins (shared between functions) only occur once in the
COMPONENT_PIN view, whereas they will occur once per function in the LOGICAL_PIN
view.
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This view differs from the COMPOSITE_PAD view (described next) in that there are no vias
(or stand-alone pins) included in this view. Also, pins of unplaced components are included
in this view and not in the COMPOSITE_PAD view.
COMPONENT_PIN
REFDES_SORT
PIN_NUMBER_SORT
REFDES
PIN_NUMBER
PIN_X
PIN_Y
PIN_EDITED
PIN_COMMON_CODE
PIN_SWAP_CODE
PIN_TYPE
PAD_STACK_NAME
NET_NAME
PIN_FLOATING_PIN
PIN_GROUND
PIN_NC
PIN_NO_PIN_ESCAPE
PIN_NO_SHAPE_CONNECT
PIN_NO_SWAP_PIN
PIN_PAD_STACK_NAME
PIN_PINUSE
PIN_PIN_ESCAPE
PIN_POWER
END
COMPOSITE_PAD
This view extracts pad data fromsymbol pins and vias in the design. You can use this view to
get padstack and drill hole data.
COMPOSITE_PAD
CLASS
PAD_STACK_NAME
PAD_STACK_INNER_LAYER
PAD_STACK_TYPE
GRAPHIC_DATA_NAME
GRAPHIC_DATA_NUMBER
GRAPHIC_DATA_1
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GRAPHIC_DATA_2
GRAPHIC_DATA_3
GRAPHIC_DATA_4
START_LAYER_NAME
START_LAYER_NUMBER
END_LAYER_NAME
END_LAYER_NUMBER
REFDES
PIN_NUMBER
PIN_X
PIN_Y
TEST_POINT
VIA_MIRROR
VIA_X
VIA_Y
NET_NAME
DRILL_HOLE_NAME
DRILL_HOLE_X
DRILL_HOLE_Y
DRILL_HOLE_PLATING
DRILL_ARRAY_ROWS
DRILL_ARRAY_COLUMNS
DRILL_ARRAY_CLEARANCE
DRILL_ARRAY_LOCATIONS
DRILL_FIGURE_CHAR
DRILL_FIGURE_SHAPE
DRILL_FIGURE_WIDTH
DRILL_FIGURE_HEIGHT
DRILL_FIGURE_ROTATION
VIA_NO_SHAPE_CONNECT
VIA_PAD_STACK_NAME
END
CONNECTIVITY
This viewextracts data about electrical connections. The nets in the design are used to create
records that represent a node or a connection. A node refers to the pins, vias, and Ts that are
part of a logical net. A connection refers to ratsnest or etch geometry. The CONNECTIVITY
baseview contains the following elds:
CONNECTIVITY
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#
NET_NAME !=
RAT_CONNECTED != YES
#
NET_NAME_SORT
NODE_SORT
NODE_1_NUMBER
NODE_2_NUMBER
RECORD_TAG
CLASS
SUBCLASS
NET_NAME
GRAPHIC_DATA_NAME
GRAPHIC_DATA_NUMBER
GRAPHIC_DATA_1
GRAPHIC_DATA_2
GRAPHIC_DATA_3
GRAPHIC_DATA_4
GRAPHIC_DATA_5
GRAPHIC_DATA_6
GRAPHIC_DATA_7
GRAPHIC_DATA_8
GRAPHIC_DATA_9
GRAPHIC_DATA_10
NODE_CONNECTS
RAT_CONNECTED
REFDES
PIN_NUMBER
PIN_TYPE
PIN_X
PIN_Y
VIA_X
VIA_Y
VIA_MIRROR
PAD_STACK_NAME
START_LAYER_NAME
END_LAYER_NAME
COMP_DEV_TYPE
COMP_TERMINATOR_PACK
COMP_VALUE
SEG_CAPACITANCE
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SEG_INDUCTANCE
SEG_IMPEDANCE
SEG_PROPAGATION_DELAY
SEG_RESISTANCE
END
FULL_GEOMETRY
This view contains the data in the GEOMETRY view plus detailed pad data. Pad data is
dened as the actual pad in use for each subclass of a pin or via.
Standard geometries have the appropriate geometry (for example, CIRCLE) as the
GRAPHIC_DATA_NAME, as well as their PAD_SHAPE_ NAME.
Pads that are arbitrary shapes are presented as a shape. The GRAPHIC_DATA_NAME is
LINE (or ARC), and GRAPHIC_DATA_10 is SHAPE. Additionally the
PAD_SHAPE_NAME eld contains the shape symbol name (preceded by FIG_SHAPE and
space). The SYM_TYPE and SYM_NAME elds still reect information about the parent
symbol for pins and are empty strings for vias.
FULL_GEOMETRY
CLASS
SUBCLASS
RECORD_TAG
GRAPHIC_DATA_NAME
GRAPHIC_DATA_NUMBER
GRAPHIC_DATA_1
GRAPHIC_DATA_2
GRAPHIC_DATA_3
GRAPHIC_DATA_4
GRAPHIC_DATA_5
GRAPHIC_DATA_6
GRAPHIC_DATA_7
GRAPHIC_DATA_8
GRAPHIC_DATA_9
GRAPHIC_DATA_10
REFDES
PIN_NUMBER
PAD_STACK_NAME
PAD_SHAPE_NAME
PAD_TYPE
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PAD_FLASH
DRILL_HOLE_X
DRILL_HOLE_Y
SYM_NAME
SYM_TYPE
NET_NAME
PIN_X
PIN_Y
VIA_X
VIA_Y
SEG_CAPACITANCE
SEG_IMPEDANCE
SEG_INDUCTANCE
SEG_PROPAGATION_DELAY
SEG_RESISTANCE
END
FUNCTION
This view extracts functions in the drawing. The basic identier in this view is the function
designator. If the function is assigned to a component, you can extract any of the components
data elds. If the component, in turn, is placed, you can extract any of the symbols data elds.
FUNCTION
FUNC_DES_SORT
FUNC_DES
COMP_DEVICE_TYPE
FUNC_TYPE
REFDES
FUNC_SLOT_NAME
FUNC_SPARE_FLAG
FUNC_GROUP
FUNC_HARD_LOCATION
FUNC_LOGICAL_PATH
END
GEOMETRY
This view extracts geometric elements of the designthe absolute coordinates of each
element, formatted into data elds named GRAPHIC_DATA_n elds. Each n eld has a
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different meaning depending on the type of geometric element it describes. See Extract Data
Dictionary for a complete listing.
You can also extract any of the properties attached to any geometric element. For example,
you can use GEOMETRY view data to extract the following:
I Design outline data for N/C router programming
I Types of geometry on an etch layer for translation to other systems, such as mechanical
analysis systems
GEOMETRY
CLASS
SUBCLASS
RECORD_TAG
GRAPHIC_DATA_NAME
GRAPHIC_DATA_NUMBER
GRAPHIC_DATA_1
GRAPHIC_DATA_2
GRAPHIC_DATA_3
GRAPHIC_DATA_4
GRAPHIC_DATA_5
GRAPHIC_DATA_6
GRAPHIC_DATA_7
GRAPHIC_DATA_8
GRAPHIC_DATA_9
GRAPHIC_DATA_10
REFDES
NET_NAME
SYM_NAME
COMP_DEVICE_TYPE
SEG_CAPACITANCE
SEG_INDUCTANCE
SEG_IMPEDANCE
SEG_PROPAGATION_DELAY
SEG_RESISTANCE
GEO_FILLET
GEO_SYMBOL_ETCH
END
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LAYER
This view extracts data about the physical layers (for example, etch, multiwire, or dielectric)
in the design. Layer information is obtained from the Cross Section parameter form.
LAYER
LAYER_SORT
LAYER_SUBCLASS
LAYER_ARTWORK
LAYER_USE
LAYER_CONDUCTOR
LAYER_DIELECTRIC_CONSTANT
LAYER_ELECTRICAL_CONDUCTIVITY
LAYER_LOSS_TANGENT
LAYER_MATERIAL
LAYER_SHIELD_LAYER
LAYER_THERMAL_CONDUCTIVITY
LAYER_THICKNESS
LAYER_TYPE
END
LOGICAL_PIN
This view extracts function pins in the drawing. The difference between the LOGICAL_PIN
view and the COMPONENT_PIN view (previously described) is that the COMPONENT_PIN
view does not include pins of unassigned functions (functions not assigned to components).
Also, common pins (shared between functions) occur only once in the component pin view,
whereas they occur once per function in the logical pin view. The LOGICAL_PIN view does
not include non-function pins, such as power, ground, and no-connect pins.
LOGICAL_PIN
FUNC_DES_SORT
PIN_NAME
FUNC_DES
REFDES
PIN_NUMBER
PIN_X
PIN_Y
PIN_EDITED
PIN_COMMON_CODE
PIN_SWAP_CODE
PIN_TYPE
PAD_STACK_NAME
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NET_NAME
PIN_FLOATING_PIN
PIN_GROUND
PIN_NC
PIN_NO_PIN_ESCAPE
PIN_NO_SHAPE_CONNECT
PIN_NO_SWAP_PIN
PIN_PAD_STACK_NAME
PIN_PINUSE
PIN_ESCAPE
PIN_POWER
END
NET
This view extracts net information fromthe design. The identier in this view is the net name.
You can use this view to extract all properties related to the nets (but not pins of nets; use
LOGICAL_PIN or COMPONENT_PIN views for that).
NET
NET_NAME_SORT
NET_NAME
NET_STATUS
NET_CAPACITANCE
NET_ETCH_LENGTH
NET_ETCH_WIDTH_AVERAGE
NET_IMPEDANCE_AVERAGE
NET_IMPEDANCE_MAXIMUM
NET_IMPEDANCE_MINIMUM
NET_INDUCTANCE
NET_MANHATTAN_LENGTH
NET_MANHATTEN_LENGTH
NET_PATH_LENGTH
NET_PROPAGATION_DELAY
NET_RESISTANCE
NET_VIA_COUNT
NET_BUS_NAME
NET_PHYSICAL_TYPE
NET_PROPAGATION_DELAY
NET_DIFFERENTIAL_PAIR
NET_DIFFP_2ND_LENGTH
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NET_DIFFP_LENGTH_TOL
NET_DRIVER_TERM_VAL
NET_ECL
NET_ECL_TEMP
NET_EXTERNAL_NOISE
NET_FIXED
NET_LOAD_TERM_VAL
NET_RELATIVE_PROPAGATION_DELAY
NET_MAX_BOND_LENGTH
NET_MAX_BVIA_STAGGER
NET_MAX_EXT_NPOSE
NET_MAX_FINAL_SETTLE
NET_MAX_FIRST_SWITCH
NET_MAX_OHM_LOSS
NET_MAX_OVERSHOOT
NET_MAX_PARALLEL
NET_MAX_PEAK_BXTALK
NET_MAX_PEAK_FXTALK
NET_MAX_PROP_DELAY
MET_MAX_SUM_BXTALK
NET_MAX_SUM_FXTALK
NET_MAX_THERM_SHIFT
NET_MAX_UNDERSHOOT
NET_MAX_VIA_COUNT
NET_MIN_BOND_LENGTH
NET_MIN_BVIA_GAP
NET_MIN_BVIA_STAGGER
NET_MIN_LINE_WIDTH
NET_MIN_NECH_WIDTH
NET_MIN_NOISE_MARGIN
NET_MIN_PROP_DELAYT
NET_NET_PHYSICAL_TYPE
NET_NET_SPACING_TYPE
NET_NO_GLOSS
NET_NO_PIN_ESCAPE
NET_NO_RAT
NET_NO_RIPUP
NET_NO_ROUTE
NET_NO_TEST
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NET_PROBE_NUMBER
NET_RATSNEST_SCHEDULE
NET_ROUTE_PRIORITY
NET_ROUTE_TO_SHAPE
NET_SAME_NET
NET_SPACING_TYPE
NET_STUB_LENGTH
NET_TS_ALLOWED
NET_VIA_LIST
NET_VOLTAGE
NET_WEIGHT
END
RAT_PIN
This view extracts the COMPONENT_PIN view with NET_RAT_ SCHEDULE. This view is
useful for retrieving the ratsnesting for a net.
COMPONENT_PIN
NET_NAME_SORT
NET_RAT_SCHEDULE
NET_NAME
REFDES
PIN_NUMBER
PIN_X
PIN_Y
END
SYMBOL
The basic identier in this view is the symbol name (for example, DIP14). Use this view to
extract symbol data from the design, whether or not the symbol has a component assigned
to it.
SYMBOL
SYM_TYPE
SYM_NAME
REFDES
SYM_BOX_X1
SYM_BOX_X2
SYM_BOX_Y1
SYM_BOX_Y2
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SYM_CENTER_X
SYM_CENTER_Y
SYM_EXTENTS_X1
SYM_EXTENTS_X2
SYM_EXTENTS_Y1
SYM_EXTENTS_Y2
SYM_HAS_PIN_EDIT
SYM_MIRROR
SYM_ROTATE
SYM_X
SYM_Y
SYM_LIBRARY_PATH
SYM_SHAPE_X_OFF
SYM_SHAPE_Y_OFF
END
The extracta Output File
The extracta command generates a text le that contains two header records followed
by one data record per extracted element. Each record in the le starts with a record-type
character.
I The rst record starts with the letter A
I The second record starts with the letter J
I Subsequent records start with the letter S
The reason for these record-type characters is that many processes require you to sort the
le before further processing. Assuming you use a simple ascending, whole-record sort, the
Arecord always sorts to the leading record and the Jrecord next, followed by all the S
records. These characters also allow for the future denition of other types of data records.
The standard separator character between every eld in all records is the exclamation point
(!). Three types of records exist: A, J, and S records.
A Records
The rst record starts with the letter A. This record contains the labels for each data eld
extracta writes in each of the data records of the le. The labels are the same as the data
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eld names in the extracta command le. (Some exceptions include cases where the view
writes a xed set of data elds and their corresponding names to the A record.)
J Records
The second record starts with the letter J. This sample record contains the following global
data about the Allegro PCB Editor design as described in the table.
A!REFDES!COMP_DEVICE_TYPE!
J!name.brd!Mon May 6 15:21:43 2003!0!0!11000!8500!1!mils!MIKEY!35.2876
mil!4!OUT OF DATE!
S!U3!7400!
S!U5!CAPA!
Field position Description Syntax of Example
1 Design name name.brd
2 Extracta execution date Mon May 6 15:21:43 2003
3 Drawing extents of the right x
coordinate: left X
0
4 Drawing extents of the left x
coordinate: lower Y
0
5 Drawing extents of the upper y
coordinate: right X
11000
6 Drawing extents of the lower y
coordinate: upper Y
8500
7 Database accuracy (the user units
of the minimum incremental
distance in the drawing)
1
8 Units of measurement used in the
database as a text string (mils,
millimeters, etc.)
mils
9 Value, if any, of the
BOARD_SCHEMATIC_NAME
property
MIKEY
10 Value, if any, of the
BOARD_THICKNESS property
35.2876 mil
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S Records
Subsequent records in the le start with the letter S and contain the data values for the elds
named in the A-record, in the same order as it gives the names.
Sample Output Files
The examples below illustrate output generated by three command les, extracting data from
the same design database. Note the use of the -t switch in the rst example.
Example 1: Using the GEOMETRY View
The extracta command le brd_outline_view.txt
# View name:
GEOMETRY
# Select:
CLASS = BOARD GEOMETRY
SUBCLASS = OUTLINE
# Requested datafields:
CLASS
SUBCLASS
RECORD_TAG
GRAPHIC_DATA_NAME
GRAPHIC_DATA_NUMBER
GRAPHIC_DATA_1
GRAPHIC_DATA_2
GRAPHIC_DATA_3
GRAPHIC_DATA_4
GRAPHIC_DATA_5
GRAPHIC_DATA_6
GRAPHIC_DATA_7
GRAPHIC_DATA_8
GRAPHIC_DATA_9
END
11 Number of etch/wire layers in the
design
4
12 BOARD_DRC_STATUS eld OUT OF DATE
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when used in the following command:
extracta -t test_board brd_outline_view outline
creates a le called outline.txt:
A!CLASS!SUBCLASS!RECORD_TAG!GRAPHIC_DATA_NAME!GRAPHIC_DATA_NUMBER
!GRAPHIC_DATA_1!GRAPHIC_DATA_2!GRAPHIC_DATA_3
!GRAPHIC_DATA_4!GRAPHIC_DATA_5!GRAPHIC_DATA_6
!GRAPHIC_DATA_7!GRAPHIC_DATA_8!GRAPHIC_DATA_9!
J!/usr2/bud/test_board.brd
!Mon May 6 15:34:52 1991!-1500!-1500!4000!4500!1!mils!!!
S!BOARD GEOMETRY!OUTLINE!7 1!LINE!257!-300!3200!3700!3200!0!!!!!
S!BOARD GEOMETRY!OUTLINE!7 2!LINE!257!-300!1200!-300!3200!0!!!!!
S!BOARD GEOMETRY!OUTLINE!7 3!LINE!257!-200!1200!-300!1200!0!!!!!
S!BOARD GEOMETRY!OUTLINE!7 4!LINE!257!-200!1100!-200!1200!0!!!!!
S!BOARD GEOMETRY!OUTLINE!7 5!LINE!257!3600!1100!-200!1100!0!!!!!
S!BOARD GEOMETRY!OUTLINE!7 6!LINE!257!3600!1200!3600!1100!0!!!!!
S!BOARD GEOMETRY!OUTLINE!7 7!LINE!257!3700!1200!3600!1200!0!!!!!
S!BOARD GEOMETRY!OUTLINE!7 8!LINE!257!3700!3200!3700!1200!0!!!!!S!BOARD
GEOMETRY!OUTLINE!8 1!TEXT!260!300!3000!0.000!NO!LEFT
!8 0 100 75 0.000 25 125 0!BOARD GEOMETRY OUTLINE:!!!
Note: The A-, J-, and the last S-record are broken into several lines for clarity; extracta
never breaks records into multiple lines.
This data can be used to create a numerical control program to drive a routing machine for
cutting boards from raw stock. Note that the outline LINE records all have the same major
element number (7) in their RECORD_TAGdata eld. extracta lists themthis way whether
the lines were added as separate elements or with a single add_line command (unless the
-t option is used).
Example 2: A Formatted Netlist Report
In this example, you can extract data about the pins and their net assignments in the design,
then create a readable netlist report using the sort utility programs. (See SORT Data Fields
for details.)
The extracta command le net_view.txt
#
# View name:
#
LOGICAL_PIN
#
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# Select only non-blank nets:
#
NET_NAME !=
#
# Datafields:
#
NET_NAME_SORT
REFDES_SORT
PIN_NUMBER_SORT
FUNC_DES_SORT
PIN_NAME
REFDES
FUNC_DES
PIN_NUMBER
NET_NAME
# end of net_view.txt
END
when used in the following command:
extracta test_board net_view net_pin
creates a le called net_pin.txt:
A!NET_NAME_SORT!REFDES_SORT!PIN_NUMBER_SORT!FUNC_DES_SORT
!PIN_NAME!REFDES!FUNC_DES!PIN_NUMBER!NET_NAME!
J!/usr2/bud/test_board.brd!Mon May 6 09:22:02 1991
!-1500!-1500!4000!4500!1!mils!!!
S!TP 00000001!TP 00000001! 00000001!F 00000009!CON
PIN!TP1!F9!1!TP1!
S!TN- 00000006!R 00000001! 00000002!F 00000001!B!R1!F1!2!TN-6!
S!TN- 00000005!R 00000001! 00000001!F 00000001!A!R1!F1!1!TN-5!
S!TN- 00000008!R 00000002! 00000002!F 00000002!B!R2!F2!2!TN-8!
S!TN- 00000010!R 00000003! 00000002!F 00000003!B!R3!F3!2!TN-10!
S!TN- 00000012!R 00000004! 00000002!F 00000004!B!R4!F4!2!TN-12!
S!TN- 00000014!R 00000005! 00000002!F 00000005!B!R5!F5!2!TN-14!
S!TN- 00000013!R 00000005! 00000001!F 00000005!A!R5!F5!1!TN-13!
S!TN-00000008!J00000001! 00000022!F 00000031!CON
PIN!J1!F31!22!TN-8!
S!TN-00000014!J00000001!00000021!F00000030!CON
PIN!J1!F30!21!TN-14!
S!TN-00000006!J00000001! 00000020!F 00000029!CON
PIN!J1!F29!20!TN-6!
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S!TN-00000012!J00000001!00000016!F 00000025!CON
PIN!J1!F25!16!TN-12!
S!TN-00000010!J00000001!00000023!F 00000020!CON
PIN!J1!F20!23!TN-10!
S!TN-00000022!J00000001! 00000008!F 00000017!CON
PIN!J1!F17!8!TN-22!
S!TN-00000022!J00000001! 00000007!F 00000016!CON
PIN!J1!F16!7!TN-22!
S!VCC!J 00000001! 00000001!F 00000014!CON-PIN!J1!F14!1!VCC!
S!VCC!J 00000001! 00000003!F 00000012!CON-PIN!J1!F12!3!VCC!
S!GND!U 00000003! 00000010!!!U3!!10!GND!
S!VCC!U 00000003! 00000020!!!U3!!20!VCC!
S!TP 00000001!U 00000003! 00000016!F 00000045!D!U3!F45!16!TP1!
S!TN- 00000004!U 00000003! 00000017!F 00000045!Q!U3!F45!17!TN
4!
S!TN- 00000005!U 00000003! 00000014!F 00000042!D!U3!F42!14!TN
5!
S!TN- 00000013!U 00000003! 00000015!F 00000042!Q!U3!F42!15!TN
13!
S!GND!U 00000001! 00000007!!!U1!!7!GND!
S!VCC!U 00000001! 00000014!!!U1!!14!VCC!
S!TP 00000001!U 00000001! 00000010!F 00000036!B!U1!F36!10!TP1!
S!TN- 00000028!U 00000001! 00000002!F 00000035!B!U1!F35!2!TN
28!
S!TN- 00000028!U 00000001! 00000004!F 00000034!A!U1!F34!4!TN
28!
S!TN- 00000028!U 00000001! 00000005!F 00000034!B!U1!F34!5!TN-28!
Note that the A and J records are broken into several lines for clarity; extracta never
breaks records into multiple lines.
Example 3: Etch Line Coordinates; GEOMETRY View
The extracta command le etch_view.txt
#
# Allegro PCB Editor Data Extract Sample
# Extract Command File
# Extracts all ETCH elements
#
# View Name:
GEOMETRY
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#
# Select:
CLASS = ETCH#
# Data fields to be written out:
CLASS
SUBCLASS
NET_N
AME_SORT
NET_NAME
RECORD_TAG
GRAPHIC_DATA_NAME
GRAPHIC_DATA_NUMBER
GRAPHIC_DATA_1
GRAPHIC_DATA_2
GRAPHIC_DATA_3
GRAPHIC_DATA_4
GRAPHIC_DATA_5
GRAPHIC_DATA_6
GRAPHIC_DATA_7
GRAPHIC_DATA_8
GRAPHIC_DATA_9
GRAPHIC_DATA_10
# End of Command File
END
when used in the following command:
extracta test_board etch_view etch_dat
creates a le called etch_dat.txt:
A!CLASS!SUBCLASS!NET_NAME_SORT!NET_NAME!RECORD_TAG
!GRAPHIC_DATA_NAME!GRAPHIC_DATA_NUMBER
!GRAPHIC_DATA_1!GRAPHIC_DATA_2!GRAPHIC_DATA_3!GRAPHIC_DATA_4
!GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!GRAPHIC_DATA_8
!GRAPHIC_DATA_9!
J!/usr2/bud/test_board.brd!Mon May 6 10:12:27 1991
!-1500!-1500!4000!4500!1!mils!!!
S!ETCH!TOP!TP 00000001!TP1!1
1!LINE!257!1500!2300!1450!2250!12!
S!ETCH!TOP!TP 00000001!TP1!1
2!LINE!257!1450!2250!1175!2250!12!
S!ETCH!TOP!TP 00000001!TP1!1
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3!LINE!257!1175!2250!1125!2300!12!
S!ETCH!TOP!TP 00000001!TP1!1 4!LINE!257!1125!2300!900!2300!12!
S!ETCH!TOP!TP 00000001!TP1!2 1!LINE!257!600!2300!900!2300!12!
S!ETCH!BOTTOM!TN- 00000028!TN-28!3
1!LINE!257!1200!2600!1250!2550!12!
S!ETCH!BOTTOM!TN- 00000028!TN-28!3
2!LINE!257!1250!2550!1250!2450!12!
S!ETCH!BOTTOM!TN- 00000028!TN-28!3
3!LINE!257!1250!2450!1200!2400!12!
S!ETCH!BOTTOM!TN- 00000028!TN-28!4
1!LINE!257!1200!2300!1200!2400!12!
S!ETCH!BOTTOM!TN- 00000013!TN-13!5
1!LINE!257!1125!2350!975!2350!12!
S!ETCH!BOTTOM!TN- 00000013!TN-13!5
2!LINE!257!975!2350!950!2375!12!
S!ETCH!BOTTOM!TN- 00000013!TN-13!53!LINE!257!950!2375!850!2375!12!
S!ETCH!BOTTOM!TN- 00000013!TN-13!5
4!LINE!257!850!2375!825!2350!12!
S!ETCH!BOTTOM!TN- 00000013!TN-13!5
5!LINE!257!825!2350!700!2350!12!
S!ETCH!BOTTOM!TN- 00000013!TN-13!5
6!LINE!257!700!2350!675!2325!12!S!ETCH!BOTTOM!TN-00000013!TN-13!5
7!LINE!257!675!
2325!675!2200!12!
S!ETCH!TOP!TN- 00000013!TN-13!6 1!LINE!257!600!2200!675!2200!12!50
Note that the A and Jrecords are broken into several lines for clarity; extracta never
breaks records into multiple lines.
This data can be used, for example, as input to a program to plot a drawing on a plotter not
supported by Allegro PCB Editor.
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4
Extract Data Dictionary
This section contains descriptions of data elds used by Allegro PCB Editor views and the
extracta command. Data elds that identify database views are listed and described in
alphabetical order.
The Data Dictionary includes all data elds that you can extract and their available views.
Legal views are:
This chapter discusses the following:
I Data Fields and Legal Views
I Data Field Descriptions
Data Fields and Legal Views
This section provides a short description of each data eld. See Data Field Descriptions on
page 80 for a comprehensive description.
A = COMPONENT G = GEOMETRY
B = COMPONENT_PIN H = FULL_GEOMETRY
C = FUNCTION I = SYMBOL
D = LOGICAL_PIN J = BOARD
E = NET K = CONNECTIVITY
F = COMPOSITE_PAD L = LAYER
Data Field Description Legal Views
APADFLASH anti-pad ash name ABCDEFGHIJKL
APADHGHT anti-pad height ABCDEFGHIJKL
APADSHAPE1 anti-pad geometry ABCDEFGHIJKL
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APADSHAPENAME anti-pad shape name ABCDEFGHIJKL
APADWIDTH anti-pad width ABCDEFGHIJKL
APADXOFF anti-pad x offset ABCDEFGHIJKL
APADYOFF anti-pad y offset ABCDEFGHIJKL
BOARD_ACCURACY accuracy of unit measurements ABCDEFGHIJKL
BOARD_DRC_STATUS (UP_TO_DATE/OUT_OF_DATE) ABCDEFGHIJKL
BOARD_EXTENTS_X1 board extents low left-X ABCDEFGHIJKL
BACKDRILL_TOP_LAYER layer to which to backdrill from
the top side
B, D, F, H
BACKDRILL_BOTTOM_LAYER layer to which to backdrill from
the bottom side
B, D, F, H
BOARD_EXTENTS_Y1 board extents low left-Y ABCDEFGHIJKL
BOARD_EXTENTS_X2 board extents up right-X ABCDEFGHIJKL
BOARD_EXTENTS_Y2 board extents up right-Y ABCDEFGHIJKL
BOARD_LAYERS etch layers in the board ABCDEFGHIJKL
BOARD_NAME name of the drawing ABCDEFGHIJKL
BOARD_UNITS units used in the drawing ABCDEFGHIJKL
CLASS class of entity .B.C..FGH..K.
COMP_CLASS component class (IC, IO, etc.) ABCD.FG.I.K
COMP_DEVICE_TYPE component device type ABCD.FG.I.K
COMP_MAX_POWER_DISS_
DEVICE_INSTNCE
maximum power dissipation
maximum power diss - from
device
maximum power diss - from inst
only
ABCD.FGHI.K
ABCD.FGHI.K
ABCD.FGHI.K
COMP_PACKAGE component package name ABCD.FG.I.K
DRILL_FIGURE_CHAR drill hole gure character .B.D.F.H.
DRILL_FIGURE_HEIGHT drill hole gure height .B.D.F.H.
DRILL_FIGURE_ROTATION drill hole gure rotation .B.D.F.H.
Data Field Description Legal Views
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DRILL_FIGURE_SHAPE drill hole gure shape .B.D.F.H.
DRILL_FIGURE_WIDTH drill hole gure width .B.D.F.H..
DRILL_HOLE_NAME drill hole name .B.D.F.H.
DRILL_HOLE_NAME2 slot minor dimension .B.D.F.H.
DRILL_HOLE_NEGTOL drill hole negative tolerance .B.D.F.H
DRILL_HOLE_PLATING drill hole plating information .B.D.F.H.
DRILL_HOLE_POSTOL drill hole positive tolerance .B.D.F.H
DRILL_HOLE_X drill hole xcoordinate .B.D.F.H.
DRILL_HOLE_Y drill hole ycoordinate .B.D.F.H.
DRILL_ARRAY_ROWS drill hole array row coordinates
(plural vias)
.B.D.F.H.
DRILL_ARRAY_COLUMNS drill hole array column
coordinates (plural vias)
.B.D.F.H.
DRILL_ARRAY_CLEARANCE drill hole clearances in arrays
(plural vias)
.B.D.F.H.
DRILL_ARRAY_LOCATIONS drill hole locations in format X1,
Y1, X2, Y2... (plural vias)
.B.D.F.H.
END_LAYER_NAME end layer (subclass) name .B.D.F
END_LAYER_NUMBER end layer number .B.D.F
FIXFLAG internal layer xed or optional
(f = xed, o = optional)
ABCDEFGHIJKL
FUNC_DES function designator .BCD.F
FUNC_DES_SORT function designatorfor sort .BCD.F
FUNC_SLOT_NAME function slot name .BCD.F
FUNC_TYPE function type .BCD.F
GRAPHIC_DATA_NAME graphic element name .B.D.FGH...K
GRAPHIC_DATA_NUMBER graphic element number .B.D.FGH...K
GRAPHIC_DATA_1 graphic data eld 1 .B.D.FGH...K
GRAPHIC_DATA_2 graphic data eld 2 .B.D.FGH...K
Data Field Description Legal Views
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GRAPHIC_DATA_3 graphic data eld 3 .B.D.FGH...K
GRAPHIC_DATA_4 graphic data eld 4 .B.D.FGH...K
GRAPHIC_DATA_5 graphic data eld 5 .B.D.FGH...K
GRAPHIC_DATA_6 graphic data eld 6 .B.D.FGH...K
GRAPHIC_DATA_7 graphic data eld 7 .B.D.FGH...K
GRAPHIC_DATA_8 graphic data eld 8 .B.D.FGH...K
GRAPHIC_DATA_9 graphic data eld 9 .B.D.FGH...K
GRAPHIC_DATA_10 graphic data eld 10 .B.D.FGH...K
LAYER layer name ..........L
LAYER_ARTWORK POSITIVE, NEGATIVE, or blank ..........L
LAYER_CONDUCTOR species YES/NO for conductor
layer
..........L
LAYER_DIELECTRIC_CONSTANT dielectric constant ..........L
LAYER_ELECTRICAL_
CONDUCTIVITY
electrical conductivity ..........L
LAYER_MATERIAL species material type ..........L
LAYER_LOSS_TANGENT represents energy lost ..........L
LAYER_SORT sorts layer data ..........L
LAYER_SUBCLASS subclass name ..........L
LAYER_SHIELD_LAYER YES indicates a shield layer ..........L
LAYER_THERMAL_CONDUCTIVIT
Y
thermal conductivity ..........L
LAYER_THICKNESS layer thickness ..........L
LAYER_TYPE basic layer type in cross-section ..........L
LAYER_USE EMBEDDED_PLANE ..........L
NET_CAPACITANCE capacitance of total net .B.DEFGH..K
NET_ETCH_LENGTH total etch (only) length on a net .B.DEFGH..K
NET_ETCH_WIDTH_AVERAGE average width of net .B.DEFGH..K
Data Field Description Legal Views
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NET_IMPEDANCE_AVERAGE average impedance of net .B.DEFGH..K
NET_IMPEDANCE_MAXIMUM maximum impedance of segment .B.DEFGH..K
NET_IMPEDANCE_MINIMUM minimum impedance of segment .B.DEFGH..K
NET_INDUCTANCE inductance of total net .B.DEFGH..K
NET_MANHATTAN_LENGTH total Manhattan connect length .B.DEFGH..K
NET_NAME net name .B.DEFGH..K
NET_NAME_SORT net name - for sort .B.DEFGH..K
NET_PATH_LENGTH length of etch + Manhattan rats .B.DEFGH..K
NET_PROPAGATION_DELAY_
ACTUAL
calculated propagation delay on
the net
.B.DEFGH..K
NET_RAT_CONNECT sort eld for connectivity .B
NET_RAT_SCHEDULE net ratsnest schedule .B
NET_RESISTANCE resistance of total net .B.DEFGH..K
NET_STATUS net (RAT) status .B.DEFGH..K
NET_VIA_COUNT number of vias in a net .B.DEFGH..K
NODE_CONNECTS number of connections .B.D.FGH..K.
NODE_1_NUMBER used for connectivity view ..........K.
NODE_2_NUMBER used for connectivity view ..........K.
NODE_SORT used for connectivity view ..........K.
PAD_FLASH pad ash name .B.D.F.H..K
PADHGHT pad height .B.D.F.H..K
PADSHAPE1 pad geometry .B.D.F.H..K
PAD_SHAPE_NAME pad shape name .B.D.F.H..K
PAD_STACK_ NAME padstack name .B.D.F.H..K
PAD_STACK_SOURCE_NAME Blank for normal padstacks and
the name of the "derived from"
padstack for instance-edited
padstacks.
.B.D.F.H..K
PAD_TYPE pad type .B.D.F.H..K
Data Field Description Legal Views
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PADWIDTH pad width .B.D.F.H..K
PADXOFF X offset for pad .B.D.F.H..K
PADYOFF Y offset for pad .B.D.F.H..K
PIN_COMMON_CODE common pin if non-blank .B.D.FG.H..K
PIN_EDITED YES=pin has been instance
edited
.B.D.FGH..K
PIN_NAME pin name .B.D.FGH..K
PIN_NUMBER pin number .B.D.FGH..K
PIN_NUMBER_SORT pin numberfor sort .B.D.FGH..K
PIN_ROTATION rotation of the pin, in degrees,
relative to its symbol. This is
essentially the rotation of the pin
as it exists in the
symbol'sdrawing (.dra) database
.B.D.FGH..K
PIN_ROTATION_ABSOLUTE rotation of the pin, in degrees,
relative to the actual drawing.
This takes into account, for
instance, the rotation of the
symbol as well as the rotation of
the pin.
.B.D.FGH..K
PIN_SWAP_CODE pin swap code .B.D.FGH..K
PIN_TYPE pin type .B.D.FGH..K
PIN_X pin absolute xcoordinate .B.D.FGH..K
PIN_Y pin absolute ycoordinate .B.D.FGH..K
RAT_CONNECTED YES/NO for ratsnest is
connected
..........K.
REC_NUMBER record of what is being output for
a particular padstack
......GH..K
RECORD_TAG record association tag ......GH..K
REFDES reference designator ABCD.FG.I.K
REFDES_SORT reference designator - for sort ABCD.FGHI.K
Data Field Description Legal Views
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SEG_CAPACITANCE capacitance of an etch segment ......GH..K
SEG_IMPEDANCE impedance of an etch segment ......GH..K
SEG_INDUCTANCE inductance of an etch segment ......GH..K
SEG_PROPAGATION_DELAY propagation delay ......GH..K
SEG_RESISTANCE resistance of an etch segment ......GH..K
START_LAYER_NAME start layer (subclass) name .B.D.F.H..K
START_LAYER_NUMBER start layer number .B.D.F.H..K
SUBCLASS subclass of entity ......GH
SYM_BOX_X1 symbol bounding box low leftX ABCD.FGHI.K
SYM_BOX_Y1 symbol bounding box low leftY ABCD.FGHI.K
SYM_BOX_X2 symbol bounding box low leftX ABCD.FGHI.K
SYM_BOX_Y2 symbol bounding box low leftY ABCD.FGHI.K
SYM_CENTER_X symbol body center xcoordinate ABCD.FGHI.K
SYM_CENTER_Y symbol body center ycoordinate ABCD.FGHI.K
SYM_EXTENTS_X1 symbol extents low leftX ABCD.FGHI.K
SYM_EXTENTS_Y1 symbol extents low leftX ABCD.FGHI.K
SYM_EXTENTS_X2 symbol extents up rightX ABCD.FGHI.K
SYM_EXTENTS_Y2 symbol extents up rightY ABCD.FGHI.K
SYM_HAS_PIN_EDIT YES=symbol has an edited pin ABCD.FGHI.K
SYM_MIRROR symbol mirror ag ABCD.FGHI.K
SYM_NAME symbol name ABCD.FGHI.K
SYM_ROTATE symbol rotation angle ABCD.FGHI.K
SYM_TYPE MECHANICAL, PACKAGE, or
FORMAT
ABCD.FGHI.K
SYM_X symbol xcoordinate ABCD.FGHI.K
SYM_Y symbol ycoordinate ABCD.FGHI.K
TEST_POINT pin/via test point code .B.FGH. . .K
TRELFLASH thermal relief ash name .B.D.F.H..K
Data Field Description Legal Views
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Data Field Descriptions
APADFLASH
The anti-pad ash name.
APADHGHT
The anti-pad height.
APADSHAPE1
The anti-pad geometry.
APADSHAPENAME
The anti-pad shape name.
APADWIDTH
The anti-pad width.
APADXOFF
The anti-pad X offset.
TRELHGHT thermal relief height .B.D.F.H..K
TRELSHAPE1 thermal relief geometry .B.D.F.H..K
TRELSHAPENAME thermal relief shape name .B.D.F.H..K
TRELWIDTH thermal relief width .B.D.F.H..K
TRELXOFF thermal relief x offset .B.D.F.H..K
TRELYOFF thermal relief y offset .B.D.F.H..K
VIAFLAG suface mount or though hole type . . . . .FGH. . K
VIA_MIRROR YES=via is mirrored . . . . .FGH. . K
VIA_X via xcoordinate . . . . .FGH . .K
VIA_Y via ycoordinate . . . . .FGH. . K
Data Field Description Legal Views
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APADYOFF
The anti-pad Y offset.
BACKDRILL_TOP_LAYER
The layer to which to backdrill fromthe top side. The top of the design is layer number 0, and
the bottom is the total number of layers minus one. For example, a 4-layer design contains
layers 0 through 3. If no backdrilling occurs for a pin or via froma side, the extract value is null.
BACKDRILL_BOTTOM_LAYER
The layer to which to backdrill from the bottom side. The top of the design is layer number 0,
and the bottom is the total number of layers minus one. For example, a 4-layer design
contains layers 0 through 3. f no backdrilling occurs for a pin or via from a side, the extract
value is null.
BOARD_ACCURACY
The accuracy of the designthe user units of one database unit. For example, if the design
is in inches with two decimal places, the accuracy will be .01 (inches). This eld is written into
all les as part of the J header record.
BOARD_DRC_STATUS
The current DRC status of the design. This eld is OUT_OF_DATE if a batch DRC needs to
be run. The design can become OUT_OF_DATE by skipping DRC of shapes or by canceling
out of a DRC. If no DRC is required the eld is UP_TO_DATE.
BOARD_EXTENTS_X1
BOARD_EXTENTS_X2
BOARD_EXTENTS_Y1
BOARD_EXTENTS_Y2
The lower left (X1, Y1) and upper right (X2, Y2) of the extents of the design in user units. Note,
this denes the minimumand maximumcoordinates that can be used in the drawing; it does
not indicate the actual extent of the design outline or any other geometry. This eld is written
into all les as part of the J header record.
BOARD_NAME
The drawing name. This eld is written into all les as part of the J header record.
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BOARD_LAYERS
The total number of etch/wire layers in the design. This is the total number of subclasses
dened for class etch.
BOARD_UNITS
The units used for specifying distance values and position coordinates. Units can be mils,
inches, millimeters, centimeters, or microns. This eld is written into all les as part of the J
header record.
CLASS
The class of the entity. Normally this eld is for geometry, and indicates the type of geometry
(ETCH, PACKAGE GEOMETRY, BOARD GEOMETRY, and so on). It is also used to indicate
pins versus vias in the PAD and COMPOSITE PAD views (PIN for pins, VIA CLASS for vias).
Legal values for the CLASS data eld are listed below.
To specify a legal value in a lter
Type
CLASS=BOARD GEOMETRY
ANALYSIS BOARD GEOMETRY
COMPONENT VALUE DEVICE TYPE
DRAWING FORMAT DRC ERROR CLASS
ETCH MANUFACTURING
PACKAGE GEOMETRY PACKAGE KEEPIN
PACKAGE KEEPOUT PIN
REF DES ROUTE KEEPIN
ROUTE KEEPOUT TOLERANCE
USER PART NUMBER VIA CLASS
VIA KEEPOUT
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COMP_CLASS
The class of the component: IC, IO, or DISCRETE.
COMP_DEVICE_TYPE
The device type of the component. The device type is dened for the component during
Netlist In.
COMP_MAX_POWER_DISS
The maximum power dissipation in watts for a component as dened by the
MAX_POWER_DISS property dened for refdes instances. If this property has not been set
on a refdes, then the PACKAGEPROP MAX_POWER_DISS from the device le during
Netlist In, if it exists, will be used. The maximum power dissipation in watts for the
component.
COMP_MAX_POWER_DISS_DEVICE
The _DEVICE sufx on the COMP_MAX_POWER_DISS data eld retrieves data from only
component denitions.
COMP_MAX_POWER_ DISS_INSTANCE
The _INSTANCE sufx on the COMP_MAX_POWER_DISS data eld retrieves data from
only a specic reference designator.
COMP_PACKAGE
The package to which the component is assigned. The package is dened for the component
during Netlist In. This eld exists for all components. After a component has been
placed on the design, a symbol that has the same name as the package is used to represent
it. For placed symbols, the symbol name is always the same as the package name.
DRILL_FIGURE_CHAR
The character to display with the graphic gure that represents a drill hole.
DRILL_FIGURE _HEIGHT
The height in user units of the graphic gure that displays to represent a drill hole. Normally
used with DRILL_FIGURE_WIDTH and DRILL_FIGURE_ROTATION.
DRILL_FIGURE _ROTATION
The angle of rotation of the graphic gure that displaysdisplays to represent a drill hole. The
value is in degrees with three decimal places of accuracy.
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DRILL_FIGURE _SHAPE
The graphic gure (shape) to represent a drill hole.
This is one of the standard graphic element names.
See GRAPHIC_DATA_NAME.
DRILL_FIGURE _WIDTH
The width in user units of the graphic gure that displays to represent a drill hole. Normally
used with DRILL_FIGURE_HEIGHT and DRILL_FIGURE_ROTATION.
DRILL_HOLE_NAME
The name of the drill hole. This name is used to tell the NC Drill program what size drill bit to
use. Note that DRILL_FIGURE_HEIGHT and DRILL_FIGURE_WIDTH are used to control
the display of the drill hole. When used for slots, represents the slots major dimension.
DRILL_HOLE_NAME2
When used for slots, represents the slots minor dimension.
DRILL_HOLE_NEGTOL
When used for slots, represents the drill holes negative tolerance.
DRILL_HOLE_PLATING
A description of whether the drill hole is plated. Values are PLATED, NON_PLATED, or
OPTIONAL.
DRILL_HOLE_POSTOL
When used for slots, represents the drill holes positive tolerance.
DRILL_HOLE_X
DRILL_HOLE_Y
The X or Y coordinate in user units of the drill hole.
DRILL_ARRAY_ROWS
DRILL_ARRAY_COLUMNS
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The parameters of rows and columns of drill holes in plural vias, in user units.
DRILL_ARRAY_CLEARANCE
The clearance between all drill holes in a plural via array.
DRILL_ARRAY_LOCATIONS
The location of all drill holes in a plural via array. The format is X1, Y1, X2, Y2...
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END_LAYER_NAME
The layer name (subclass) closest to the BOTTOMof the design that has a pad for a particular
COMPOSITE PAD. This eld is normally used with START_LAYER_NAME. Normal through
holes (pins or vias) have the START_LAYER_NAME as TOP and the END_LAYER_NAME
as bottom. Surface mount devices typically have pads with START_LAYER_NAME and
END_LAYER_NAME the same. Blind and buried vias have START_LAYER_NAME and/or
END_LAYER_NAME as something other than TOP or BOTTOM.
END_LAYER_NUMBER
The eld is used like END_LAYER_NAME, except that the value is the actual layer number
rather than the subclass name. The top of the design is layer number 0, and the bottomis the
total number of layers minus one. For example, a 4-layer design contains layers 0 through 3.
FIXFLAG
The internal layer xed or optional (f = xed, o = optional).
FUNC_DES
The function designator.
FUNC_DES_SORT
The function designator in a formfor sorting. The sort formenables a standard text string sort,
to sort the numeric part of the function designator in correct numeric order. This eld should
not be used for display purposes.
FUNC_SLOT_NAME
The slot name of the component to which a function has been assigned.
FUNC_TYPE
The function type of the function. The function type may be specied when the function is
loaded during netlist processing. If the component has only one type of function, the function
type is the same as the device type.
GRAPHIC_DATA_NAME
For standard Allegro PCB Editor gures, the GRAPHIC_DATA_NAME is the Allegro PCB
Editor gure name. For other gures, the name is indicated in the description of the
GRAPHIC_DATA_N elds.
FIGURE_NULL 0
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FIGURE_CIRCLE 2
FIGURE_OCTAGON 3
FIGURE_CROSS 4
FIGURE_SQUARE 5
FIGURE_RECTANGLE 6
FIGURE_DIAMOND 7
FIGURE_OBLONG_X 11
FIGURE_OBLONG_Y 12
FIGURE_HEXAGON_X 15
FIGURE_HEXAGON_Y 16
FIGURE_TRIANGLE_1 18
GRAPHIC_DATA _NUMBER
This eld may used instead of the GRAPHIC_DATA_NAME to save disk space and to make
the post processors job easier.
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GRAPHIC_DATA_N fields
The GRAPHIC_DATA_N (where N is 1 to 10) elds are used differently depending on the
graphic element as dened by the GRAPHIC_DATA_NAME (and
GRAPHIC_DATA_NUMBER) eld as follows:
GRAPHIC_DATA_NAME figure name-standard figure
GRAPHIC_DATA_NUMBER figure number (1 to 255)
GRAPHIC_DATA_1 xcoord of the figure
GRAPHIC_DATA_2 ycoord of the figure
GRAPHIC_DATA_3 width of the figure
GRAPHIC_DATA_4 height of the figure
GRAPHIC_DATA_NAME ARC-arc
GRAPHIC_DATA_NUMBER 256
GRAPHIC_DATA_1 xcoord of start of arc
GRAPHIC_DATA_2 ycoord of start of arc
GRAPHIC_DATA_3 xcoord of end of arc
GRAPHIC_DATA_4 ycoord of end of arc
GRAPHIC_DATA_5 xcoord of center of arcs curve
GRAPHIC_DATA_6 ycoord of center of arcs curve
GRAPHIC_DATA_7 radius of arcs curve
GRAPHIC_DATA_8 width of the arc
GRAPHIC_DATA_9 direction (CLOCKWISE or COUNTER-CLOCKWISE)
GRAPHIC_DATA_10 type of arc (see LINE)
GRAPHIC_DATA_NAME LINE-line (segment)
GRAPHIC_DATA_NUMBER 257
GRAPHIC_DATA_1 xcoord of one end of line
GRAPHIC_DATA_2 ycoord of one end of line
GRAPHIC_DATA_3 xcoord of other end of line
GRAPHIC_DATA_4 ycoord of other end of line
GRAPHIC_DATA_5 width of the line
GRAPHIC_DATA_10 type of line:
CONNECT connect line (cline)
NOTCONNECT not a connect line
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SHAPE part of a shape outline
VOID part of a void within a shape
POLYGON part of an unfilled
shape
(including keepins/
keepouts and rotated rectangles
GRAPHIC_DATA_NAME RECTANGLE-rectangle
GRAPHIC_DATA_NUMBER 259
GRAPHIC_DATA_1 xcoord of lower left corner
GRAPHIC_DATA_2 ycoord of lower left corner
GRAPHIC_DATA_3 xcoord of upper right corner
GRAPHIC_DATA_4 ycoord of upper right corner
GRAPHIC_DATA_5 fill code: 0=unfilled,
1=filled
GRAPHIC_DATA_NAME TEXT - a line of text
GRAPHIC_DATA_NUMBER 260
GRAPHIC_DATA_1 xcoord of text line
GRAPHIC_DATA_2 ycoord of text line
GRAPHIC_DATA_3 angle of rotation of the text
GRAPHIC_DATA_4 mirror code of text = YES or NO
GRAPHIC_DATA_5 justification. LEFT, RIGHT, or
CENTER.
GRAPHIC_DATA_6 font data. Stored as 1 field with size,
font, height, width, slant,
character_spacing,line_spacing and
photoplot_width separated by spaces.
Values: 0=ANSI, 1=ISO, or 2=MICRO.
GRAPHIC_DATA_7 the text string.
GRAPHIC_DATA_NAME T-ratsnest (CONNECTIVITY view only)
GRAPHIC_DATA_NUMBER 261
GRAPHIC_DATA_1 xcoord of the T
GRAPHIC_DATA_2 ycoord of the T
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GRAPHIC_DATA_NAME RATSNEST (CONNECTIVITY view only)
GRAPHIC_DATA_NUMBER 262
GRAPHIC_DATA_1 xcoord of one end of the
ratsnestGRAPHIC_DATA_2ycoord of one end of the ratsnest
GRAPHIC_DATA_3 xcoord of the other end of the ratsnest
LAYER
The layer name.
LAYER_ARTWORK
The artwork type to use for the layer (subclass). The value is POSITIVE or NEGATIVE for a
conductor layer, or blank if the layer is not a conductor.
LAYER_CONDUCTOR
YES indicates that the layer is a conductor layer; NO indicates it is not.
LAYER_DIELECTRIC _CONSTANT
The dielectric constant of the layer. This eld is only meaningful for dielectric layers
(LAYER_CONDUCTOR = NO).
LAYER_ ELECTRICAL_CONDUCTIVITY
The electrical conductivity of the layer.
LAYER_MATERIAL
The type of material for the layer. Common values are COPPER for conductor layers and FR
4, G9, and so on, for dielectric layers.
LAYER_LOSS_TANGENT
A number betweenbut not includingzero and one that represents the amount of energy lost
to the dielectric from a signal travelling through an adjacent conductor.
LAYER_SORT
This eld is an integer that can be used to sort the records froma LAYERviewinto the correct
sequence.
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LAYER_SUBCLASS
The subclass name for the layer.
LAYER_SHIELD_LAYER
YES indicates a shield layer.
LAYER_THERMAL_CONDUCTIVITY
The thermal conductivity of the layer.
LAYER_THICKNESS
The thickness of the layer.
LAYER_TYPE
The basic type of layer in the board/package stackup cross-section. Must be one of a set of
the following pre-dened types:
I Conductor
I Crossover
I Dielectric
I Plane
I Bonding Wire
I Microwire
I Multiwire
I Optical Wave Guide
I Thermal Glue Coating
LAYER_USE
The use of the layer. Layers can be used as EMBEDDED PLANEs.
NET_CAPACITANCE
The capacitance of a net.
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NET_ETCH_LENGTH
The total length of the etch on a net. See NET_PATH_LENGTH and
NET_MANHATTAN_LENGTH.
NET_ETCH_WIDTH _AVERAGE
The average trace width of a net.
NET_IMPEDANCE _AVERAGE
The average impedance for a net.
NET_IMPEDANCE _MAXIMUM
The maximum impedance of any segment of a net.
NET_IMPEDANCE _MINIMUM
The minimum impedance of any segment of a net.
NET_INDUCTANCE
The inductance of a net.
NET_MANHATTAN _LENGTH
Total length of a net using the manhattan distance of all the pintopin connections. See also
NET_ETCH_LENGTH and NET_PATH_LENGTH.
NET_NAME
The name of the net.
NET_NAME_SORT
The net name in a form for sorting. The sort form enables a standard text string sort, to sort
the numeric part of the net name in correct numeric order. This eld should not be used for
display purposes.
NET_PATH_LENGTH
The length of the net using actual etch for connections already made and the manhattan
distance for connections that have not yet been made.
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NET_PROPAGATION _DELAY_ACTUAL
The delay contributed by each cline on the net. Each cline is counted once.
NET_RAT_CONNECT
A text eld used to sort pins into an order useful for determining the physical connectivity of
the pins in the net. This eld is used internally by Allegro PCB Editor.
NET_RAT_SCHEDULE
A text eld used to sort pins into the order indicated by the ratsnest records for the net. This
eld is most meaningful for nets that have been scheduled by the $SCHEDULE section in
netin. Nets with the NO_RAT property are ratsnested if this eld is requested.
The eld has three parts, separated by spaces:
I The rst is a subnet number.
I The second is the pin sequence number on that subnet.
The rst subnet is 1; the rst element on a subnet is 1. Subsequent subnets are created
when a pin is connected by a ratsnest to more than one other pin.
I The third part of the eld is used only for the rst pin of any subnet other than the rst.
It is the pin designator of the pin to which this pin is connected. In other words it is the
parent of this subnet. Each pin other than the rst pin on the subnet is assumed to be
connected to the previous pin.
Consider the following:
U1.1-----U2.2------U3.3
|
|
U4.------U5.5
The Netlist In $SCHEDULE would have been:
signal_name; U1.1 U2.2 U3.3 ; U2.2 U4.4 U5.5
The NET_RAT_SCHEDULE eld for the pins would be:
U1.1 - 1 1
U2.2 - 1 2
U3.3 - 1 3
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U4.4 - 2 1 U2.2
U5.5 - 2 2
Note that an equivalent schedule is:
signal_name; U1.1 U2.2 U4.4 U5.5 ; U2.2 U3.3
and NET_RAT_SCHEDULE:
U1.1 - 1 1
U2.2 - 1 2
U4.4 - 1 3
U5.5 - 1 4
U3.3 - 2 1 U2.2
There is no guarantee which equivalent schedule will be returned.
The NET_RAT_SCHEDULE is only available when using the COMPONENT_PIN view. If it is
requested, the pins are read from the database on a net by net basis, rather than on a
component by component basis. This means that only pins on nets are extracted if this eld
is requested.
NET_RESISTANCE
The total resistance of a net.
NET_STATUS
The (rat) status of the net. This eld is: SCHEDULED if the net has been scheduled by Auto
Schedule or Netlist In; NO_RAT if the NO_RAT property has been set; or REGULAR.
NET_VIA_COUNT
The number of vias on a net.
NODE_CONNECTS
This eld indicates how many connections there are for particular objects. For connect lines,
it will equal 0, 1, or 2, depending on howmany ends connect to a T, PIN, or VIA. For Ts, PINS,
or VIAS, it is the number of connect lines that connect to it. This eld is blank for shapes.
NODE_1_NUMBER
NODE_2_NUMBER
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NODE_SORT
These elds are used in the connectivity view so that a follow-up program can construct the
connectivity of a net. The nets are used to create records that represent either a node of the
net or a connection. NODE_SORT is used to sort nodes (pins, vias, and Ts) before
connections that reference them (ratsnests and standard etch geometry). The usual
sequence of data elds would then be NET_NAME_SORT (or NET_NAME),
NODE_SORT, NODE_1, NODE_2, and RECORD_TAG. The text le can be sorted using
a standard lefttoright sort.
For nodes, NODE_1 equals NODE_2 and is the node number. For connections, NODE_1
is the node number of one end of the connection and NODE_2 is the node number of the
other end of the connection. Shapes can be extracted with this view, but their NODE_1 and
NODE_2 elds are blank. For ratsnests, in addition to the NODE_1 and NODE_2 elds, the
RAT_CONNECTED eld indicates whether there is an electrical connection between the
two nodes.
PAD_FLASH
The name of the ash to be used for this pad. The ash maps a pad to a specic aperture
when creating artwork. This is typically done for non-standard pads such as thermal-relief
pads or anti-pads.
PADHGHT
The height of the pad.
PADSHAPE1
The pad geometry.
PAD_SHAPE_NAME
Describes the shape of the pad. When used in the FULL_GEOMETRY view, the geometry of
the pad is indicated. On other views, this eld describes the composite pad used for display
in the interactive editor. If the shape is a standard geometry, this eld is the same as the
GRAPHIC_ DATA_NAME eld (for example, FIG_CIRCLE or FIG_RECTANGLE). If the
shape is a non-standard geometry, this eld contains the name of the shape preceded by
FIG_SHAPE and a space.
PAD_STACK_ NAME
The name of the padstack.
PAD_STACK_SOURCE_NAME
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Blank for normal padstacks and the name of the "derived from" padstack for instance-edited
padstacks.
PAD_TYPE
Describes the kind of pad as either regular, thermal, or antipad. In the FULL_GEOMETRY
view, the type of the actual pad used contains ANTI, THERMAL, or REGULAR statements.
In other views, it contains the value COMPOSITE to indicate that the pad refers to the
composite pad.
PADWIDTH
The width of the pad.
PADXOFF
The X coordinate for the offset of the pad.
PADYOFF
The Y coordinate for the offset of the pad.
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PIN_COMMON_CODE
A code to indicate whether a pin is common to (shared by) multiple functions in the device. If
the pin is not common, the eld is blank. If it is common and the view is LOGICAL_PIN, the
value is a number increasing from 1. This makes it possible for post processors (such as
netlist generators) to lter out the redundant occurrences of the same physical. If it is common
and the view is other than LOGICAL_PIN (COMPONENT_ PIN, GEOMETRY, and so on), it
is a number and can be the number of functions that share the pin. It should only be treated
as blank or non-blank.
PIN_EDITED
The value is YESif the pin has been instance edited. This occurs when the pin is either moved
or the padstack has been edited.
PIN_NAME
The name of the pin. If the actual internal pin name was generated by Allegro PCB Editor,
this eld is the same as the PIN_NUMBER. Allegro PCB Editor generates pin names when
there are no explicitly dened functions in the device le (in which case the internal name
becomes TP-nnn, where nnn is the pin number).
PIN_NUMBER
The pin number. If a pin is part of a function that has not been assigned to a component, this
eld is blank.
PIN_NUMBER_SORT
The pin number in a formfor sorting. The sort formenables a standard text string sort, to sort
the numeric part of the pin number in correct numeric order. This eld should not be used for
display purposes. As a convenience, if the pin number is blank (unassigned functions), the
pin name is put into the pin_number_sort eld. The fact that it is a pin name and not a pin
number can be obtained by the fact the PIN_NUMBER and/or FUNC_SLOT_ NAME elds
are blank.
PIN_ROTATION
The degree of pin rotation relative to its symbol. This is the rotation of the pin as it exists in
the symbol drawing (.dra) database.
PIN_ROTATION_ABSOLUTE
The degree of pin rotation relative to the actual drawing, accounting for the rotation of the
symbol as well as the rotation of the pin.
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PIN_SWAP_CODE
A number indicating whether a pin can be swapped with other pins of the same function. All
pins of a function that have the same number can be swapped with each other. This eld is
blank when pins cannot be swapped. This eld only represents the swap code as dened by
the device le. Properties may be attached to functions that override the pins ability to be
swapped, but they do not affect this eld.
PIN_TYPE
The type of pin, sometimes called pin use uses the PINUSE property when it has been
dened. Values are IN, OUT, BI, TRI, OCA, OCL, UNSPEC, DISCRETE, NC, POWER, and
GROUND.
PIN_X
PIN_Y
The absolute (relative to the design not the symbol) X and Y coordinate, in user units, of the
location of the pin. Mirror and rotation calculations have been performed in calculating the
coordinate. If the pin is part of an unplaced component (or unassigned function), the eld is
blank.
RAT_CONNECTED
This eld is available in the CONNECTIVITY view for ratsnest connection records. YES
means that the nodes (NODE_1_NUMBER and NODE_2_NUMBER) are connected. The
route for the connection must be determined by analyzing the net topology. This may not be
straightforward if shapes are involved. See also NODE 1_NUMBER, NODE_2_NUMBER,
NODE_SORT, and NODE_CONNECTS.
REC_NUMBER
The record of what is being output for a particular padstack. (For example: .00001 = TOP,
00002 - internal pad def, 00003 = BOTTOM, then top SM, bottom SM, top paste, bottom
paste.)
RECORD_TAG
A eld to establish association for geometric elements. Certain geometry is considered to be
a sub-element of a major geometric element. For example, text lines are sub-elements of a
major element text; line and arc segments are sub-elements of major element line; and
patches are a sub-element of a major element shape. Rectangles and the Allegro PCB
Editor-dened graphic gures never have any sub-elements.
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The purpose of RECORD_TAG is to preserve the association of the sub-elements to the
major element during sorts of the text le.
RECORD_TAG consists of two parts separated by a space.
I The rst is a number that indicates the major geometric element number.
This number starts at 1 (one) and increases for each major element in the database.
I The second is the sub-element number, which starts at 1 (one) for the rst sub-element
of each major element and then increases by one for each subsequent sub-element.
The line major element is handled in two ways. Line or arc segments that are attached on
nets (generally ETCH) or symbols (generally PACKAGE GEOMETRY) are considered part of
the line generated by a single add_line command. However, the major element for all other
segments (generally BOARD GEOMETRY) are part of a major element determined by the
actual polygon dened by connecting the endpoints of all the individual segments.
REFDES
The reference designator of the component. If a function (or its pins) has not been assigned,
this eld is blank. This eld is also blank for a symbol, with no component assigned to it. That
is, the eld is the actual name given to the component, and not generated by looking for
display text of class REFDES.
REFDES_SORT
The reference designator in a form for sorting. The sort form enables a standard text string
sort, to sort the numeric part of the reference designator in correct numeric order. This eld
should not be used for display purposes. If the refdes eld is blank (unassigned functions),
the function designator is used to ll in the value of this eld.
Note: It is a function designator and not a reference designator because the REFDES or
FUNC_SLOT_ NAME elds are blank.
SEG_CAPACITANCE
The capacitance of an etch segment.
SEG_IMPEDANCE
The impedance of an etch segment.
SEG_INDUCTANCE
The inductance of an etch segment.
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SEG_PROPAGATION _DELAY
The propagation delay of an etch segment.
SEG_RESISTANCE
The resistance of an etch segment.
START_LAYER _NAME
The start layer name (subclass) for a COMPOSITE PAD. See the description of
END_LAYER_NAME.
START_LAYER _NUMBER
The start layer number for a COMPOSITE PAD. See the description of
END_LAYER_NUMBER and END_LAYER_NAME.
SUBCLASS
The subclass name of the geometric element. For ETCH and PAD data, this is the name of
the layer on which it has been placed. For other geometry, it is the name of the subclass that
was active when it was added to the design. To specify a legal value for a subclass in a lter
for example, enter SUBCLASS = TITLE_BLOCK (a legal subclass value for the DRAWING
FORMAT class). You can also dene new subclasses using the Define option. See CLASS.
SYM_BOX_X1
SYM_BOX_Y1
SYM_BOX_X2
The lower left (X1,Y1) and upper right (X2,Y2) coordinates, in user units, of a rectangle that
bounds the symbol. These elds are derived from the symbols PLACE_BOUND_TOP
rectangle(s). If the user does not explicitly create one when building the symbol, the rectangle
is automatically generated by Allegro PCB Editor.
SYM_CENTER_X
SYM_CENTER_Y
The X (Y) coordinate, in user units, of the symbols body center. These elds are taken from
the text point of text attached to the symbol with subclass BODY_CENTER. If that text does
not exist, it is calculated from the PLACE_BOUND_TOP rectangle(s).
SYM_EXTENTS_X1
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SYM_EXTENTS_Y1
SYM_EXTENTS_X2
The lower left (X1,Y1) and upper right (X2,Y2) coordinates, in user units, of a rectangle that
encloses the drawing extents of the symbol.
SYM_HAS_PIN_EDIT
The value is YES if the symbol contains any instance-edited pins.
SYM_MIRROR
The eld indicates whether a symbol is mirrored. If the symbol is mirrored, this eld is YES.
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SYM_NAME
The name of the symbol. For a placed component, SYM_NAME should be the same as the
package name.
SYM_ROTATE
The angle of rotation in degrees, with three decimal places of accuracy.
SYM_TYPE
The type of symbol. Values can be: MECHANICAL, BOARD, or FORMAT.
SYM_X SYM_Y
The X (Y) coordinate of the origin of the symbol. Note that mirroring and rotation in Allegro
PCB Editor do not change the origin of the symbol.
TEST_POINT
This eld indicates whether a via is a test point. Values are TOP, BOTTOM, TOP_MANUAL,
and BOTTOM_MANUAL indicating whether the test point test point is on the top or bottom
and whether it was added manually or automatically. The eld is blank if the via is not a test
point.
TRELFLASH
The thermal relief ash name.
TRELHGHT
The height of the thermal relief.
TRELSHAPE1
The thermal relief geometry.
TRELSHAPENAME
The thermal relief shape name.
TRELWIDTH
The width of the thermal relief.
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TRELXOFF
The X coordinate for the offset of the thermal relief.
TRELYOFF
The Y coordinate for the offset of the thermal relief.
VIAFLAG
The suface mount or though-hole type (v = surface mount, empty = through-hole).
VIA_MIRROR
This eld indicates whether the via is mirrored. The value is YES if it is mirrored, NOif it is not.
VIA_X
The X coordinate of the via.
VIA_Y
The Y coordinate of the via.
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5
Generating Test Coupons
Allegro PCB Editor features an automatic test coupon generator. Manufacturers use test
coupons to measure the quality and accuracy of the Printed Circuit Board (PCB)/Multi-Chip
Module (MCM) fabrication.
You can generate the following coupons per ANSI/IPC-D-275 standards:
I Coupon A to evaluate solderability of plated through holes.
I Coupon B to evaluate plating thickness, thermal stress and Type 1 bond strength.
I Coupon C to evaluate plating adhesion and solderability.
I Coupon D to evaluate interconnection resistance and continuity.
I Coupon E to evaluate surface resistance, bulk resistance, and material cleanliness after
exposure to cyclic temperature and humidity.
I Coupon F to evaluate drill holes for break-out, etch back, or hole clean.
I Coupon G to evaluate solder resist adhesion.
Examples of each coupon type follow.
For instructions about generating and placing coupons, see the procedures outlined in
Manufacture Create Coupons (create coupons command) in the Allegro PCB and
Package Physical Layout Command Reference.
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Coupon Examples
Coupon A
Coupon B
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Coupon C
Coupon D
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Coupon E
Coupon F
Coupon G