Hola, para la actividad 2 de la unidad 1 debers analizar los siguientes diagramas, esto es, explicar su funcionamiento

sus seales, y determinar qu tipo de sistema es el que se est presentando (combinacional, secuencial o programado),
elaborar un cuadro comparativo en el que se integren los diagramas analizados.
D
13
Q0
4
Q1
5
A0
1
Q2
6
A1
2
Q3
7
A2
3
Q4
9
Q5
10
LE
14
Q6
11
MR
15
Q7
12
U1
74259
PRIMITIVE=DIGITAL,SCRIPT
SCRIPT=74XX259
INIT=1
*SCRIPTPROGRAM 74XX259
// This is the model for the 74XX259. To avoid cluttering the diagram
// most of the script is hidden. To see the full script point at it with the
// mouse (you may need to zoom in first) and press CTRL+E to Edit it.
*ENDSCRIPT
U1(A0)
U1(A1)
U1(A2)
U1(D)
U1(MR)
WIDTH=32u
START=32u
U1(LE)
WIDTH=32u
START=16u
U1(Q0)
U1(Q1)
U1(Q2)
U1(Q3)
U1(Q4)
U1(Q5)
U1(Q6)
U1(Q7)
E l e c t r o n i c s
Labcenter Electronics, 53-55 Main Street, Grassington, North Yorkshire, BD23 5AA
Fax: +44 (0)1756 752857 Tel: +44 (0)1756 753440
Email: [email protected] http://www.labcenter.co.uk/ WWW:
74259 EasyHDL Model
74259 EasyHDL Model
This sample design shows how a digital part (a 74259) can be modelled
by a script written in EasyHDL. This is an alternative to modelling the
device as an equivalent circuit and allows for great flexibility in creating
your models.
The script is held on the schematic and can be seen below the 74259
and above the graph. Most of the script is hidden to avoid clutter - to see it
fully point at it with the mouse (you may need to zoom in to point at it
accurately) and press CTRL+E to Edit it. Notice that the script not only
models the functional behaviour of the device but also its timing based on
a set of values selected from the 'value' of the device the script is attached
to (in this example, a standard TTL family 74259).
For another example of EasyHDL modelling, see the 7493.DSN sample.
A[0..7]
A[8..15]
D[0..7]
A[0..15]
A15
RESET
9
PD1/TXD
11
XTAL2
18
XTAL1
19
PD2/INT0
12
PD3/INT1
13
PD4
14
PD5/OC1A
15
PD0/RXD
10
WR
16
RD
17
ICP
31
ALE
30
OC1B
29
AD[0..7]
A[8..15]
PB0/T0
1
PB1/T1
2
PB2/AIN0
3
PB4/SS
5
PB5/MOSI
6
PB6/MISO
7
PB7/SCK
8
PB3/AIN1
4
U2
AT90S8515
PROGRAM=EXTRAM1.HEX
DBG_PORDELAY=0
OE
1
LE
11
D[0..7] Q[0..7]
U1
74LS373
CE
20
CS
26
WE
27
OE
22
A[0..12] D[0..7]
U3
6264
D[0..7]
A[8..15]
A[0..7]
U2(ALE)
U2(WR)
U2(RD)
U2(XTAL1)
E l e c t r o n i c s
Labcenter Electronics, 53-55 Main Street, Grassington, North Yorkshire, BD23 5AA
Fax: +44 (0)1756 752857 Tel: +44 (0)1756 753440
Email: [email protected] http://www.labcenter.co.uk/ WWW:
AVR External Memory Access
AVR External Memory Access
This design demonstrates the VSM simulation of an AT8515 performing external
memory access cycles.
Note that the clock signal is including as a reference for the timing waveforms but does
not actually clock the processor. The CPU clock rate is set by a component property.
Note also that being a graph based simulation, this design cannot be simulated with
Proteus VSM Lite.
D
[
0
.
.
7
]
D0
D1
D2
D3
D4
D5
D6
D7
SDA
SCK
R1
PULLUP
R3
PULLUP
ErrCode
SCK
6
SDA
5
WP
7
A1
2
A2
3
U1
24C04A
RA0/AN0
2
RA1/AN1
3
RA2/AN2/VREF-
4
RA4/T0CKI
6
RA5/AN4/SS
7
RE0/AN5/RD
8
RE1/AN6/WR
9
RE2/AN7/CS
10
OSC1/CLKIN
13
OSC2/CLKOUT
14
RC1/T1OSI/CCP2
16
RC2/CCP1
17
RC3/SCK/SCL
18
RD0/PSP0
19
RD1/PSP1
20
RB7/PGD
40
RB6/PGC
39
RB5
38
RB4
37
RB3/PGM
36
RB2
35
RB1
34
RB0/INT
33
RD7/PSP7
30
RD6/PSP6
29
RD5/PSP5
28
RD4/PSP4
27
RD3/PSP3
22
RD2/PSP2
21
RC7/RX/DT
26
RC6/TX/CK
25
RC5/SDO
24
RC4/SDI/SDA
23
RA3/AN3/VREF+
5
RC0/T1OSO/T1CKI
15
MCLR/Vpp/THV
1
U2
PIC16F877
?
R2
PULLUP
WRITE
MEMORY?
STATUS
This sample shows the functioning of the a 24C04A I2C serial memory.
The source code writes a series of values to address 0x0100-0x010F and then reads them back
again verifying each byte as it is read. If an error occurs then the error code is written to Port D
and the Status (RA0) line is toggled.
A switch on RA5 controls whether or not the write portion of the test is performed. When the
switch is closed only a read test is done. This can be used to verify memory persistence.
I2C Memory Test
SEQUENTIAL LOGIC CIRCUITS - RS FLIP-FLOP
The RS (reset-set) flip-flop is the simplest logic circuit that can exhibit memory behaviour.
If the SET input is changed to logic 0, the Q output becomes set to logic 1. When the SET
input returns to logic 1, the Q output 'remembers' its state. Similarly, the RESET input will
clear the Q output to logic 0. The circuits ability to remember its state derives from the
feedback connections from each NAND gate to the other.
U1
NAND
U2
NAND
Q-OUTPUT
0 SET
0 RESET
Q-OUTPUT

*SCRIPT PROGRAM 7493
ALIAS RA=R0(1), RB=R0(2)
IPROP INIT=0
TPROP TDRA, TDRB, TDRC, TDRD
TPROP TDLHQA, TDLHQB, TDLHQC, TDLHQD
TPROP TDHLQA, TDHLQB, TDHLQC, TDHLQD
PIN CKA, CKB, RA, RB
PIN QA,QB,QC,QD
INT counta = INIT & 1, countb = INIT >> 1
MAP ON VALUE
CASE 7493 :
TDRA=26n : TDRB=26n : TDRC=26n : TDRD=26n
TDLHQA=10n : TDHLQA=12n : TDLHQB=10n : TDHLQB=14n
TDLHQC=21n : TDHLQC=23n : TDLHQD=34n : TDHLQD=34n
BREAK
ENDMAP
IF EVTID=EI_BOOT
QA = counta & 1
QB = countb & 1
QC = countb & 2
QD = countb & 4
ELSIF RA & RB
counta = 0
QA = FALSE AFTER TDRA
countb = 0
QB = FALSE AFTER TDRB
QC = FALSE AFTER TDRC
QD = FALSE AFTER TDRD
ELSE
IFCKA=NEGEDGE
counta = counta+1
QA = counta & 1 AFTER TDLHQA,TDHLQA
ENDIF
IFCKB=NEGEDGE
countb = countb+1
QB = countb & 1 AFTER TDLHQB,TDHLQB
QC = countb & 2 AFTER TDLHQC,TDHLQC
QD = countb & 4 AFTER TDLHQD,TDHLQD
ENDIF
ENDIF
*ENDSCRIPT
CKA
14
QA
12
CKB
1
QB
9
QC
8
QD
11
R0(1)
2
R0(2)
3
U1
7493
PRIMITIVE=DIGITAL
SCRIPT=7493
A
B
C
D
CLOCK
RESET
This sample shows a 7493 counter modelled using an EasyHDL script. The script
is a complete model of both the functional as well as timing behaviour of the 7493.
For another example of EasyHDL modelling see the 74259.DSN sample file.
E l e c t r o n i c s
Labcenter Electronics, 53-55 Main Street, Grassington, North Yorkshire, BD23 5AA
Fax: +44 (0)1756 752857 Tel: +44 (0)1756 753440
Email: [email protected] http://www.labcenter.co.uk/ WWW:
7493 EasyHDLModel
7493 EasyHDLModel