1

I. Introduction
Recently, current mode circuits have been receiving significant attention in analog
signal processing. A useful function block for high frequency current mode
applications is a current conveyor. The current conveyor is a three terminal device
performing many useful analog signal processing functions when the device is
connected with other electronic elements in specific circuit configurations. The
current conveyor has evolved from first generation to second generation. The first
generation current conveyor (CCI) was proposed by Smith and Sedra in 1968 [1] and
the more versatile second generation current conveyor (CCII) was introduced by the
same two authors in 1970 [2], as an extension of their first generation conveyor.
In many cases, the current conveyor simplifies circuit design in much the same way
as the conventional op-amp, but it presents an alternative method of implementing
analog systems which traditionally has been based on op-amp. This alternative
approach leads to new methods of implementing analog transfer functions, and in many
cases the conveyor-based implementation offers improved performance to the voltage
op-amp-based implementation in terms of accuracy, bandwidth and convenience.
Circuits based on voltage op-amps are generally easy to design since the behavior of a
voltage op-amp can be approximated by few simple design rules. This is also true for
current conveyors. Several hundred papers have been published on the theory and
applications of current conveyors. Some of these applications are shown in Fig. 1 [3,
4].

The second generation current controlled conveyor (CCCII) which implemented
with the BJT and the BiCMOS technology by Fabre, etc. in 1995 [5] and 1997 [6]
respectively. One of the reasons we use the CCCII is that it allows implementation of
electronic functions usable at high frequency. The other reason to use the CCCII is its
parasitic resistance at terminal X is controllable [7]. The controllable resistance is
usable for the applications of tunable circuits, such as filters.
In order to obtain a small-size low-weight handheld system, a single-technology
scheme is preferred for maximum integration level. To realize this scheme, the low-
cost high-integration all-CMOS implementation is one of the most attractive solutions.
Up to date, the CMOS CCCII has not yet been explored. This paper will describe the
CMOS current controlled conveyor (CCCII) and its application for a tunable high
frequency high Q current-mode bandpass filter [6, 8]. We will also exploit its
potential in the frequency range around 200MHz~300MHz which is within the IF filter
design specification of modern wireless mobile phone. The tuning of the center
frequency
o
f and Q-factor can be obtained by varying two independent dc current
sources.

Section II gives an overview of the current conveyor, the proposed CMOS current
controlled conveyor is described in Section III, and the architecture of the second order
current-mode bandpass filter is described in Section IV. Section V is the conclusion.
2
Current Conveyors
Amplifiers
CCCS
Differentiation
Integration
Summation
Analogue
Computation
Instrumentation
Amps
VCCS
Ideal transistor
Oscillators
Current-Feedback
Op-amps
Filters
Impedance
Conversion
FDNR
Synthesis
Inductance
Synthesis
Fig. 1 Current conveyor applications
3
II. Conventional Current Conveyors
The current controlled conveyor is derived from the current conveyor. In this
section, we will describe the basic idea of the CCII circuit, and the previous Bipolar
implementation of CCIIs.
A. Second Generation Current Conveyor

The block diagram of a second generation current conveyor (CCII) is shown in
Fig.2. The CCII has three terminals X, Y, and Z. The relationship of terminal
currents and voltages is defined as [2]:

y
i 0 0 0
y
v


x
v = 1 0 0
x
i (1)


z
i 0 1 0
z
v
The above equation indicates: voltage
x
v follows voltage
y
v , currents
z
i follows
current
x
i , and the current
y
i is equal to zero. The zero current indicates terminal Y
has an infinite input resistance. By convention, the positive current indicates the
current flow into the device. The sign indicates the
x
i and
z
i are in the same
direction or opposite.
According to Eq. (1), we know that an ideal CCII is a combination of a voltage
follower and a current follower. The voltage follower is between terminal Y and
terminal X, and the current follower is between terminal X and terminal Z. A
simplified representation of CCII is shown in Fig. 3. An ideal voltage follower has
infinite input impedance and zero output impedance, and an ideal current follower has
zero input impedance and infinite output impedance.


y
i

y
v Y
z
i
CCII Z
z
v


x
v X

x
i

Fig. 2 Current conveyor electrical symbol
4

Fig. 3 Simplified representation of CCII

Y
X
Z
x
i
x
i t
z
i
5
B. CCII in Practice

Nevertheless, a practical implementation of the CCII can never be ideal. The
input resistance
y
Z at terminal Y and the output resistance
z
Z at terminal Z may not
be infinite, the input resistance
x
Z at terminal X may not be zero, and the voltage gain
and current gain may not be unity. In order to optimize the design for high-frequency
operation, it is necessary to consider a more realistic model for the CCII. In Fig. 4, a
widely used equivalent circuit is shown to describe the conveyor analytically at high
frequency [6, 9, 10].
Fig. 4 High-frequency model for the CCII
Y
Voltage
follower
Current
follower
) (t i
y
y
R
y
C
) (t i
x
) (t v
x
x
R
'
x
i
'
z
i
z
R
Z
C
) (t i
z
) (t v
z
Z
X
Ideal CCII
X
Y Z
) (t v
y
6
C. Translinear Implementation of CCII+
The circuit, shown in Fig. 5 [11], uses a mixed translinear cell between terminal Y
and X, which is biased by
o
I . Output Z, which duplicates the current flowing through
terminal X, is realized in a conventional manner, using two complementary mirrors.
The input cell, with mixed translinear loop, contains two PNP and two NPN
transistors. It is characterized by the translinear relationship between collector currents
of these transistors [11]:

4 2 3 1 c c c c
I I I I (2)
The circuit is biased by dc current
o
I (
o c c
I I I
3 1
, by assuming current gain of
the transistors much greater than unity). Thus, it presents a high impedance input
terminal Y and a low impedance output terminal X. This cell acts as a voltage
follower. The voltage difference between terminals X and Y depends on the value of
the current ( ) t i
x
; its expression is given by
( )
( )
o
c
T XY
I
t I
V t V
2
log (3)

where mV q kT V
T
26 / at 27is the thermal voltage. The relationship Eq. (2)
allows, in the particular case of the loop shown in Fig. 5 (i.e., for
o c c
I I I
3 1
), to
calculate the expressions for the currents ) (
2
t I
c
and ) (
4
t I
c
. They are given by [11]
( ) ( ) ( ) ( )
1
]
1

+ t i I t i t I
x x c
2
1
2
0
2
2
4
2
1
(4)
( ) ( ) ( ) ( )
1
]
1

+ + t i I t i t I
x x c
2
1
2
0
2
4
4
2
1
(5)
Now, with the assumption, ( ) t i
x
<<
o
I 2 , Eq. (3) and Eq. (4) lead to
( ) ( ) t i
I
V
t V
x
o
T
XY
2
(6)

The relationship shows that the output small signal resistance of the equivalent
voltage follower is
o T X
I V R 2 / (7)
So,
x
R can be controlled by varying the bias current
o
I of the loop.

7
Fig.5 Translinear implementation of CCII+
V+
V
o
I
o
I
Y X Z
) (t i
x
Q5 Q6
Q1 Q2
Q3 Q4
Q7 Q8
8
D. Previous Current Controlled Conveyors

The schematic of the CCCII+ deduced from Fig.5 implemented by BJT [5, 12] and
BiCMOS [6, 8] are shown in Fig. 6. Two current mirrors (transistor
5
Q to
7
Q and
10
Q ,
11
Q ) allow the translinear loop to be biased by the current
o
I . Note that the
MOS transistors in Fig. 6(b) are used for the biasing to minimize noise, the main
contribution in noise coming from the current mirrors.
In this paper, we will show that it is possible to take advantage of this parasitic
resistance on terminal X of CCCII because its value depends on the bias current of the
conveyor. Thus the CCCIIs allow current conveyor applications to be extended to the
domain of electronically adjustable functions.
From Eq. (7),
x
R can be controlled by
o
I . This property can be applied for
some useful applications [12] such as: (1) controllable voltage-current conversion (see
Fig. 7), (2) negative current controlled resistance (Fig. 8), and they are used in our
design of a bandpass filter.
(1) Controllable voltage-current conversion
When the terminal Y of the CCCII+ is grounded and terminal X constitutes the
input of the circuit, the output current ) ( ) ( t i t I
x z
is then given by
( ) ( ) t V
R
t I
in
x
out
1
(8)
Its value is therefore controllable by the bias current
o
I . The input resistance of this
circuit, seen from terminal X is equal to
x
R .
(2) Negative current controlled resistance
The circuit represented in Fig. 8 simulates a grounded negative resistance which
value:
x in
R Z is current controlled, and we will discuss it in Section IV-C.


9
(a)
(b)
Fig. 6 The schematic implementation of CCCII+ (a) BJT, (b) BiCMOS
) (t i
x
X
) (t v
x
) (t i
z
Z
) (t v
z
) (t i
y
Y
) (t v
y
) (t i
z
) (t v
z
Z ) (t i
x
X
) (t v
x
) (t v
y
Y
) (t i
y
o
I
o
I
Q10 Q11 Q8 Q9
Q1 Q2
Q3 Q4
Q5 Q7 Q12 Q13
Q6
Q10 Q11 Q13 Q12
Q1 Q2
Q3 Q4
Q5 Q7 Q15 Q14
V+
V
V+
V
Q9
Q8
Q6
10

Fig. 7 Voltage-current conversion with Y grounded

Fig. 8 Negative current controlled resistance
CCCII+
X Z
Y
) (t i
x
out z
I t i ) (
+
) (t V
in

o
I
CCCII+
Y Z
X
) (t i
x
) (t i
z
in
Z
o
I
Input
11
III. CMOS Current Controlled Conveyor
In this section we will describe our design of a CMOS current controlled conveyor
and show the simulation results.
A. Circuit Description and Analysis
The circuit shown in Fig. 9(a) is similar to the translinear implementation of the
CCCII+ shown in Fig. 6. The input cell, M1-M4, contains two N-MOS and two P-
MOS transistors, and the voltage at terminal X follows the voltage supplied at terminal
Y. The transistors M5~M11 form a controllable bias circuit. Two complementary
current mirrors M12-M13, M14-M15 make the current flowing through terminal Z
duplicates the current flowing through the terminal X. The transistors M16-M17 and
M18-M19 improve the input impedance
y
R and output impedance
z
R , respectively.
Fig. 9(b) presents the equivalent model of the current conveyor giving the input and
output impedance of each terminal, and Fig. 9(c) shows the equivalent circuit between
terminal Y and X.
Since the input impedance
x
Z is strongly related to the performance of the
bandpass filter, it is studied in detail here. Referring to the Fig. 9(a), the expression of
x
R is given by the following formula [13]:



4 2
1
m m
x
g g
R
+
(9)


where
m
g is the MOSFET transconductance controlled by
gs
v . For a MOS transistor,
it can be shown that the transconductance are proportional to
o
I , so that the input
resistance
x
R depends on the bias current.
Assume P-MOS and N-MOS transistors are matched. Including all the parasitics
in terminal X, the input impedance
x
Z is

( )
( )( )
2 2 1 1
1 2 1
2
1
m gs m gs
m gs gs
x
g sC g sC
g C C s
Z
+ +
+ +
(10)
Fig. 9(d) shows the detailed equivalent circuit.
12

(a)

(b)
Fig. 9 CMOS current controlled conveyor (CCCII+) (a) Schematic implementation,
(b) Equivalent model of the CCCII+

) (t i
y
) (t v
y
) (t i
x
) (t v
x
) (t i
z
) (t v
z
o
I
Y X Z
a
V
b
V
c
V
d
V
Y
x i
i A
X
y v
v A
y
Z
x
Z
Z
z
i
x
i
z
Z
M10 M11 M13 M12
M16 M18
M1 M2
M3 M4
M5 M7 M14 M15
M6
M17 M19
M9
M8
V+
V
13



(c)

(d)
Fig. 9 CMOS current controlled conveyor (CCCII+) (c) Equivalent circuit between
Y and X, (d) Practical circuit of terminal X including parasitic elements
Y X
v
A
) (t v
y
) (t v
x
) (
'
t v
x
x
R
) (t i
x
Voltage follower
x
i
xb
R
x
C
x
L
xa
R
x
Z
X
'
14
Expressions of
xa
R and
xb
R are
( )
( ) ( )( )
1 2 1 2 1 1 2 2 1
2
2 1 2
2
2 1
2
1
m gs gs gs gs gs m gs m gs gs m
gs gs
xa
g C C C C C g C g C C g
C C
R
+ + + +
+

(11)
( )
( )( )
2 1 1 2 1 1 2 2 1
2
2 1
2
1
gs gs m gs gs gs m gs m
gs gs
xb
C C g C C C g C g
C C
R
+ +
+
(12)
and
2
2 / 1 //
m xb xa x
g R R R . The expression of the input inductance is


xa
m
gs gs
x
R
g
C C
L
1
2 1
2
1
+
(13)
and the parasitic capacitor
x
C is


2 1
2 1
2
gs gs
gs gs
x
C C
C C
C
+
(14)
B. Simulation Results
In this design, the bias current
0
I is equal to 100A using 2.5V power supply
voltages, and Table I gives the transistor design parameters. Fig. 10 shows the
voltage transfer characteristic
v
A (=
y x
v v / ) with an open circuit node X and a
grounded node Z. The 3dB cutoff frequency is 950MHz, and the voltage gain at low
frequency is around 0.973. Fig. 10 also shows the current transfer characteristic
i
A
(=
x z
i i / ) when nodes Y and Z are grounded. Its 3dB bandwidth is about 380MHz, and
the gain of the current transfer is 0.927. The simulated impedance
x
Z is shown in
Fig. 11. The calculated value of parasitic elements (
xa
R = 2.25K ,
xb
R = 445 ,
x
L
= 0.66 H, and
x
C = 0.18pF) are very approximate to the simulated curve. Table II
gives the simulation results.
Table III shows the comparison of the BJT [12], BiCMOS [8] and CMOS
implementations. In this table,
0
I is equal to 50A and supply voltages are 2.5V.
15

TABLE I
TRANSISTOR DESIGN PARAMETERS
Transistors W/L (m)
M1, M2, M17 100/0.5
M3, M4, M12, M13 45/0.55
M5, M6 15/0.5
M7 16.5/0.5
M8, M9 45/0.5
M10 75/0.55
M11 90/0.55
M14, M15, M19 10/0.5
M16, M18 25/0.55
TABLE II
BASIC CHARACTERISTICS OF THE CCCII+ (CMOS),

0
I = 100 A, 2.5V SUPPLY VOLTAGE
Voltage follower Current follower

Gain
-3dB Bandwidth
Input impedance
Output impedance
Offset current at Y
Output offset

0.973
950MHz
78K //0.28pF
371
1.24 A
5.5mV

0.927
380MHz
371
591K//0.14pF
1.24 A
2.19 A
16

TABLE III
BASIC CHARACTERICTICS OF THE CCCII+
0
I = 50 A, t2.5V SUPPLY VOLTAGE
BJT BiCMOS CMOS
Voltage
follower
Gain
-3dB bandwidth
Input impedance
Output impedance
Offset current at Y
Output offset
0.9984
1.1GHz
323K//0.54pF
263
2.1A
32V
0.996
1.5GHz
72K//0.55pF
228


89V
0.974
628MHz

132K//0.22pF
567
2.9A
5.5mV
Current
follower
Gain
-3dB bandwidth
Input impedance
Output impedance
Output offset

1.022
615MHz
263.8
319.6//0.5pF
3.4A
1.022
680MHz
228
276K//0.5pF

3.9A

0.974

290MHz

567

900K//0.15pF

2.2A
17
Fig. 10 Voltage transfer (
y x
v v / ) characteristics, when node X is opened and node Z
is grounded, and Current transfer (
x z
i i / ) characteristics, when nodes Y and Z are
grounded.
0
I = 100A, V+ = -V = 2.5V, Va = -Vb = 0.5V, Vc = Vd = 0V
Fig. 11 The simulated and calculated X-input impedance when
0
I = 100A, V+ =
-V = 2.5V, Va = -Vb = 0.5V, Vc = Vd = 0V
10
6
10
7
10
8
10
9
370
375
380
385
390
395
400
405
Simulated
Calculated
X
-
i
n
p
u
t

i
m
p
e
d
a
n
c
e



Z
x
Frequency (Hz)
(

)
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-40
-30
-20
-10
0
Voltage gain
Current gain
V
o
l
t
a
g
e

g
a
i
n

A
v
,

C
u
r
r
e
n
t

g
a
i
n

A
i

(
d
B
)
Frequency (Hz)
18
Since the circuit is current controlled, we are interested in the characteristics by
varying the value of the controlled current
o
I . Fig. 12 presents the variation of the
intrinsic
x
Z (see Fig. 9(d)) as a function of the dc bias current
o
I . Fig. 13 gives the
values
x
R obtained from SPICE simulations with the CCCII+, as well as the
theoretical ones calculated from Eq. (9). As shown, the simulated values of the
controlled resistance are in good agreement with theoretical ones. Deviations less
then 10% were obtained in the range 10A~500A for
o
I . The most important
deviation, which appear either for the very low or very high values of
o
I principally
come from the difference that exist between
o
I and the current of transistors M1 and
M3. These current deviations result from the current gains of transistors operating for
very high or very low values of currents. When the bias current
o
I is less then 10A,
the deviation is more then 10%; and when
o
I is more then 500A, the variation of
parasitic resistance
x
R is not evident, so the range of the controlled current is defined
from 10A~500A in practice. Simulation results show that its value is tunable from
172 to 1.65K.
The variation of voltage gain and current gain under the bias current
o
I can be seen
in Fig. 14. On the range from 10A~500A, the gain of voltage follower and current
follower are about unity. Fig. 15 presents the 3dB cutoff frequency of the voltage
follower and current follower, obtained by varying
o
I . The bandwidth of
v
A and
i
A
can be up to 2.1GHz and 640MHz respectively when
o
I = 500A.
19
(a)
(b)
0 100 200 300 400 500
400
800
1200
1600
2000
R
x
b
Bias current I
O
0 100 200 300 400 500
2.0k
4.0k
6.0k
8.0k
R
x
a
Bias current I
0
(A)
(A)
(

)
(

)
20
(c)
(d)
Fig. 12 The variation of the intrinsic
x
Z as a function of the dc bias current
o
I
0 100 200 300 400 500
0
2
4
6
8
10
L
x
Bias current I
0
(A)
(A)
(

H
)
0 100 200 300 400 500
0.175
0.180
0.185
0.190
0.195
0.200
C
x



(
p
F
)
Bias current I
o
21
Fig. 13 Theoretical and simulated values for
x
R (=
xa
R //
xb
R )
0 100 200 300 400 500
0
200
400
600
800
1000
1200
1400
1600
1800
Simulated
Theoretical
R
e
s
i
s
t
a
n
c
e


R
x
Bias current I
0
(A)
(

)
22
Fig. 14 The variation of voltage gain and current gain under the bias current
o
I
Fig. 15 The 3dB bandwidth of voltage follower and current follower, obtained by
varying
o
I
0 100 200 300 400 500
0
500
1000
1500
2000
Voltage follower
Current follower
3
d
B

b
a
n
d
w
i
d
t
h

(
M
H
z
)
Bias current I
0
0 100 200 300 400 500
0.0
0.5
1.0
1.5
2.0
A
v
A
i
V
o
l
t
a
g
e

g
a
i
n


A
v

,

C
u
r
r
e
n
t

g
a
i
n


A
i
Bias current I
0
(A)
(A)
23
IV. Second Order Bandpass Filter
The basic idea of a tunable bandpass filter is derived from a parallel RLC resonant
circuit, which resonant frequency and Q-factor can be tuned by a variable inductance
and a variable resistance. The variable inductance is implemented with two CCCII+s,
and a controlled negative impedance converter (NIC) in parallel with the RLC circuit
makes the resistance tunable.
A. Parallel RLC Resonant Circuit
The typically parallel RLC tank circuit is shown in Fig.16. Its resonant
frequency is

LC
1
0
(15)
and the quality factor Q of the parallel RLC network is:

L
C
R RC
L
R
Q
0
0

(16)
From Eq. (15) and Eq. (16), if the inductance is variable the
0
can be tuned; and also
if the resistance is variable the Q can be tuned.
The tunable inductance L is implemented with two CCCII+s connected as a gyrator,
and the tunable resistance is implemented with a CCCII+ connected as a negative
impedance converter (NIC). These will be described in the following sections.

Fig. 16 Parallel RLC tank circuit
I
in
V
out
R C L
24
B. Current-Controlled Active Inductance
Consider the circuit connection shown in Fig. 17(a), where the CCII+s are ideal.
The equivalent circuit derived from this connection is shown in Fig. 17(b), where the
equivalent inductance
eq
L is

1 2 1
C R R L
x x eq
(17)
The input resistances of practical CCII+s can take the place of the external resistances,
and these resistances are controllable as practical CCII+s are replaced by the CCCII+s.
The circuit is shown in Fig. 17(c) [6, 8].
(a)
(b)
Fig.17 Nonideal inductance: (a) Implementation from two CCII+ and two
external resistances (b) Electrical equivalent impedance
) (t I
in
) (t V
in
1 x
R
2 x
R
in
Z
1
C
CCII+ CCII+
X1
Y1
Z1 X2 Y2
Z2
in
Z
2 x
R
1 x
R
eq
L
Input
25





(c)
Fig.17 Nonideal inductance: (c) Implementation of the controlled inductance by
using the intrinsic parasitic resistance at terminal X of CCCII+
1 o
I
2 o
I
) (t I
in
) (t V
in in
Z
Z1 X1
Y1
X2 Y2
Z2
1
C
CCCII+ CCCII+
Input
26
C. Negative Impedance Converter

The parallel resistances
x
R s in Fig. 17(b) usually reduce the Q-factor. In order to
increase the Q-factor, we need to increase the resistance R in Fig. 16. A simple way to
increase R is using negative resistance in parallel with
x
R s, The negative resistance
can be implemented with a CCCII+ connected as Fig. 18 [6, 8,12].
To cancel the effect of the parasitic shunt resistors, a negative resistor in parallel
with the inductance is needed. The practical current conveyor can be configured in
such a way to perform the function of the negative impedance converter (NIC), which
is useful for implementation of the filter. The circuit represented in Fig. 18 simulates
a grounded negative resistance which value:
x in
R Z is current controlled. Since
the current through the input node is
x z y z
i i i i + , and
y x
v v , the input impedance
x x x in
R i v Z ) /( , that the circuit in Fig. 18 is a NIC.





Fig. 18 Negative resistor implemented from the CCCII+
o
I
in
Z
in
Z
) (t i
x
) (t i
z
x
R
Input
Input
CCCII+
Y Z
X
27
D. CCCII+ Bandpass Filter Design
1. Circuit Description and Analysis
Fig. 19 shows the current mode second-order elementary bandpass filter [6, 8].
The first and second CCCII+ and capacitor
1
C implement the inductance as previously
described. The third acts as a controlled negative resistance, as indicated in Fig. 20.
Finally, the fourth CCCII+ constitutes an output current source. The transfer function
of the filter is given by [8]

( )
2
2 1 2 1
1 2 1
4
1 2 1
1
) (
s C C R R s
R
C R R
s
R
C R R
s
I
I
x x
eq
x x
x
x x
in
out
+
1
1
]
1

+
1
]
1

,
_

(18)

and


1
]
1

+ +
3 4 2 1
1 1 1 1 1
x x x x eq
R R R R R
(19)
Its characteristic parameters are the following:

2 1 2 1
0
1
C C R R
x x
(20)


1
2
2 1
C
C
R R
R
Q
x x
eq
(21)
2.
o
f Tuning
From Eq. (20) and Eq. (21) it is obvious that one can modify the center frequency
o
f and the Q-factor independently of each other, the way to tune the center frequency
of the filter is to vary the value of
1 x
R and
2 x
R . Referring to Eq. (20), an appropriate
choice to simplify the tuning of
o
f is to use the same current
o
I for
1 o
I and
2 o
I .
Then it follows that
2 1 x x
R R , and we can modify
o
f by varying this current
o
I
keeping the other currents (
3 o
I and
4 o
I ) fixed.
28
3. Q Tuning
From Eq. (19) and Eq. (21) we can see that Q can be tuned either from
3 o
I or
4 o
I
(see Fig. 19) without affecting the value of
o
f and with a theoretical possibility of
making Q infinite if
eq
R in Eq. (19) tends to infinite. For example, let the first,
second and forth conveyors have the same bias current
o
I (i.e.,
2 1 x x
R R
x x
R R
4
),
when the input impedance of the third conveyor (NIC) is
3 x
R 3 /
x
R , the Q is
theoreticaly infinite. Thus when the bias current
o
I and
4 o
I are fixed, the Q-factor
can be modified just only by varying the current
3 o
I .


Fig. 19 Second order bandpass filter operating in current-mode
1 o
I
2 o
I
3 o
I
4 o
I
) (t I
in
) (t I
out
1
C
2
C
29
E. Practical Inductance, NIC and Bandpass Filter
However, the parasitic effects which can not be ignored will influence the
theoretical values. The parasitics at node X are more complex (see Section III and Fig.
9(d)), and there is a parasitic resistance
1 2
//
z y p
R R R in parallel with
1
C , also there
is an additional resistance
P x x p
R R R r / ) (
2 1
appears in series with
eq
L . When all the
parasitics of the controlled conveyors (i.e., parasitic impedance: ) // (
y y
C R , ) // (
z z
C R ,
and nonideal values of the voltage and current transfer
v
A and
i
A ) are taken into
account, rearrange the above equations, we can get that [6]

i v x x eq
A A C R R L /
1 2 1
(22)

P i v x x p
R A A R R r / ) (
2 1
(23)
The detail equivalent circuit for this controlled inductance is shown in Fig. 20(a).
Note that the input impedance
in
Z of the NIC shown in Fig. 18 is now replace
x
R
with Zx A A
i v
, and the transfer functions of the practical bandpass filter are [6]

2
'
2 1 2 1 1 2 1
4
1 2 1
1
) (
s
A A
C C R R
s
R A A
C R R
s
R A
C R R
s
I
I
i v
x x
eq i v
x x
x v
x x
in
out

,
_

+
1
1
]
1

+
1
]
1

,
_

(24)
where


xbn xan xn
R R R // n=1, 2, 3, 4 (25)

1
]
1

+ +
3 4 2 1
1 1 1 1
x
i v
x x x eq
R
A A
R R R R
(26)

2 1 1 y z
C C C + (27)
3 3 2
'
2 z y
C C C C + + (28)
30
Their characteristic parameters are given as

'
2 1 2 1
0
C C R R
A A
x x
i v
(29)

1
'
2
2 1
C
C
R R
R
A A Q
x x
eq
i v
(30)
The equivalent circuit of controlled inductance may be simplified as shown in Fig.
20(b) because ( )

,
_

<< +
x
xb x xa
sC
R sL R
1
// when operating in high frequency. The
voltage gain (
v
A ), and current gain (
i
A ) approximate to unity at low frequency, the
value of capacitor '
2 2
C C and
eq p
sL r << when the circuit is operated at high
frequency. See from the bandpass filter s input, this filter is now equivalent to a shunt
RLC circuit as shown in Fig.21 where
3 4 2 1 2
'
x x x x x
C C C C C C + + + and
4 2 1
// // '
xb xb xb x
R R R R .

(a)
(b)
Fig. 20 Parasitical current-controlled active inductance (a) It s detail equivalent
circuit, (b) The simplified circuit when operating in high frequency
eq
L
p
r
2 /
xa
R
2 /
x
L
x
C 2 2 /
xb
R
2 /
xb
R
x
C 2
p
r
eq
L
31





Fig. 21 The input impedance see from the bandpass filter s input
eq
L
'
x
C
'
x
R
3 xb
R
32
F. Simulation Results
Fig. 22(a) shows the value of this simulated inductance, using the CCCII+ with
100A bias current and 2.5V voltage sources. The circuit in Fig. 17(c) was
designed with
2 1 o o
I I = 100A, and the following parameters are extracted from the
design: C
1
= 0.42pF, R
xa1,2
= 2.25k, R
xb1,2
= 445, the parasitic inductance L
x1,2
=
0.66H, and the parasitic capacitor C
x1,2
= 0.18pF. Fig. 22(b) compares the impedance
variation of this circuit (Fig. 17(c)) in parallel with the value of ( ) 2
x
Z , and the
theoretical impedance ( )
eq p
sL r + . We can see a good agreement between both curves.
The values of
eq
L and
p
r extracted from the simulations: 0.9H and 2.1 were found
in good accordance with theoretical ones (0.92H and 3.2, respectively) from Eq. (22)
and Eq. (23).
The capacitor
2
C is always 2.3pF in our tunable bandpass filter design. Fig. 23
shows the tunability of the center frequency with the bias current
o
I (from Eq. (29)
and Eq. (30)). In this figure, we vary the current
o
I (50A, 100A, and 200A) with
350
4 3

o o
I I A. The higher the bias current
o
I , the higher the center frequency
o
f . Fig. 24 shows the tunability of the Q-factor with the current
3 o
I (Eq. (26) and
Eq. (30)). The controlled current
3 o
I is varier as 300A, 330A, 350A, and 360A
with 100
4

o o
I I A. From this simulation, it can be seen that Q-tuning is very
sensitive. Even with a small change of
3 o
I , the Q-factor changes largely. Besides,
we find that not only the Q-factor but also
o
f is tuned. This is because the parasitic
capacitors in parallel with
2
C which influence the center frequency (see Eq. (28)) are
also changed.
Fig. 25 indicates that this configuration is quite useful for an IF bandpass filter which
center frequency is from 200MHz to 300MHz which is within the IF design
specification of modern wireless mobile phone. The Q-factor in this configuration is
up to 800. Table IV lists the comparison among the tunable bandpass filter
implemented with BiCMOS [8] and CMOS.
Table IV
BiCMOS CMOS
o
f
30 MHz ~ 120MHz 55 MHz ~ 410MHz
Q 1 ~ 140 1~800
33
(a)
(b)
Fig. 22 Parasitical current-controlled active inductance (a) The simulated
inductance (b) Frequency variation of

,
_

,
_

2
//
X
in
Z
Z and ( )
eq p
sL r +
10
5
10
6
10
7
10
8
10
9
10
0
10
1
10
2
10
3


I
m
p
e
d
a
n
c
e
Frequency (Hz)

,
_

,
_

2
//
X
in
Z
Z
( )
eq p
sL r +
(

)
10
5
10
6
10
7
10
8
10
9
0
100
200
300
400
500
S
i
m
u
l
a
t
e
d

i
n
d
u
c
t
a
n
c
e



Z
L
Frequency (Hz)
(

)
34

Fig. 23 Second-order bandpass filter: frequency tuning.
4 3 o o
I I 350A and

2
C 2.3pF.
o
I 50A, 100A, and 200A.

Fig. 24 Second order bandpass filter: Q tuning.
3 o
I = 300A, 330A, 350A and
360A,
4 o o
I I 100A and
2
C 2.3pF
2.0x10
8
2.1x10
8
2.2x10
8
2.3x10
8
2.4x10
8
0
10
20
30
40
50




G
a
i
n

m
a
g
n
i
t
u
d
e

(
d
B
)
Frequency (Hz)
1.0x10
8
1.5x10
8
2.0x10
8
2.5x10
8
3.0x10
8
3.5x10
8
4.0x10
8
-20
-15
-10
-5
0
5
10



G
a
i
n

m
a
g
n
i
t
u
d
e

(
d
B
)
Frequency (Hz)
o
I = 50A
o
I =100A
o
I = 200A
3 o
I =300A
3 o
I =330A
3 o
I =350A
3 o
I =360A
35
V. Conclusion
The CMOS CCCII and the tunable bandpass IF filter based on the CCCII are
successfully developed. Simulations show that they are suitable for the application
around 200MHz~300MHz which is the specification of current wireless mobile phone.
36
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