TDA7440D

TONE CONTROL
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- 4 STEREOINPUTS
- SELECTABLEINPUT GAINFOR OPTIMAL
ADAPTATIONTO DIFFERENT SOURCES
ONE STEREOOUTPUT
TREBLE AND BASS CONTROL IN 2.0dB
STEPS
VOLUMECONTROL IN 1.0dB STEPS
TWOSPEAKERATTENUATORS:
- TWOINDEPENDENTSPEAKERCONTROL
IN 1.0dBSTEPS FOR BALANCEFACILITY
- INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
DESCRIPTION
The TDA7440D is a volume tone (bass and
treble) balance (Left/Right) processor for quality
audio applicationsin Hi-Fi systems.
Selectable input gain is provided. Control of all
the functionsis accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOSTechnology,
Low Distortion, Low Noise and DC stepping are
obtained
April 1999

0/30dB
2dB STEP
MUXOUTL INL
VOLUME
VOLUME
TREBLE
TREBLE
TREBLE(L)
MUXOUTR INR TREBLE(R)
BOUT(L)
SPKR ATT
LEFT
LOUT
SCL
SDA
DIG_GND
ROUT
D98AU883
I
2
CBUS DECODER + LATCHES
100K
100K
100K
100K
G
L-IN1
L-IN2
L-IN3
L-IN4
100K
100K
100K
100K
R-IN1
R-IN2
R-IN3
R-IN4
G
INPUT MULTIPLEXER
+ GAIN
BASS
BIN(L)
BASS
SPKR ATT
RIGHT
BOUT(R) BIN(R)
SUPPLY
CREF
AGND
V
S
27
4
5
6
7
3
2
1
28
21
22
20
26
24
25
10 11 19 12 13 23
8 9 18 14 15
R
B
R
B
V
REF
BLOCK DIAGRAM
ORDERING NUMBER: TDA7440D
SO28
1/16
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
S
Operating Supply Voltage 10.5 V
T
amb
Operating Ambient Temperature -10 to 85 C
T
stg
Storage Temperature Range -55 to 150 C
THERMAL DATA
Symbol Parameter Value Unit
Rth j-pin Thermal Resistance Junction-pins 85 C/W
L_IN3
L_IN4
MUXOUTL
IN(L)
MUXOUT(R)
BIN(R)
IN(R)
BOUT(R)
BIN(L)
1
3
2
4
5
6
7
8
9
BOUT(L)
N.C.
N.C.
TREBLE(R)
TREBLE(L)
SCL
SDA
DIG-GND
CREF 23
22
21
20
19
17
18
16
15
D98AU884
10
11
12
13
14
28
27
26
25
24
R_IN3
R_IN2
R_IN1
L_IN1
L_IN2 V
S
AGND
ROUT
LOUT
R_IN4
PIN CONNECTION (Top view)
QUICK REFERENCE DATA
Symbol Parameter Min. Typ. Max. Unit
V
S
Supply Voltage 6 9 10.2 V
V
CL
Max. input signal handling 2 Vrms
THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 0.1 %
S/N Signal to Noise Ratio V out = 1Vrms (mode = OFF) 106 dB
S
C
Channel Separation f = 1KHz 90 dB
Input Gain in (2dBstep) 0 30 dB
Volume Control (1dB step) -47 0 dB
Treble Control (2dB step) -14 +14 dB
Bass Control (2dB step) -14 +14 dB
Balance Control 1dB step -79 0 dB
Mute Attenuation 100 dB
TDA7440D
2/16
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25C, VS = 9V, RL= 10K,
RG = 600, all controls flat (G = 0dB), unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
V
S
Supply Voltage 6 9 10.2 V
I
S
Supply Current 4 7 10 mA
SVR Ripple Rejection 60 90 dB
INPUT STAGE
R
IN
Input Resistance 70 100 130 K
V
CL
Clipping Level THD = 0.3% 2 2.5 Vrms
S
IN
Input Separation The selected input is grounded
through a 2.2 capacitor
80 100 dB
Gi nmin Minimum Input Gain -1 0 1 dB
G
inman
Maximum Input Gain 29 30 31 dB
G
step
Step Resolution 1.5 2 2.5 dB
VOLUMECONTROL
R
i
Input Resistance 20 33 50 K
C
RANGE
Control Range 45 47 49 dB
A
VMAX
Max. Attenuation 45 47 49 dB
A
STEP
Step Resolution 0.5 1 1.5 dB
E
A
Attenuation Set Error A
V
= 0 to -24dB -1.0 0 1.0 dB
A
V
= -24 to -47dB -1.5 0 1.5 dB
E
T
Tracking Error A
V
= 0 to -24dB 0 1 dB
A
V
= -24 to -47dB 0 2 dB
V
DC
DC Step adjacent attenuation steps
from0dB to A
V
max
0
0.5
3 mV
mV
A
mute
Mute Attenuation 80 100 dB
BASS CONTROL (1)
Gb Control Range Max. Boost/cut +12.0 +14.0 +16.0 dB
B
STEP
Step Resolution 1 2 3 dB
R
B
Internal Feedback Resistance 33 44 55 K
TREBLE CONTROL (1)
Gt Control Range Max. Boost/cut +13.0 +14.0 +15.0 dB
T
STEP
Step Resolution 1 2 3 dB
SPEAKERATTENUATORS
C
RANGE
Control Range 70 76 82 dB
S
STEP
Step Resolution 0.5 1 1.5 dB
E
A
Attenuation Set Error A
V
= 0 to -20dB -1.5 0 1.5 dB
A
V
= -20 to -56dB -2 0 2 dB
V
DC
DC Step adjacent attenuation steps 0 3 mV
A
mute
Mute Attenuation 80 100 dB
NOTE1:
1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V doest reset the device.
2) BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
TDA7440D
3/16
ELECTRICAL CHARACTERISTICS (continued.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
AUDIOOUTPUTS
VCLIP Clipping Level d = 0.3% 2.1 2.6 VRMS
R
L
Output Load Resistance 2 K
RO Output Impedance 10 30 50
VDC DC Voltage Level 3.5 3.8 4.1 V
GENERAL
E
NO
Output Noise All gains = 0dB;
BW = 20Hz to 20KHz flat
5 15 V
E
t
Total Tracking Error A
V
= 0 to -24dB 0 1 dB
A
V
= -24 to -47dB 0 2 dB
S/N Signal to Noise Ratio All gains 0dB; VO = 1VRMS ; 95 106 dB
S
C
Channel Separation Left/Right 80 100 dB
d Distortion AV = 0; VI = 1VRMS ; 0.01 0.08 %
BUS INPUT
V
IL
Input Low Voltage 1 V
V
IH
Input High Voltage 3 V
IIN Input Current VIN = 0.4V -5 0 5 A
V
O
Output Voltage SDA
Acknowledge
IO = 1.6mA 0.4 0.8 V
10F 5.6nF
100nF 100nF
5.6K
2.2F
5.6nF
2.2F
100nF 100nF
5.6K
0.47F
0.47F
0.47F
0.47F
0.47F
0.47F
0.47F
0.47F
0/30dB
2dB STEP
MUXOUTL INL
VOLUME
VOLUME
TREBLE
TREBLE
TREBLE(L)
MUXOUTR INR TREBLE(R)
BOUT(L)
SPKR ATT
LEFT
LOUT
SCL
SDA
DIG_GND
ROUT
D98AU885
I
2
CBUS DECODER + LATCHES
100K
100K
100K
100K
G
L-IN1
L-IN2
L-IN3
L-IN4
100K
100K
100K
100K
R-IN1
R-IN2
R-IN3
R-IN4
G
INPUT MULTIPLEXER
+ GAIN
BASS
BIN(L)
BASS
SPKR ATT
RIGHT
BOUT(R) BIN(R)
SUPPLY
CREF
AGND
V
S
27
4
5
6
7
3
2
1
28
21
22
20
26
24
25
10 11 19 12 13 23
8 9 18 14 15
R
B
R
B
V
REF
TEST CIRCUIT
TDA7440D
4/16
APPLICATIONSUGGESTIONS
The first and the last stages are volume control
blocks. The control range is 0 to -47dB (mute) for
the first one, 0 to -79dB (mute) for the last one.
Both of themhave 1dB step resolution.
The very high resolution allows the implementation
of systems freefromany noisy acoustical effect.
The TDA7440D audioprocessor provides 3 bands
tones control.
Bass Stage
Several filter types can be implemented, connect-
ing external components to the Bass IN and OUT
pins.
The fig.1 refers to basic T Type Bandpass Filter
starting from the filter component values (R1 in-
ternal and R2,C1,C2 external) the centre fre-
quency Fc, the gain Av at max. boost and the fil-
ter Q factor are computed as follows:
F
C
=
1
2 R1 R2 C1 C2
A
V
=
R2 C2 + R2 C1 + Ri C1
R2 C1 + R2 C2
Q =
R1 R2 C1 C2
R2 C1 + R2 C2
Viceversa, once Fc, Av, and Ri internal value are
fixed, the external components values will be:
C1 =
A
V
1
2 F
C
R
i
Q
C2 =
Q
2
C1
AV 1 Q
2
R2 =
A
V
1 Q
2
2 C1 F
C
(A
V
1) Q
Treble Stage
The treble stage is a high pass filter whose time
constant is fixed by an internal resistor (25K
typical) and an external capacitor connected be-
tween treble pins and ground
Typical responses are reported in Figg. 10 to 13.
CREF
The suggested 10F reference capacitor (CREF)
value can be reduced to 4.7F if the application
requires faster power ON.
Ri internal
C
2
OUT IN
C
1
R
2
D95AU313
Figure 1.
Figure 2: THD vs. frequency Figure 3: THDvs. RLOAD
TDA7440D
5/16
Figure 4: Channel separationvs. frequency
Figure 6: Treble response
Figure 5: Bass response
R
i
= 44k
C9 = C10 = 100nF (Bout, Bin)
R3 = 5.6k
TDA7440D
6/16
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7440D and vice versa takes place through
the 2 wires I
2
C BUS interface, consisting of the
two lines SDA and SCL (pull-up resistors to posi-
tive supply voltage must be connected).
Data Validity
As shown in fig. 7, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.8 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferredfirst.
Acknowledge
The master (P) puts a resistive HIGHlevel on the
SDA line during the acknowledge clock pulse (see
fig. 9). The peripheral (audio processor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audio processor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmissionwithout Acknowledge
Avoiding to detect the acknowledge of the audio
processor, the P can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.
Figure 7: Data Validity on the I
2
CBUS
Figure 8: Timing Diagramof I
2
CBUS
Figure 9: Acknowledge on the I
2
CBUS
TDA7440D
7/16
SOFTWARE SPECIFICATION
InterfaceProtocol
The interface protocol comprises:
A start condition (S)
A chip address byte, containingthe TDA7440D
address
A subaddressbytes
A sequenceof data (N byte + acknowledge)
A stop condition (P)
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
S 1 0 0 0 1 0 0 0 ACK ACK DATA ACK P
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU420
X DATA
SUBADDRESS DATA 1 to DATA n
X X B
EXAMPLES
No Incremental Bus
The TDA7440D receives a start condition, the
correct chip address, a subaddresswith the B = 0
(no incremental bus), N-data (all these data con-
cern the subaddress selected), a stop condition.
S 1 0 0 0 1 0 0 0 ACK ACK DATA ACK P
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU421
X D3
SUBADDRESS DATA
X X 0 D2 D1 D0
Incremental Bus
The TDA7440D receive a start conditions, the
correct chip address, a subaddress with the B = 1
(incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas
SUBADDRESS from XXX1000 to XXX1111 of
DATAare ignored.
The DATA 1 concern the subaddress sent, and
the DATA 2 concern the subaddress sent plus
one in the loop etc, and at the end it receivers the
stop condition.
S 1 0 0 0 1 0 0 0 ACK ACK DATA ACK P
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU422
X D3
SUBADDRESS DATA 1 to DATA n
X X 1 D2 D1 D0
TDA7440D
8/16
POWERON RESET CONDITION
INPUT SELECTION IN2
INPUT GAIN 28dB
VOLUME MUTE
BASS 0dB
TREBLE 2dB
SPEAKER MUTE
DATA BYTES
Address = 88 HEX (ADDR:OPEN).
FUNCTIONSELECTION: First byte (subaddress)
MSB LSB
SUBADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
X X X B 0 0 0 0 INPUT SELECT
X X X B 0 0 0 1 INPUT GAIN
X X X B 0 0 1 0 VOLUME
X X X B 0 0 1 1 BASS
X X X B 0 1 0 0 NOT USED
X X X B 0 1 0 1 TREBLE
X X X B 0 1 1 0 SPEAKER ATTENUATE R
X X X B 0 1 1 1 SPEAKER ATTENUATE L
B = 1: INCREMENTAL BUS ACTIVE
B = 0: NO INCREMENTAL BUS
X = DONT CARE
INPUT SELECTION
MSB LSB
INPUT MULTIPLEXER
D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X 0 0 IN4
X X X X X X 0 1 IN3
X X X X X X 1 0 IN2
X X X X X X 1 1 IN1
In Incremental Bus Mode, the not used function must be addressed in any case. For example to re-
fresh Volume = 0dB and Speaker_R= -40dB, the following bytes must be sent:
SUBADDRESS XXX10010
VOLUME DATA X0000000
BUS DATA XXXX1111
NOT USED DATA XXXX1111
TREBLE DATA XXXX1111
SPEAKER_R DATA X0000010
TDA7440D
9/16
DATA BYTES (continued)
INPUT GAIN SELECTION
MSB LSB INPUT GAIN
D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS
0 0 0 0 0dB
0 0 0 1 2dB
0 0 1 0 4dB
0 0 1 1 6dB
0 1 0 0 8dB
0 1 0 1 10dB
0 1 1 0 12dB
0 1 1 1 14dB
1 0 0 0 16dB
1 0 0 1 18dB
1 0 1 0 20dB
1 0 1 1 22dB
1 1 0 0 24dB
1 1 0 1 26dB
1 1 1 0 28dB
1 1 1 1 30dB
GAIN= 0 to 30dB
VOLUMESELECTION
MSB LSB VOLUME
D7 D6 D5 D4 D3 D2 D1 D0 1dB STEPS
0 0 0 0dB
0 0 1 -1dB
0 1 0 -2dB
0 1 1 -3dB
1 0 0 -4dB
1 0 1 -5dB
1 1 0 -6dB
1 1 1 -7dB
0 0 0 0 0dB
0 0 0 1 -8dB
0 0 1 0 -16dB
0 0 1 1 -24dB
0 1 0 0 -32dB
0 1 0 1 -40dB
X 1 1 1 X X X MUTE
VOLUME = 0 to 47dB/MUTE
TDA7440D
10/16
DATA BYTES (continued)
BASS SELECTION
MSB LSB BASS
D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS
0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0 1 1 1 0dB
1 1 1 1 0dB
1 1 1 0 2dB
1 1 0 1 4dB
1 1 0 0 6dB
1 0 1 1 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB
TREBLE SELECTION
MSB LSB TREBLE
D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS
0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0 1 1 1 0dB
1 1 1 1 0dB
1 1 1 0 2dB
1 1 0 1 4dB
1 1 0 0 6dB
1 0 1 1 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB
TDA7440D
11/16
DATA BYTES (continued)
SPEAKERATTENUATE SELECTION
MSB LSB SPEAKER ATTENUATION
D7 D6 D5 D4 D3 D2 D1 D0 1dB
0 0 0 0dB
0 0 1 -1dB
0 1 0 -2dB
0 1 1 -3dB
1 0 0 -4dB
1 0 1 -5dB
1 1 0 -6dB
1 1 1 -7dB
0 0 0 0 0dB
0 0 0 1 -8dB
0 0 1 0 -16dB
0 0 1 1 -24dB
0 1 0 0 -32dB
0 1 0 1 -40dB
0 1 1 0 -48dB
0 1 1 1 -56dB
1 0 0 0 -64dB
1 0 0 1 -72dB
1 1 1 1 X X X MUTE
SPEAKERATTENUATION = 0 to -79dB/MUTE
TDA7440D
12/16
20K
20K
CREF
V
S
D96AU430
V
S
PINS: 23
V
S
D96AU434
20A
ROUT 24
LOUT
PINS: 26,27
V
S
D96AU426
20A
V
S
MIXOUT
GND
PINS: 8, 10
20A
V
S
100K
V
REF
D96AU425
IN
PINS: 1, 2, 3, 4, 5, 6, 7, 28
20A
V
S
33K
D96AU427
INL
INR
V
REF
PINS: 19, 11
44K
V
S
BIN(R) D96AU428
20A
BIN(L)
PINS: 12,14
TDA7440D
13/16
50K
V
S
TREBLE(R)
D96AU433
20A
TREBLE(L)
PINS: 18, 19
44K
V
S
BOUT(R) D96AU429
20A
BOUT(L)
PINS: 13, 15
D96AU423
20A
SDA
PINS: 21
D96AU424
20A
SCL
PINS: 20
TDA7440D
14/16
SO28
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.65 0.104
a1 0.1 0.3 0.004 0.012
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.013
C 0.5 0.020
c1 45 (typ.)
D 17.7 18.1 0.697 0.713
E 10 10.65 0.394 0.419
e 1.27 0.050
e3 16.51 0.65
F 7.4 7.6 0.291 0.299
L 0.4 1.27 0.016 0.050
S 8 (max.)
OUTLINE AND
MECHANICAL DATA
TDA7440D
15/16
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of use of such information nor for any infringement of patents or other rights of third parti es which may result from its use. No li cense is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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TDA7440D
16/16
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