RT9202
RT9202
RT9202
I
OCSET
vs. Temperature
20
25
30
35
40
45
50
55
-40 -10 20 50 80 110 140
Temperature ( C)
I
O
C
S
E
T
(
A
)
Falling
Rising
Oscillator Frequency vs. Temperature
270
275
280
285
290
295
300
305
310
315
-50 0 50 100 150
Temperature ( C)
F
r
e
q
u
e
n
c
y
(
k
H
z
)
RT9202
DS9202-02 August 2002 www.richtek.com
9
Functional Description
The RT9202 operates at either single 5V power
supply with a bootstrap UGATE driver or 5V/12V
dual-power supply form the ATX SMPS. The dual-
power supply is recommended for high current
application, the RT9202 can deliver higher gate
driving current while operating with ATX SMPS based
on dual-power supply.
The Bootstrap Operation
In a single power supply system, the UGATE driver of
RT9202 is powered by an external bootstrap circuit,
as the Fig.1. The boot capacitor, C
BOOT
, generates a
floating reference at the PHASE pin. Typically a
0.1F C
BOOT
is enough for most of MOSFETs used
with the RT9202. The voltage drop between BOOT
and PHASE is refreshed to a voltage of VCC diode
drop (V
D
) while the low side MOSFET turning on.
Fig.1 Single 5V power Supply Operation
Dual Power Operation
The RT9202 was designed to regulate a 6.0V at VCC
pin automatically when BOOT pin is powered by 12V.
In a system with ATX 5V/12V power supply, the
RT9202 is ideal for higher current application due to
the higher gate driving capability, V
UGATE
= 7V and
V
LGATE
= 6.0V. A RC (10/1F) filter is also
recommended at BOOT pin to prevent the ringing
induced from fast power on, as shown in Fig.2.
Fig.2 Dual Power Supply Operation
Power On Reset
The Power-On Reset (POR) monitors the supply
voltage (normal +5V) at the VCC pin and the input
voltage at the OCSET pin. The VCC POR level is
4.1V with 0.5V hysteresis and the normal level at
OCSET pin is 1.5V (see over-current protection). The
POR function initiates soft-start operation after all
supply voltages exceed their POR thresholds.
Soft Start
A built-in soft-start is used to prevent surge current
from power supply input during power on. The soft-
start voltage is controlled by an internal digital
counter. It clamps the ramping of reference voltage at
the input of error amplifier and the pulse-width of the
output driver slowly. The typical soft-start duration is
2mS.
Over-Current Protection
The over current protection (OCP) function of the
RT9202 is triggered when the voltage across the
R
DS(ON)
of upper side MOSFET that developed by
drain current exceeds over-current tripping level. An
external resistor (R
OCSET
) programs the over-current
tripping level of the PWM converter. As shown on
Fig.1, the internal 40A current sink (I
OCSET
) develops
a voltage across R
OCSET
(V
SET
) that is referenced to
V
IN
. The DRIVE signal enables the over-current
comparator (OC). When the voltage across the upper
MOSFET (V
DS(ON)
) exceeds V
SET
, the over-current
+
BOOT
UGATE
PHASE
LGATE
RT9202
VCC
D1
0.1F
5V
R1
C2
1F
VCC
+
BOOT
UGATE
LGATE
6.0V
Regulator
VCC
5V
R1
10
C2
1F
C1
1F
12V VCC
RT9202
RT9202
www.richtek.com DS9202-02 August 2002
10
comparator trips to set the over-current latch. Both
V
SET
and V
DS
are referenced to V
IN
and a small
capacitor across R
OCSET
helps V
OCSET
tracking the
variations of V
IN
due to MOSFET switching. The over-
current function will be tripped at a peak inductor
current (I
PEAK
) determined by:
The OC trip point varies with MOSFETs R
DS(ON)
temperature variations. The temperature coefficient
of I
OCSET
is 2500ppm that is used to compensate
R
DS(ON)
temperature variations. To avoid over-current
tripping in the normal operating load range,
determine the R
OCSET
resistor value from the equation
above with:
1. The maximum R
SD(ON)
at the highest junction
temperature
2. The minimum I
OCSET
from the characteristics
3. Determine I
PEAK
for I
PEAK
> I
OUT(MAX)
+ (I)/2
where I is the output inductor ripple current.
Fig.3
Under Voltage and Over Voltage Protection
The voltage at FB pin is monitored and protected
against OC (over current), UV (under voltage), and
OV (over voltage). The UV threshold is 0.5V and OV-
threshold is 1.0V. Both UV/OV detection have 30S
triggered delay. When OC or UV trigged, a hiccup re-
start sequence will be initialized, as shown in Fig.4.
Only 3 times of trigger are allowed to latch off. Hiccup
is disabled during soft-start interval.
Fig. 4
Shutdown
Pulling low the OCSET pin by a small single
transistor can shutdown the RT9202 PWM controller
as shown in typical application circuit.
+
_
GATE
CONTROL
PWM
OC
DRIVE
VCC
UGATE
PHASE
R
OCSET
OCSET
I
OCSET
40A
V
PHASE
= V
IN
- V
DS
V
OCSET
= V
IN
- V
SET
V
SET+
OVER-CURRENT TRIP:
V
DS
> V
SET
iD
R
DS(ON)
> I
OCSET
R
OCSET
V
IN
= +5V
i
D
V
DS+
0A
0V
2V
4V
I
n
t
e
r
n
a
l
S
S
I
N
D
U
C
T
O
R
C
U
R
R
E
N
T
T0T1 T2 T3
TIME
COUNT = 1 COUNT = 2 COUNT = 3
OVERLOAD
APPLIED
RT9202
DS9202-02 August 2002 www.richtek.com
11
Applications Information
Inductor Selection
The RT9202 was designed for V
IN
= 5V, step-down
application mainly. Fig.5 shows the typical topology
and waveforms of step-down converter.
The ripple current of inductor can be calculated as
follows:
IL
RIPPLE
= (5V - V
OUT
)/L T
ON
Because operation frequency is fixed at 300kHz,
T
ON
= 3.33 V
OUT
/5V
The V
OUT
ripple is
V
OUT RIPPLE
= IL
RIPPLE
ESR
ESR is output capacitor equivalent series resistor
Table 1 shows the ripple voltage of V
OUT
: VIN = 5V
Table 1
Fig.5
V
OUT
3.3V 2.5V 1.5V
Inductor 2H 5H 2H 5H 2H 5H
1000F (ESR=53m) 100mV 40mV 110mV 44mV 93mV 37mV
1500F (ESR=33m) 62mV 25mV 68mV 28mV 58mV 23mV
3000F (ESR=21m) 40mV 16mV 43mV 18mV 37mV 15mV
*Refer to Sanyo low ESR series (CE, DX, PX)
The suggested L and C are as follows:
2H with 1500F C
OUT
5H with 1000F C
OUT
T
ON
T
OFF
T
S
V
L
V
I
-
V
O
-
V
O
I
L
= I
O
i
L Q
I
L
i
Q
I
Q
i
D
I
D
C.C.M.
V
L
R V
O
L
D C
Q
V
I
RT9202
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12
Input / Output Capacitor
High frequency/long life decoupling capacitors should
be placed as close to the power pins of the load as
physically possible. Be careful not to add inductance
to the PCB trace, as it could eliminate the
performance from utilizing these low inductance
components. Consult with the manufacturer of the
load on specific decoupling requirements.
The output capacitors are necessary for filtering
output and stabilizing the close loop (see the PWM
loop stability). For powering advanced, high-speed
processors, it is required to meet with the
requirement of fast load transient, high frequency
capacitors with low ESR/ESL capacitors are
recommended.
Another concern is high ESR induced ripple may
trigger UV or OV protections.
PWM Loop Stability
The RT9202 is a voltage mode buck controller
designed for 5V step-down applications. The gain of
error amplifier is fixed at 35dB for simplified design.
The output amplitude of ramp oscillator is 1.6V, the
loop gain and loop pole/zero are calculated as
follows:
DC loop gain G
A
= 35dB
LC filter pole P
O
=
Error Amp pole P
A
= 300kHz
ESR zero Z
O
= ESR C
The RT9202 Bode plot as shown Fig.6 is stable in
most of application conditions.
Reference Voltage
Because RT9202 use a low 35dB gain error amplifier,
shown in Fig. 7. The voltage regulation is dependent
on V
IN
& V
OUT
setting. The FB reference voltage of
0.8V were trimmed at V
IN
= 5V & V
OUT
= 2.5V
condition. In a fixed V
IN
= 5V application, the FB
reference voltage vs. V
OUT
voltage can be calculated
as Fig. 8.
Fig. 7
Fig. 8
Feedback Divider
The reference of RT9202 is 0.8V. The output voltage
can be set using a resistor based divider as shown in
Fig.9. Put the R1 and R2 as close as possible to FB
pin and R2 should less than 1 k to avoid noise
coupling. The C1 capacitor is a speed-up capacitor
for reducing output ripple to meet with the
requirement of fast transient load. Typically a 1nF ~
0.1F is enough for C1.
Loop Gain
V
OUT
= 1.5V
V
OUT
= 2.5V
V
OUT
= 3.3V
Z
O
= 3.2kHz
P
O
= 2.9kHz
L=2H
C
OUT
= 1500F(33m)
V
OUT
= 3.3V
40
30
20
10
1M 100k 10k 1k 100
Fig. 6
+
_
+
_
EA
+
_
PWM
REP
0.8V
I3
56K
I2
1K
FB
RAMP
1.75V
F
B
(
V
)
V
OUT
(V)
VIN = 5V
4 3.5 3 1 1.5 2 2.5
0.82
0.78
0.80
0.81
0.79
0.5 4.5
LC
2
1
2
1
6 . 1
5
VOUT
8 . 0
RT9202
DS9202-02 August 2002 www.richtek.com
13
Fig. 9
PWM Layout Considerations
MOSFETs switch very fast and efficiently. The speed
with which the current transitions from one device to
another causes voltage spikes across the
interconnecting impedances and parasitic circuit
elements. The voltage spikes can degrade efficiency
and radiate noise, that results in ocer-voltage stress
on devices. Careful component placement layout and
printed circuit design can minimize the voltage spikes
induced in the converter. Consider, as an example,
the turn-off transition of the upper MOSFET prior to
turn-off, the upper MOSFET was carrying the full load
current. During turn-off, current stops flowing in the
upper MOSFET and is picked up by the low side
MOSFET or Schottky diode. Any inductance in the
switched current path generates a large voltage spike
during the switching interval. Careful component
selections, layout of the critical components, and use
shorter and wider PCB traces help in minimizing the
magnitude of voltage spikes.
There are two sets of critical components in a DC-DC
converter using the RT9202. The switching power
components are most critical because they switch
large amounts of energy, and as such, they tend to
generate equally large amounts of noise. The critical
small signal components are those connected to
sensitive nodes or those supplying critical bypass
current.
The power components and the PWM controller
should be placed firstly. Place the input capacitors,
especially the high-frequency ceramic decoupling
capacitors, close to the power switches. Place the
output inductor and output capacitors between the
MOSFETs and the load. Also locate the PWM
controller near by MOSFETs.
A multi-layer printed circuit board is recommended.
Fig.10 shows the connections of the critical
components in the converter. Note that the capacitors
CIN and COUT each of them represents numerous
physical capacitors. Use a dedicated grounding plane
and use vias to ground all critical components to this
layer. Apply another solid layer as a power plane and
cut this plane into smaller islands of common voltage
levels. The power plane should support the input
power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the
PHASE node, but it is not necessary to oversize this
particular island. Since the PHASE node is subjected
to very high dV/dt voltages, the stray capacitance
formed between these island and the surrounding
circuitry will tend to couple switching noise. Use the
remaining printed circuit layers for small signal
routing. The PCB traces between the PWM controller
and the gate of MOSFET and also the traces
connecting source of MOSFETs should be sized to
carry 2A peak currents.
Fig. 10
+
+
+
LOAD
RT9202
VCC GND
FB
LGATE
UGATE
V
OUT
IQ1 IL
Q1
Q2
IQ2
5V
GND
VIN
C
OUT
+
V
OUT
RT9202
FB
L
R1
R2
< 1K
C1
RT9202
www.richtek.com DS9202-02 August 2002
14
Package Information
Dimensions In Millimeters Dimensions In Inches
Symbol
Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 3.988 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.178 0.254 0.007 0.010
I 0.102 0.254 0.004 0.010
J 5.791 6.198 0.228 0.244
M 0.406 1.270 0.016 0.050
F
A
J
B
D I
C
M
H
RT9202
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RT9202
www.richtek.com DS9202-02 August 2002
16
RICHTEK TECHNOLOGY CORP.
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
RICHTEK TECHNOLOGY CORP.
Taipei Office (Marketing)
8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)89191466 Fax: (8862)89191465
Email: [email protected]