The Stack, Subroutines, Interrupts and Resets

In many computers, memory is divided into three

distinct areas:
program area
data area
stack
The stack is an area of memory used for the temporary
storage of information. Subroutines and interrupts
make use of the stack.
The stack pointer (SP) is a register within the P that
contains the address of the net !ocation avai!ab!e
for the stack.
The P"s interna! !ogic causes the SP to decrement
automatica!!y when data is stored in the stack and
to automatica!!y increment when it is removed.
Therefore, the SP must initia!!y be set to the highest
address in the stack area (ca!!ed the top of the stack
initia!!y).
e.g., if the stack is to occupy !ocations #$%$$ to #$%&&
then use '(S )#$%&& instruction as initia!i*ation
before using the stack.
+
SP instructions are:
, (-S SP , + SP
, I.S SP / + SP
, '(S 0:0 / + SP (in immediate, direct, etended
and indeed modes)
, STS SP 0:0 / + (in direct, etended and
indeed modes)
, T1S I1 , + SP
, TS1 SP / + I1
, T2S I2 , + SP
, TS2 SP / + I2
P3S4 and P3'' Instructions
The push (PS4) and pu!! (P3') instructions store and
!oad data to and from the stack.
5 PS45 (or 6 or 1 or 2) writes the contents of the
specified register in the stack at the SP !ocation and then
decrements the SP once (for PS45 and PS46) or twice
(for PS41 and PS42) because the origina! stack
!ocation is no !onger vacant but contains the pushed
data.
5 P3'5 (or 6 or 1 or 2) first increments the SP once
to point to the !ast item that has been inserted into the
stack and then transfers the contents of the stack
appropriate!y to the specified register.
%
.ote that the stack acts as a 'ast,In,&irst,7ut ('I&7)
structure. 5 P3'' retrives the information that was !ast
P3S4ed onto the stack.
8
9
Subroutines
:hen the same function is re;uired more than one in a
program, it is fre;uent!y written as a subroutine,
5 subroutine can be used any number of times by the
main program.
This capabi!ity is provided by the fo!!owing three
instructions<
o =S> (?ump to subroutine)
o 6S> (branch to subroutine)
o >TS (return from subroutine)
@
=S> instruction has both indeed and etended modes.
:ith the comp!ete eucution of =S>, the address of the
net instruction to be eecuted (the one fo!!owing the
=S>) is stored automatica!!y in the stack
Then the PA is changed appropriate!y according to the
addressing mode used for =S>
B
6S> (branch to subroutine) has on!y the re!ative
addressing mode and the subroutine start address is
ca!cu!ated by the AP3 by using the offset.
-ach subroutine must have >TS (return from
subroutine) as the !ast insatruction of the subroutine.
:ith the eecution of the >TS, the AP3 restores the PA
from the stack again automatica!!y and therefore the
program returns back to the instruction where it has !eft
before the ?ump or branch to the subroutine. The
fo!!owing eamp!e is for the etended case in the above
figure:
C
Dn/8E 4
Dn/8E '
.ested subroutines: Since PA saving and recovery is
automatic by the use of stack, it is possib!e to eecute
nested subroutines as fo!!ows.
If the stack is used for register savings in a subroutine,
the recovery shou!d be done in the reverse order and in
a ba!anced fashion
F
-amp!e: If a subroutine uses accumu!ators 5 and 6
and the AA>, how can the main program preserve
the contents of these registers G
The first four instruction of the subroutine may be
7pcode 0nemonic
8B PS45
8C PS46
$C TP5
8B PS45
which puts 5, 6 and AA> on the stack as fo!!ows:
>estore order before the >TS:
7pcode 0nemonic
8% P3'5
$B T5P
88 P3'6
8% P3'5
8H >TS
H
Aontents of the stack after
entering the subroutineand
eecuting the first four
instructions
-amp!e: So!ve eamp!e H (s;uare from a !ookup tab!e)
as a subroutine and use it in a main program to
ca!cu!ate the s;ure of two numbers. 5!so pass the
input parameter and the output parameter using
accumu!ator 5 on!y. (o not use !oc. #9$ and #9+
any more.
!abe! mnemonic comment
SI> '(1 )SIT56 !oad base of tab!e
TST5 check input number
6-I &73.( if it is *ero, stop
searching and goto
&73.(
A7.T I.1 point to the net
tab!e entry
(-A5 decrement 5
6.- A7.T and repeat for a
number of times
&73.( '(55 #$$,1 get the
corresponding tab!e
entry
>TS
05I. '(55 )#$@ get the input data
=S> SI>
ST55 #9+ store the first resu!t
'(55 )#$B
=S> SI>
ST55 #9% store the second
resu!t
-.( 6>5 -.(
+$
-amp!e: :rite an 0BF4A++ program, which performs
the fo!!owing task:
data array starts in memory !ocation #$@$$
!ength of the array is in memory !ocation #$$9$.
Some of the e!ements of the given array wi!! be
p!aced to another area in the memory starting at
!ocation #$H$$.
-ach e!ement of the origina! array wi!! be checked
whether it is a %,digit va!id 6A( number or not and
wi!! be p!aced in the new array by reversing its bit
order if it is va!id,
i.e,
if the content of the memory !ocation #$@$$, for
eamp!e, is a va!id %,digit 6A( number
1
C
1
B
1
@
1
9
1
8
1
%
1
+
1
$
then 1
$
1
+
1
%
1
8
1
9
1
@
1
B
1
C
wi!!
be stored to the memory !ocation #$H$$. If the
number is not a va!id %,digit 6A( number, then it
wi!! not be stored.
5t the end, the memory !ocation #$$9+ wi!! ho!d the
tota! number of bytes in the new array.
:rite the 6A( checking part of your code as a
subroutine.
++
So!ution: (write comments for the program as an
eercise)
05I.
'(S )#ST5AJ65S-
'(1 )#$@$$
'(56 #9$
ST56 62T-A73.T
'(2 )#$H$$
A7.T
'(55 #$$,1
=S> A4J6A(
6.- A7.T%
K5'I(
'(56 )#$F
ST56 6ITA73.T no need
A7.TS4I&T
'S'5
>7> #$$,2
(-A6
6.- A7.TS4I&T
I.2
A7.T%
I.1
(-A 62T-A73.T
6.- A7.T
-.(
6>5 -.(
+%
A4J6A(
PS45
A'>5
T5P
P3'5
T56
(55
A65
>TS
Interrupts and Resets
5n interrupt is an hardware (sometimes software)
initiated subroutine ca!!
(epending on the type of the interrupt and the !ogic
state of the I bit in the condition code register, the AP3
may suspend its norma! operation and service the
interrupt.
The software used in response to the interrupt signa! is
ca!!ed an interrupt service subroutine.
5fter the interrupt service subroutine is eecuted, the
AP3 returns to the origina! program and resumes
eecution as if no interrupt occurred.
+8
This re;uires the AP3"s registers to be saved when AP3
services an interrupt and returned una!tered when the
routine is finished.
5n interrupt service subroutine ends with an >TI
instruction which automatica!!y returns the AP3
registers.
Interrupt vectors
5!! resets and interrupts use vectors indicating the start
address of reset or interrupt routines.
+9
+@
-amp!e:
#&&&% $$
#&&&8 --
#$$-- C-
#$$-& $$
#$$&$ 8$
#$$8$ 6B
#$$8+ ++
#$$8% 5%
Interrupt masks and enables
5n interrupt signa! may or may not be recogni*ed under
programmer"s contro! by most!y setting the interrupt
mask bit (I bit) in the AP3"s AA>.
If I L +, AP3 does not recogni*e interrupt signa!s LM
Interrupts are masked.
I bit can be set by using the S-I instruction and c!eared
by using the A-I instruction.
+B
Fixed by the system
Vector jump table
Aan be initia!i*ed as
'(55 )#C-
ST55 #--
'(1 )#$$8$
ST1 #-&
Interrupt service subroutine
:hen an interrupt re;uest occurs AP3 pushes a!! AP3
register va!ues to stack in the order: PA, I2, I1, 5AA5,
5AA65, AA> (pushing !ow byte first for +B,bit
registers).
:hen >TI is eecuted the data is pu!!ed from the stack
and the registers are restored.
&or >-S-T: .o stacking of the registers.
Hardware interrupts and resets
>-S-T: -ecuted whenever the chip is powered up,
whenever the eterna!
RESET
pin is activated. 4ighest
priority.
7ther processor resets: Aomputer 7perating Proper!y
(A7P) fai!ure reset, A7P c!ock monitor fai! reset,
.onmaskab!e interrupt (1I>I): is used to hand!e the
highest priority interrupts.
:hen you power up or >-S-T BF4A++, 1I>I is
masked, i.e. 1 bit in AA> is set.
To c!ear 1, T5P (Transfer from 5AA5 to AA>)
instruction shou!d be used.
Interrupt >e;uest (I>I): is maskab!e by setting bit I in
the AA>.
+C
I>I versus 1I>I
+. AP3 can ignore the I>I input if the I f!ag is +< it
can ignore 1I>I if the 1 f!ag is +. 4owever I f!ag
can be set and c!eared any time by software. 1 f!ag
can be c!eared on!y once, then it remains at $.
%. I>I can be programmed as a !eve!,sensitive or
edge,sensitive input via the I>I- bit in the
7PTI7. (at #+$8H) register. 1I>I is a!ways !eve!
sensitive.
8. 1I>I input has higher priority over I>I input.
:hen they are activated simu!taneous!y (whi!e
1LIL$), AP3 wi!! respond to 1I>I first.
+F
BF4A++
I>I
1I>I
Sotware and !"# control interrupts
Software interrupt (S:I): &orces the AP3 to respond
the same as it does to an eterna!!y generated interrupt.
3sefu! in he!ping to debug the programs. .ot maskab!e
by either I or 1 bits in AA>.
:ait for Interrupt (:5I): BF4A++ reduces its power
whi!e waiting to be woken up. 5!! registers are stacked.
7n!y an unmasked interrupt wi!! wake up the contro!!er.
ST7P: If S bit in AA> is set, ST7P performs !ike a
.7P. If S bit is reset, a!! interna! c!ocks ha!t, thus
ha!ting eecution. To wake up the contro!!er, >-S-T,
1I>I or I>I (when IL$) must be used.
+H
%$