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Vlsi Design Cia2

This document contains an internal assessment for a digital logic design course. It has two parts - Part A contains 10 multiple choice questions related to topics like logical effort, Verilog coding, interconnect delay, static power dissipation, rise time, design corners, SOC, Monte Carlo simulation, and latch up. Part B contains 4 questions - two questions ask to explain power dissipation methods and D flip-flop Verilog code, and the other two ask about latches, constant field scaling, reliability problems in CMOS chips, and a 1-to-4 decoder using NAND gates and a USIM model summary. The assessment is for first year ECE students and aims to evaluate their understanding of basic digital design and Verilog

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58 views2 pages

Vlsi Design Cia2

This document contains an internal assessment for a digital logic design course. It has two parts - Part A contains 10 multiple choice questions related to topics like logical effort, Verilog coding, interconnect delay, static power dissipation, rise time, design corners, SOC, Monte Carlo simulation, and latch up. Part B contains 4 questions - two questions ask to explain power dissipation methods and D flip-flop Verilog code, and the other two ask about latches, constant field scaling, reliability problems in CMOS chips, and a 1-to-4 decoder using NAND gates and a USIM model summary. The assessment is for first year ECE students and aims to evaluate their understanding of basic digital design and Verilog

Uploaded by

Anonymous GTb7FF3sTr
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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HINDUSTHAN INSTITUTE OF TECHNOLOGY, COIMBATORE 32

DEPARTMENT OF ECE
Internal Assessent II ! MARCH 2"#$
%I SEMESTER &B'E ECE(
EC23)$!%LSI DESIGN
DATE* #2'"3'#$ FN TIME* #'3" HOURS MA+'MAR,S* )"
PART A #" - 2 . 2"
ANS/ER ALL 0UESTIONS

1. Define logical effort and write the expression.
2. Write a Verilog coding for CMOS inverter in switch level model.
3. Wh does interconnect increase the circ!it dela"
#. What are the factors that ca!se static power dissipation"
$. Define %ise time.
&. Define design or process corner.
'. What is S()C* and write the a++reviation of S()C*"
,. What is meant + monte carlo sim!lation"
-. Define set!p time.
1.. What is /atch !p"
PART! B 2- #). 3"
11. a0 i0 *xplain Power dissipation and power reduction methods in
Detail with necessary equation and diagrams 11.0
ii0 Write a Verilog code for D23lip flop. )n +ehavioral level
modelling. 1$0
&OR(
+0 i0 With neat diagram explain the (!lsed and resetta+le latch. 11.0
ii0 Write short notes on Constant field4 Voltage and /ateral
scaling. 1$0

12. a0 i0 *xplain the different relia+ilit pro+lems related to the design
of relia+le CMOS chips. 11$0

&OR(
+0 i0 Draw the logic diagram of # to 1 M56 !sing 787D gates
with logic e9!ation and write the Verilog :D/ in gate level
modeling. 11.0
ii0 Write short notes on ;S)M model. 1$0
******ALL THE BEST*****
HINDUSTHAN INSTITUTE OF TECHNOLOGY, COIMBATORE 32
DEPARTMENT OF ECE
Internal Assessent II ! MARCH 2"#$
%I SEMESTER &B'E ECE(
EC23)$!%LSI DESIGN
DATE* #2'"3'#$ FN TIME* #'3" HOURS MA+'MAR,S* )"
PART A #" - 2 . 2"
ANS/ER ALL 0UESTIONS

1. Define logical effort and write the expression.
2. Write a Verilog coding for CMOS inverter in switch level model.
3. Wh does interconnect increase the circ!it dela"
#. What are the factors that ca!se static power dissipation"
$. Define %ise time.
&. Define design or process corner.
'. What is S()C* and write the a++reviation of S()C*"
,. What is meant + monte carlo sim!lation"
-. Define set!p time.
1.. What is /atch !p"
PART! B 2- #). 3"
11. a0 i0 *xplain Power dissipation and power reduction methods in
Detail with necessary equation and diagrams 11.0
ii0 Write a Verilog code for D23lip flop. )n +ehavioral level
modelling. 1$0
&OR(
+0 i0 With neat diagram explain the (!lsed and resetta+le latch. 11.0
ii0 Write short notes on Constant field4 Voltage and /ateral
scaling. 1$0

12. a0 i0 *xplain the different relia+ilit pro+lems related to the design
of relia+le CMOS chips. 11$0

&OR(
+0 i0 Draw the logic diagram of # to 1 M56 !sing 787D gates
with logic e9!ation and write the Verilog :D/ in gate level
modeling. 11.0
ii0 Write short notes on ;S)M model. 1$0
******ALL THE BEST*****

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