MC14007UB

Dual Complementary Pair

Plus Inverter
The MC14007UB multipurpose device consists of three
Nchannel and three Pchannel enhancement mode devices packaged
to provide access to each device. These versatile parts are useful in
inverter circuits, pulseshapers, linear amplifiers, high input
impedance amplifiers, threshold detectors, transmission gating, and
functional gating.

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MARKING
DIAGRAMS

Diode Protection on All Inputs

Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Lowpower TTL Loads or One Lowpower

14
PDIP14
P SUFFIX
CASE 646

Schottky TTL Load Over the Rated Temperature Range

PinforPin Replacement for CD4007A or CD4007UB
This device has 2 outputs without ESD Protection. Antistatic
precautions must be taken.

MC14007UBCP
AWLYYWW
1
14

SOIC14
D SUFFIX
CASE 751A

14007U
AWLYWW
1
14

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol
VDD
Vin, Vout

Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)

Value

Unit

0.5 to +18.0

0.5 to VDD + 0.5

14
007U
ALYW
1
14

Input or Output Current

(DC or Transient) per Pin

10

PD

Power Dissipation,
per Package (Note 3.)

500

mW

TA

Ambient Temperature Range

55 to +125

Tstg

Storage Temperature Range

65 to +150

TL

Lead Temperature
(8Second Soldering)

260

Iin, Iout

TSSOP14
DT SUFFIX
CASE 948G

mA

SOEIAJ14
F SUFFIX
CASE 965

MC14007U
ALYW
1

2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/
C From 65
C To 125
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.

A
WL, L
YY, Y
WW, W

= Assembly Location
= Wafer Lot
= Year
= Work Week

ORDERING INFORMATION
Device

Package

Shipping

MC14007UBCP

PDIP14

2000/Box

MC14007UBD

SOIC14

55/Rail

MC14007UBDR2

SOIC14

2500/Tape & Reel

MC14007UBDT

TSSOP14

96/Rail

MC14007UBF

SOEIAJ14

See Note 1.

MC14007UBFEL

SOEIAJ14

See Note 1.

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local
ON Semiconductor representative.

Semiconductor Components Industries, LLC, 2000

August, 2000 Rev. 4

Publication Order Number:

MC14007UB/D

MC14007UB
PIN ASSIGNMENT
D-PB

14

VDD

S-PB

13

D-PA

GATEB

12

OUTC

S-NB

11

S-PC

D-NB

10

GATEC

GATEA

S-NC

VSS

D-NA

D = DRAIN
S = SOURCE

SCHEMATIC
14

13

11

12

10

VDD = PIN 14
VSS = PIN 7

A
12

9
B

1
C

INPUT

VDD
14

C
11

INPUT OUTPUT CONDITION

1
0

13

INPUT

A = C, B = OPEN
A = B, C = OPEN

Substrates of Pchannel devices internally

connected to VDD; substrates of Nchannel
devices internally connected to VSS.

10

VSS

Figure 1. Typical Application: 2Input Analog Multiplexer

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2

MC14007UB

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Symbol

55
C

25
C

125
C

VDD
Vdc

Min

Max

Min

Typ (4.)

Max

Min

Max

Unit

Output Voltage
Vin = VDD or 0

0 Level

VOL

5.0
10
15

0.05
0.05
0.05

0
0
0

0.05
0.05
0.05

0.05
0.05
0.05

Vdc

Vin = 0 or VDD

1 Level

VOH

5.0
10
15

4.95
9.95
14.95

4.95
9.95
14.95

5.0
10
15

4.95
9.95
14.95

Vdc

0 Level

VIL

5.0
10
15

1.0
2.0
2.5

2.25
4.50
6.75

1.0
2.0
2.5

1.0
2.0
2.5

5.0
10
15

4.0
8.0
12.5

4.0
8.0
12.5

2.75
5.50
8.25

4.0
8.0
12.5

5.0
5.0
10
15

3.0
0.64
1.6
4.2

2.4
0.51
1.3
3.4

5.0
1.0
2.5
10

1.7
0.36
0.9
2.4

IOL

5.0
10
15

0.64
1.6
4.2

0.51
1.3
3.4

1.0
2.5
10

0.36
0.9
2.4

mAdc

Input Current

Iin

15

0.1

0.00001

0.1

1.0

Adc

Input Capacitance
(Vin = 0)

Cin

5.0

7.5

pF

Quiescent Current
(Per Package)

IDD

5.0
10
15

0.25
0.5
1.0

0.0005
0.0010
0.0015

0.25
0.5
1.0

7.5
15
30

Adc

IT

5.0
10
15

Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

Output Drive Current

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

1 Level

VIH

Vdc

IOH

Source

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Total Supply Current (5.) (6.)

(Dynamic plus Quiescent,
Per Gate) (CL = 50 pF)

Sink

Vdc

mAdc

IT = (0.7 A/kHz) f + IDD/6

IT = (1.4 A/kHz) f + IDD/6
IT = (2.2 A/kHz) f + IDD/6

4. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
5. The formulas given are for the typical characteristics only at 25
C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk

where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.003.

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3

Adc

MC14007UB

SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25
C)

Characteristic

Symbol

Output Rise Time

tTLH = (1.2 ns/pF) CL + 30 ns
tTLH = (0.5 ns/pF) CL + 20 ns
tTLH = (0.4 ns/pF) CL + 15 ns

tTLH

Output Fall Time

tTHL = (1.2 ns/pF) CL + 15 ns
tTHL = (0.5 ns/pF) CL + 15 ns
tTHL = (0.4 ns/pF) CL + 10 ns

tTHL

TurnOff Delay Time

tPLH = (1.5 ns/pF) CL + 35 ns
tPLH = (0.2 ns/pF) CL + 20 ns
tPLH = (0.15 ns/pF) CL + 17.5 ns

tPLH

TurnOn Delay Time

tPHL = (1.0 ns/pF) CL + 10 ns
tPHL = (0.3 ns/pF) CL + 15 ns
tPHL = (0.2 ns/pF) CL + 15 ns

tPHL

VDD
Vdc

Min

Typ (8.)

Max

5.0
10
15

90
45
35

180
90
70

5.0
10
15

75
40
30

150
80
60

5.0
10
15

60
30
25

125
75
55

5.0
10
15

60
30
25

125
75
55

Unit
ns

ns

ns

ns

7. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
8. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

VDD = -
VGS

VDD = VGS

14
IOH
7

14

VDS = VOH - VDD

IOL

VSS

All unused inputs connected to ground.

a TA = -
55C
b TA = +
25C
c TA = +
125C

-
8.0

b
a
c

-
12

b
b

-
10 Vdc

-
16

IOL , DRAIN CURRENT (mAdc)

IOH , DRAIN CURRENT (mAdc)

20

VGS = -
5.0 Vdc

-
15 Vdc

a
a

-
20
-
10

-
8.0

-
6.0
-
4.0
VDS, DRAIN VOLTAGE (Vdc)

VSS

All unused inputs connected to ground.

0
-
4.0

VDS = VOL

-
2.0

VGS = 15 Vdc

b
c

16

12

10 Vdc
b

c
a TA = -
55C
b TA = +
25C
c TA = +
125C

8.0
a

4.0

c
0

-
0

Figure 2. Typical Output Source Characteristics

2.0

b 5.0 Vdc

4.0
6.0
VDS, DRAIN VOLTAGE (Vdc)

8.0

Figure 3. Typical Output Sink Characteristics

These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.

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4

10

MC14007UB
VDD
500F
PULSE
GENERATOR

20 ns
0.01 F
CERAMIC

ID

VDD

90%
50%
10%

Vin

14

Vin

tPHL

VSS

CL

Vout

20 ns

90%
50%
10%

Vout

VSS

tPLH

VOH
VOL

tTHL

tTLH

Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms

APPLICATIONS
VDD
14

The MC14007UB dual pair plus inverter, which has

access to all its elements offers a number of unique circuit
applications. Figures 1, 5, and 6 are a few examples of the
device flexibility.

OUT = A+BC

13
11

+
VDD
2
DISABLE3
B

12

10

1
8

OUTPUT

11
9
12OUTPUT

INPUT10

5
C

3
4

9
8
A

DISABLE6

7
Substrates of Pchannel devices internally connected to VDD;
Substrates of Nchannel devices internally connected to VSS.
INPUT

DISABLE

OUTPUT

1
0
X

0
0
1

0
1
OPEN

Figure 6. AOI Functions Using Tree Logic

X = Dont Care

Figure 5. 3State Buffer

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5

MC14007UB
PACKAGE DIMENSIONS

P SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE M
14

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

A
F

DIM
A
B
C
D
F
G
H
J
K
L
M
N

T
SEATING
PLANE

K
H

D 14 PL

0.13 (0.005)

INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
--10

0.015
0.039

MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
--10

0.38
1.01

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

A
14

B
1

P 7 PL
0.25 (0.010)

R X 45

T
SEATING
PLANE

0.25 (0.010)

D 14 PL
M

T B

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6

DIM
A
B
C
D
F
G
J
K
M
P
R

MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0

7

5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0

7

0.228
0.244
0.010
0.019

MC14007UB
PACKAGE DIMENSIONS

DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G01
ISSUE O
14X K REF

0.10 (0.004)
0.15 (0.006) T U

T U

N
2X

14

L/2

0.25 (0.010)

M
B
U

L
PIN 1
IDENT.

F
7

0.15 (0.006) T U

DETAIL E
K

A
V

K1

J J1

SECTION NN
W

C
0.10 (0.004)
T SEATING
PLANE

DETAIL E

F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96501
ISSUE O

14

LE

Q1
E HE

M

DETAIL P

Z
D
VIEW P

A1

b
0.13 (0.005)

0.10 (0.004)

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7

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
4.90
5.10 0.193
0.200
B
4.30
4.50 0.169
0.177
C
--1.20
--0.047
D
0.05
0.15 0.002
0.006
F
0.50
0.75 0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.50
0.60 0.020
0.024
J
0.09
0.20 0.004
0.008
J1
0.09
0.16 0.004
0.006
K
0.19
0.30 0.007
0.012
K1
0.19
0.25 0.007
0.010
L
6.40 BSC
0.252 BSC
M
0

8

0

8

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z

MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10

0

0.70
0.90
--1.42

INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10

0

0.028
0.035
--0.056

MC14007UB

ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be
validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

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For additional information, please contact your local

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MC14007UB/D