EE271 @ Thuy T.

Le SJ SU - EE
1
1
EE 271
Advanced Digital System Design & Synthesis
Ripple Carry and Carry Lookahead
Addition and Subtraction Circuits
2
Functional Units for Addition and Subtraction
Full
Adder
a
i
b
i
c
i
s
i
c
i+1
a
i
b
i
c
i
s
i
c
i+1
carry status
0 0 0 0 0 Delete
0 0 1 1 0 Delete
0 1 0 1 0 Propagate
0 1 1 0 1 Propagate
1 0 0 1 0 Propagate
1 0 1 0 1 Propagate
1 1 0 0 1 Generate
1 1 1 1 1 Generate
EE271 @ Thuy T. Le SJ SU - EE
2
3
Serial Binary Adders
Full
Adder
a
i
b
i
c
i
Delay
s
i
c
i+1
Full
Adder
a
i
b
i
c
i
Q D
Q' CLK
s
i
c
i+1
0 1
00 0 1
01 1 0
11 0 1
10 1 0
c
i
a
i
b
i
s
i
0 1
00 0 0
01 0 1
11 1 1
10 0 1
c
i
a
i
b
i
c
i+1
4
Serial Adder with Accumulator
Full
Adder
a
i
b
i
c
i
Q D
Q' CLK
s
i
c
i+1
a
0
a
1
a
2
a
n-1
b
0
b
1
b
2
b
n-1
Control
Circuit
Start (s)
Clock
Accumulator
SH
Ex: n =4, input =S, output =SH
S
0
S
3
S
1
S
2
1/1
0/0
-/1
-/1
-/1
EE271 @ Thuy T. Le SJ SU - EE
3
5
Parallel Adder with Accumulator
Full
Adder
s
a
b
c
i
b
i
unused
Q' Q
CLK D
c
o
a
i
& s
i
c
i+1
A typical one-bit
adder cell
Full
Adder
a
i
b
i
c
i
c
i+
1
Q' Q
CLK D
s
i
Full
Adder
c
i+
2
Q' Q
CLK D
s
i+1
Full
Adder
a
n-1
b
n-1
c
n-1
c
n
Q' Q
CLK D
s
n-1
......
Add control signal
Accumulator register
Carry ripple through
6
Subtracter
Can be used for one's and
two's complement
The one's complement is
performed by inverting all bits
of one operand
The two's complement can be
performed by add 1 to the
one's complement
The add 1 to the one's
complement can be
accomplished by assigning 1
to the first carry input of the
first full-adder
4
MUX
A/S
4
4
4
a b
sum
+
f
o
r

2
'
c
o
m
p
l
e
m
e
n
t
EE271 @ Thuy T. Le SJ SU - EE
4
7
Express Sum and Carry as a Functions of G & P
Ignore sign-bit-carry for 2's complement system
End-around carry for 1's complement system (MSB carry is
added to the LSB of sum)
Both systems have the same overflow mechanism
( )
( )
( )
1
Generate: ; Delete:
Propagate: or sometime
Then:
,
i i i i i i
i i i i i
i i i i i i i i i i i i i i i i i
i i i
i i i i i i i i i i i i i i
i i i i i
g a b d a b
p a b a b
c g p a bc a bc a b a b a c bc
g p c
s p a bc a bc a bc a bc
a b c p c
+
- = =
- = +
-
= + + = + +
= +
= + + +
= =
8
Full-Adder Implementation
c
out
c
in
s
i
a
i
b
i
i i i
b a p = i i i
b a g - =
Basic implementation
b
i
a
i
c
out
s
i
c
in
i i i
b a p =
i i i
c p s =
more efficiently cell
(MUX is faster)
0
1
EE271 @ Thuy T. Le SJ SU - EE
5
9
Ripple-Carry Adder Design and Timing Analysis
Recursive design - Worst case delay linear with the number
of bits (for no sign or 2's complement system)
Goal: Make the fastest possible carry path circuit
( )
( )
_
1
d
add setup carry last sum
t O n
t t n t t
=
~ + +
Full
Adder
a
0
b
0
c
0
c
1
s
0
Full
Adder
c
i+
2
s
i+1
Full
Adder
a
n-1
b
n-1
c
n-1
c
n
s
n-1
......
Carry ripple through
End-around carry for 1's complement or
Ignore sign-bit carry for 2's complement
10
Gate-level schematic of a basic 4-bit adder
b
0
a
0
p
0
g
0
c
0
s
0
c
1
b
1
a
1
p
1
g
1
c
1
s
1
c
2
b
2
a
2
p
2
g
2
c
2
s
2
c
3
b
3
a
3
p
3
g
3
c
3
s
3
c
4
t
carr
y
t
setup
EE271 @ Thuy T. Le SJ SU - EE
6
11
module Add_PG ( sum, cout , a, b, ci n) ;
out put [ 3: 0] sum;
out put cout ;
i nput [ 3: 0] a, b;
i nput ci n;
r eg [ 4: 0] car r y;
i nt eger i ;
wi r e [ 3: 0] g = a & b;
wi r e [ 3: 0] p = a ^ b;
al ways@( a or b or ci n or p or g) begi n
car r y[ 0] = ci n;
f or ( i = 1; i <= 4; i = i + 1) begi n
car r y[ i ] = g[ i - 1] | ( p[ i - 1] &car r y[ i - 1] ) ;
end
end
wi r e [ 3: 0] sum= p ^ car r y;
wi r e cout = car r y[ 4] ;
endmodule
12
RCA implemented with multiplexer from the standard cell library
a
i+1
b
i+1 a
i
b
i
a
i+2
b
i+2
c
i+3
s
i
s
i+1
s
i+2
c
i
Critical Path
EE271 @ Thuy T. Le SJ SU - EE
7
13
4 stage adder
final sum and
carry
late
arriving
signal
Whenever c
in
is stable,
it takes two gate delays
to make c
out
stable
a
a
b
b
c
in
c
out
@0
@0
@0
@0
@n
@1
@1
@n+1
@n+2
a
0
b
0
c
0
s
0
@2
a
1
b
1
c
1
@2
s
1
@3
a
2
b
2
c
2
@4
s
2
@5
a
3
b
3
c
3
@6
s
3
@7
c
4
@8
0
1
2
3
For c
0
=0 initially
14
Critical delay: Propagation of carry from low to high order stages
1111 +0001
worst case
addition
2 delays to compute sum
but last carry-in is not
ready until 6 delays later
T
0
: Inputs to the adder are valid
T
2
: Stage 0 carry out (C
1
)
T
4
: Stage 1 carry out (C
2
)
T
6
: Stage 2 carry out (C
3
)
T
8
: Stage 3 carry out (C
4
)
EE271 @ Thuy T. Le SJ SU - EE
8
15
Adder/Subtractor
A - B = A + (-B) =A +B' +1
16
All 2n input bits available at the same time
Carries propagate from FA
0
to FA
n
before FA
n
produces
correct sum and carry-out bits
Ripple effect observed at sum outputs of adder until
carry propagation is complete
Reducing Propagation Delay:
Shorten carry propagation delay
Detect completion of carry propagation and so no
waiting for maximum fixed delay. But variable addition
time isinconvenient in a synchronous design and
So shorten carry propagation delay is the better approach
EE271 @ Thuy T. Le SJ SU - EE
9
17
Carry-Look-Ahead
Adder Design and Timing Analysis
(Weinberger and Smith, 1958)
ARITH-13: Presenting Achievement Award to
Arnold Weinberger of IBM (who invented CLA adder in 1958)
Basic Algorithm of Carry Look Ahead
18
t
prop
~ n
t
prop
~ log
2
(n)
a
0
a
1
a
2
a
3
a
4
a
5
a
6
a
7
a
1
a
2
a
3
a
4
a
5
a
6
a
7
a
0
EE271 @ Thuy T. Le SJ SU - EE
10
19
Generate all incoming carries in parallel
So carries depend on a
n-1
, a
n-2
, ..., a
0
and b
n-1
, b
n-2
, ..., b
0
a
i
b
i
c
i
s
i
c
i+1
carry status
0 0 0 0 0 Delete
0 0 1 1 0 Delete
0 1 0 1 0 Propagate
0 1 1 0 1 Propagate
1 0 0 1 0 Propagate
1 0 1 0 1 Propagate
1 1 0 0 1 Generate
1 1 1 1 1 Generate
c g a b
i i i i +
= =
1
c c p
c a b
i i i
i i i
+
=
=
1
b g
20
One-bit Adder
i i i
c p s =
i i i
b a p =
Can consider this as
i i i
g a b = -
bi
a
i
c
out
s
i
cin
c g c p
i i i i +
= +
1
0
1
EE271 @ Thuy T. Le SJ SU - EE
11
21
An example of 4-bit CLA Adder
c a b c a b c a b g p c
c g p c g p g p c
g p g p p c
c g p c
g p g p g p p c
g p g p p g
p p p c
i i i i i i i i i i i i
i i i i i i i i i
i i i i i i
i i i i
i i i i i i i i
i i i i i i
i i i i
+
+ + + + + +
+ + +
+ + + +
+ + + + +
+ + + + +
+ +
= + + = +
= + = + +
= + +
= +
= + + +
= + +
+
1
2 1 1 1 1 1
1 1 1
3 2 2 2
2 2 1 1 1
2 2 1 2 1
2 1
( )
( )

22
G
i+3,i
P
i+3,i
c g p c
g p g p g p p g
g p g p p g
p p p g
p p p p c
i i i i
i i i i i i i i
i i i i i i
i i i i
i i i i i
+ + + +
+ + + + + + +
+ + + + + +
+ + +
+ + +
= +
= + + + +
= + +
+
+
4 3 3 3
3 3 2 2 1 2 1
3 3 2 3 2 1
3 2 1
3 2 1
( )

c g g p g p p g p p p
p p p c
i i i i i i i i i i i
i
+
= + + +
+ +
1 1 2 1 3 2 1
0 1 0

b g
So all carries can be calculated in parallel from
a
n-1
, a
n-2
, ..., a
0
, b
n-1
, b
n-2
, ..., b
0
, and c
0
EE271 @ Thuy T. Le SJ SU - EE
12
23
One t
G
to calculate all p
i
and g
i
Two additional t
G
to calculate G and G +Pc
0
(2 levels)
One t
G
to calculate Pc
0
(parallel with calculating terms of G)
One t
G
to calculate the OR of G and Pc
0
So total is 3t
G
for calculating all c
i
One additional t
G
to calculate all s
i
=p
i
c
i
(all bits are
calculated in parallel)
So total is 4t
G
to complete, regarding number of bits
Compare that to 8t (for 4 bits) in RCA
c
0
P, G Generator
b
0
a
0
p
0
g
0
b
1
a
1
p
1
g
1
b
2
a
2
p
2
g
2
b
3
a
3
p
3
g
3
c
4
But n is related to fan-in and so Divide into k-bit groups
24
Carry Lookahead Logic
Cascaded Carry Lookahead
Carry lookahead logic generates
individual carries
Sums computed much faster
A
0
B
0
C
0
S
0
@2
A
1
B
1
C
1
@3
S
1
@4
A
2
B
2
C
2
@3
S
2
@4
A
3
B
3
C
3
@3
S
3
@4
C
4
@3
EE271 @ Thuy T. Le SJ SU - EE
13
25
Carry Lookahead Implementation
Adder with Propagate and
Generate Outputs
Increasingly complex logic
Pi @ 1 gate delay
Ci
Si @ 2 gate delays
Bi
Ai
Gi @ 1 gate delay
C0 C0
C0
C0
P0 P0
P0
P0
G0
G0
G0
G0
C1
P1
P1
P1
P1
P1
P1
G1
G1
G1
C2
P2
P2
P2
P2
P2
P2
G2
G2
C3
P3
P3
P3
P3
G3
C4
26
Logic Implementation of the Carry Block (two-level logic)
J ournal of VLSI Signal Processing, Vol.3, No.4, October 1991
c
4
c
3
c
2
c
1
c
0
EE271 @ Thuy T. Le SJ SU - EE
14
27
Logic Implementation of the Carry Block
(restricted fan-in three-level logic)
J ournal of VLSI Signal Processing, Vol.3, No.4, October 1991
c
4
c
3
c
2
c
0
c
1
28
Four Groups of 4-bit CLA Adder Connected by RC
Groups are interconnected by ripple-carry method
Equal-sized groups for simplicity
Size of group depends on technology (no. of input/output)
4-bit groups are common
Carry skip method is in fact CLA with groups
Carry Skip: Uses ripple-carry method to calculate carry bits within a
groupand PG method to calculate group carry bits
Group CLA: Uses PG method to calculate carry bits within a group
and ripple carry method to calculate group carry bits
EE271 @ Thuy T. Le SJ SU - EE
15
29
One t
G
is needed to generate all p
i
and g
i
Two additional t
G
for all carry bits in each group, one at a
time, once the carry in into the group is available
First group forms G+Pc
0
in parallel with other groups form G and
P (OR-AND of gs and AND of ps) since other groups have not
had c
i
's yet. Forming P and G alone reduces fan-in.
So (n/4)(2t
G
) = (n/2)t
G
is needed to propagate carry through all
groups (G+Pc
i
operations in each group)
An additional t
G
is needed to generate sum bits of the last
group (Once all carry bits in a group are available, t
G
is
need for sum bits generation (all sum bits in a group are
generated in parallel)
Total of t
G
+(n/2)t
G
+t
G
=((n/2) +2)t
G
is needed.
Compare to 2nt
G
in a ripple-carry adder
Four Groups of 4-bit CLA Adder Connected by CLA
30
G =1if a carry-out (of group) is generated internally
P =1if a carry-in (to group) is propagated internally
to produce a carry-out (of group)
P,G Generator P,G Generator
P,G Generator
P
3,0
G
3,0
P
15,0
G
15,0
c
out
P
7,4
G
7,4
EE271 @ Thuy T. Le SJ SU - EE
16
31
Logic Implementation of the Multilevel
Carry-Lookahead Generator (two-level logic)
J ournal of VLSI Signal Processing, Vol.3, No.4, October 1991
c
3
c
2
c
1
c
0
32
Logic Implementation of the Multilevel Carry Lookahead
Generator (restricted fan-in - three-level logic)
J ournal of VLSI Signal Processing, Vol.3, No.4, October 1991
c
3
c
2
c
0
c
1
EE271 @ Thuy T. Le SJ SU - EE
17
33
One t
G
is needed to generate all p
i
and g
i
Two additional t
G
is needed to calculate group P and G
Parallel with calculating carries in 1st group because c
0
is available
All groups calculate group P and G in parallel.
Two additional t
G
is needed to produce c
4
, c
8
, and c
12
(in
lower CLA)
Two additional t
G
is for the calculation of all carry bits (by g
+p-c) in all groups (in upper CLA)
One additional t
G
is for the calculation of all sum bits
Total of t
G
+2t
G
+2t
G
+2t
G
+t
G
=8t
G
is needed.
Not depend on number of groups Theory, may be different in practice
c G P c
c G P G P P c
c G P G P P G P P P c
4 30 30 0
8 7 4 7 4 30 7 4 30 0
12 118 118 7 4 118 7 4 30 118 7 4 30 0
= +
= + +
= + + +
, ,
, , , , ,
, , , , , , , , ,
Higher than 16-bit CLA Higher-Level CLA
4 bits per group, 4 groups (16 bits) per section, 4 sections for
a 64-bit adder
Sections are connected by RC method or use another level of
carry-look-ahead for faster execution
The 3rd-level of CLA generator receives 2 pairs of G and P
from the two 2-level generators and produces carries c
16
and
c
out
(c
64
)
As n increases, more levels of carry-look-ahead generators
can be added
Number of levels for maximum speed-up proportional to
log
b
(n) where b is the blocking factor (number of bits in a
group, number of groups in a section, etc.)
Overall addition time is proportional to log
b
(n)
34
EE271 @ Thuy T. Le SJ SU - EE
18
35
Theoretical Speeds and Costs of Adders
We so far doing the timing analysis for addition circuits
based on only one type of gate delay, which is not true
The two main factors are gate fan-in (f) and radix (r). So
we represent a gate by (f,r)
We assume that gates are capable of computing with any
radix in the same time delay, which is again not true
A circuit for adding two radix-r operands with n digits
each must have 2n inputs and n+1 outputs
Number of inputs can be reduced by using many gates
operating in parallel
Number of intermediate arguments can be further reduced
by having additional level of gates
We mostly only consider fan-in limitation and ignore fan-
out. In practice fan-out is also constrained
36
The general lower bound in addition time is
(and so for binary system)
The above bound assumes at least one output digit that
depends on all 2n input digits. If not, a better (lower)
value for the bound exists. This occurs if carry does not
propagate from least-significant to most-significant
position
Example: s
i
only depends on a
i
, b
i
, a
i-1
, b
i-1
:
In the carry-look-ahead and carry-select algorithms,
execution time theoretically proportional to log
2
(n),
which is the binary bound approached
We should also consider the implementation cost in
addition to execution time
T n
add f
> log 2 b g
T
add f
> log 4 b g
EE271 @ Thuy T. Le SJ SU - EE
19
37
Implementation cost depends on technology
Discrete gates
Number of gates measures implementation cost
Number of gates along the critical (longest) path (number of circuit
levels) determines execution time
Full custom VLSI technology
The effect of number of gates on implementation cost is actually
limited
Regularity of design and length of interconnections are more important
in both silicon area and design time
Additional constraints such as number of pins exist. Highest
blocking factor is not necessarily the best
If performance is more important then carry-look-ahead adder
preferable
If lower implementation cost is required then ripple-carry
method with speed-up techniques is the best