Test 1 CS 270 Spring 2007

Student Name:_____________________________

This test is closed book, closed notes and calculators are not allowed. If more space
is needed put answers on the backs of the adjacent pages.

1. Consider the R-format instruction add, the lw and sw instructions, and the beq
instruction using the figure given. Which of these instructions will not work
correctly for the given stuck-at-1 faults.

Consider the following faults separately:

a. RegDst = 1

b. MemtoReg = 1

c. AluSrc =1
Consider the following table that has been modified from our text and notes. It no
longer makes sense as far as a control table but that is not our concern.

ALUOp Funct field Operation

ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0
1 0 X X X X X X 0010
0 1 X X X X X X 0110
0 X X X 0 0 0 0 1110
1 X X X 0 0 1 0 0101
0 X X X 0 1 0 0 1000
1 X X X 0 1 0 1 0101
0 X X X 1 0 1 0 1111

2. Use a PLA to implement the table above for the eight inputs and four outputs.
 3. Some changes have been made to the figure below. Use this figure and your
knowledge about the single cycle datapath control unit to fill in the values in the table
below. The R-format instruction row in the table is for arithmetic and logic instructions
only. Show don’t cares with an x if any exist.

0
M
u
x
Add ALU 1
result
Add Shift
RegDst left 2
4 Branch
MemRead
Instruction [31– 26] MemtoReg
Control ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25– 21] Read

Read register 1
PC address Read
Instruction [20– 16] Read data 1
register 2 Zero
Instruction 1 Registers Read
[31– 0] ALU ALU
Write 1 Read
M data 2 result Address 0
Instruction u register M data
u M
memory x u
Instruction [15– 11] Write x
0 Data x
data 0 memory 1
Write
data
16 32
Instruction [15– 0] Sign
extend ALU
control

Instruction [5– 0]

Memto- Reg Mem Mem

Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0
R-format
lw
sw
beq
Notice that the states are not numbered as they were in the text. Consider the following
FSM.

Instruction decode/
Instruction fetch register fetch
0
MemRead 1
ALUSrcA = 0
IorD = 0 ALUSrcA = 0
Start IRWrite ALUSrcB = 11
ALUSrcB = 01 ALUOp = 00
ALUOp = 00
PCWrite
PCSource = 00
e)

')
-typ

EQ

(Op = 'J')
R
p=

'B
') (O

=
Memory address 'SW

p
p= Branch Jump

(O
computation ( O
W ') or Execution completion completion
= 'L
6 (Op 4 3 2
ALUSrcA = 1
ALUSrcA = 1 ALUSrcA =1 ALUSrcB = 00
ALUSrcB = 10 PCWrite
ALUSrcB = 00 ALUOp = 01
ALUOp = 00 PCSource = 10
ALUOp = 10 PCWriteCond
PCSource = 01
(O
(Op = 'LW')

p
=
'S
W
')

Memory Memory
access access R-type completion
8 7 5

RegDst = 1
MemRead MemWrite RegWrite
IorD = 1 IorD = 1 MemtoReg = 0

Write-back step
9

RegDst = 0
RegWrite
MemtoReg =1
4. Using the FSM and the multicycle data path in figure 5.28 provided seperately. Build
a PLA for the control signals only. We assume that a subcontractor will provide the PLA
for the next state information.
 5. We wish to add the instruction sll (shift left logical) to the single-cycle datapath
below. Add any necessary hardware and control signals to the figure below. Also
show any necessary changes and additions to the table below. Explain your answer
fully. Note that the R-format in the first row of the original table is for add, sub,
and, or functions only, it does not cover the sll which will need a new row for sure.

Memto- Reg Mem Mem

Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0
R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 1 0 1