LTC2655

1
2655f
BLOCK DIAGRAM
FEATURES DESCRIPTION
Quad I
2
C 16-/12-Bit
Rail-to-Rail DACs with
10ppm/C Max Reference
The LTC

2655 is a family of Quad I

2
C 16-/12-Bit Rail-to-
Rail DACs with integrated 10ppm/C max reference. The
DACs have built-in high performance, rail-to-rail, output
buffers and are guaranteed monotonic. The LTC2655-L
has a full-scale output of 2.5V with the integrated refer-
ence and operates from a single 2.7V to 5.5V supply.
The LTC2655-H has a full-scale output of 4.096V with
the integrated reference and operates from a 4.5V to
5.5V supply. Each DAC can also operate with an external
reference, which sets the full-scale output to 2 times the
external reference voltage.
The parts use the 2-wire I
2
C compatible serial interface.
The LTC2655 operates in both the standard mode (maxi-
mum clock rate of 100kHz) and the fast mode (maximum
clock rate of 400kHz). The LTC2655 incorporates a
power-on reset circuit that is controlled by the PORSEL
pin. If PORSEL is tied to GND the DACs power-on reset to
zero-scale. If PORSEL is tied to V
CC
, the DACs power-on
reset to mid-scale.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5396245, 6891433 and 7671770.
INL Curve
APPLICATIONS
n
Integrated Reference 10ppm/C Max
n
Maximum INL Error: 4LSB at 16 Bits
n
Guaranteed Monotonic Over Temperature
n
Selectable Internal or External Reference
n
2.7V to 5.5V Supply Range (LTC2655-L)
n
Integrated Reference Buffers
n
Ultralow Crosstalk Between DACs (<1nVs)
n
Power-On-Reset to Zero-Scale/Mid-Scale
n
Asynchronous DAC Update Pin
n
Tiny 20-Lead 4mm 4mm QFN and
16-Lead Narrow SSOP packages
n
Mobile Communications
n
Process Control and Industrial Automation
n
Instrumentation
n
Automatic Test Equipment
n
Automotive
2655 BD
GND
V
OUTA
V
OUTB
SCL
CA2
LDAC
REFLO
CA1
CA0
REFIN/OUT
REFCOMP
V
CC
V
OUTD
V
OUTC
PORSEL
SDA
INTERNAL REFERENCE
DAC A
POWER-ON
RESET
DAC B
DAC D
DAC C
R
E
G
I
S
T
E
R
32-BIT SHIFT REGISTER
2-WIRE INTERFACE
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
CODE
128
I
N
L

(
L
S
B
)
4
2
1
3
2
3
1
0
4
32768 49152 16384
2655 TA01b
65535
V
CC
= 5V
LTC2655
2
2655f
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V
CC
) ................................... 0.3V to 6V
SCL, SDA, LDAC, REFLO .............................. 0.3V to 6V
V
OUTA
to V
OUTD
................ 0.3V to Min (V
CC
+ 0.3V, 6V)
REFIN/OUT, REFCOMP .....0.3V to Min (V
CC
+ 0.3V, 6V)
PORSEL, CA0, CA1, CA2 ..0.3V to Min (V
CC
+ 0.3V, 6V)
(Notes 1, 2)
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
REFLO
V
OUTA
REFCOMP
V
OUTB
REFIN/OUT
LDAC
CA2
SCL
GND
V
CC
V
OUTD
V
OUTC
PORSEL
CA0
CA1
SDA
T
JMAX
= 150C,
JA
= 110C/W
20 19 18 17 16
6 7 8
TOP VIEW
21
GND
UF PACKAGE
20-LEAD (4mm 4mm) PLASTIC QFN
9 10
5
4
3
2
1
11
12
13
14
15 V
OUTA
REFCOMP
V
OUTB
REFIN/OUT
LDAC
DNC
V
OUTD
V
OUTC
PORSEL
CA0
R
E
F
L
O
G
N
D
V
C
C
D
N
C
D
N
C
C
A
2
S
C
L
D
N
C
S
D
A
C
A
1
T
JMAX
= 150C,
JA
= 37C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
Operating Temperature Range
LTC2655C ................................................ 0C to 70C
LTC2655I ............................................. 40C to 85C
Maximum Junction Temperature .......................... 150C
Storage Temperature Range ...................... 65 to 150C
Lead Temperature, GN Only (Soldering, 10 sec).... 300C
LTC2655
3
2655f
ORDER INFORMATION
LTC2655 B C UF L 16 #TR PBF
LEAD FREE DESIGNATOR
TAPE AND REEL
TR = Tape and Reel
RESOLUTION
16 = 16-Bit
12 = 12-Bit
FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
UF = 20-Lead (4mm 4mm) Plastic QFN
GN = 16-Lead Narrow SSOP
TEMPERATURE GRADE
C = Commercial Temperature Range (0C to 70C)
I = Industrial Temperature Range (40C to 85C)
ELECTRICAL GRADE (OPTIONAL)
B = 4LSB Maximum INL (16-Bit)
PRODUCT PART NUMBER
Consult LTC Marketing for information on non-standard lead based nish parts. Consult LTC Marketing for parts specied with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specications, go to: http://www.linear.com/tapeandreel/
LTC2655
4
2655f
PRODUCT SELECTION GUIDE
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION
TEMPERATURE
RANGE
MAXIMUM
INL
LTC2655BCGN-L16#PBF LTC2655BCGN-L16#TRPBF 655L16 16-Lead Narrow SSOP 0C to 70C 4
LTC2655BIGN-L16#PBF LTC2655BIGN-L16#TRPBF 655L16 16-Lead Narrow SSOP 40C to 85C 4
LTC2655BCUF-L16#PBF LTC2655BCUF-L16#TRPBF 55L16 20-Lead (4mm 4mm) Plastic QFN 0C to 70C 4
LTC2655BIUF-L16#PBF LTC2655BIUF-L16#TRPBF 55L16 20-Lead (4mm 4mm) Plastic QFN 40C to 85C 4
LTC2655BCGN-H16#PBF LTC2655BCGN-H16#TRPBF 655H16 16-Lead Narrow SSOP 0C to 70C 4
LTC2655BIGN-H16#PBF LTC2655BIGN-H16#TRPBF 655H16 16-Lead Narrow SSOP 40C to 85C 4
LTC2655BCUF-H16#PBF LTC2655BCUF-H16#TRPBF 55H16 20-Lead (4mm 4mm) Plastic QFN 0C to 70C 4
LTC2655BIUF-H16#PBF LTC2655BIUF-H16#TRPBF 55H16 20-Lead (4mm 4mm) Plastic QFN 40C to 85C 4
LTC2655CGN-L12#PBF LTC2655CGN-L12#TRPBF 655L12 16-Lead Narrow SSOP 0C to 70C 1
LTC2655IGN-L12#PBF LTC2655IGN-L12#TRPBF 655L12 16-Lead Narrow SSOP 40C to 85C 1
LTC2655CUF-L12#PBF LTC2655CUF-L12#TRPBF 55L12 20-Lead (4mm 4mm) Plastic QFN 0C to 70C 1
LTC2655IUF-L12#PBF LTC2655IUF-L12#TRPBF 55L12 20-Lead (4mm 4mm) Plastic QFN 40C to 85C 1
LTC2655CGN-H12#PBF LTC2655CGN-H12#TRPBF 655H12 16-Lead Narrow SSOP 0C to 70C 1
LTC2655IGN-H12#PBF LTC2655IGN-H12#TRPBF 655H12 16-Lead Narrow SSOP 40C to 85C 1
LTC2655CUF-H12#PBF LTC2655CUF-H12#TRPBF 55H12 20-Lead (4mm 4mm) Plastic QFN 0C to 70C 1
LTC2655IUF-H12#PBF LTC2655IUF-H12#TRPBF 55H12 20-Lead (4mm 4mm) Plastic QFN 40C to 85C 1
Consult LTC Marketing for parts specied with wider operating temperature ranges. *The temperature grade is identied by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specications, go to: http://www.linear.com/tapeandreel/
LTC2655
5
2655f
ELECTRICAL CHARACTERISTICS The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at T
A
= 25C. V
CC
= 2.7V to 5.5V, V
OUT
unloaded unless otherwise specied.
LTC2655B-L16/ LTC2655-L12 (Internal Reference=1.25V)
SYMBOL PARAMETER CONDITIONS
LTC2655-12 LTC2655B-16
UNITS MIN TYP MAX MIN TYP MAX
DC Performance
Resolution l 12 16 Bits
Monotonicity (Note 3) l 12 16 Bits
DNL Differential Nonlinearity (Note 3) l 0.1 0.5 0.3 1 LSB
INL Integral Nonlinearity (Note 3) V
CC
= 5.5V, V
REF
= 2.5V l 0.5 1 2 4 LSB
Load Regulation V
CC
= 5V 10%, Internal Reference,
Mid-Scale, 15mA I
OUT
15mA
l 0.04 0.125 0.6 2 LSB/mA
V
CC
= 3V 10%, Internal Reference,
Mid-Scale, 7.5mA I
OUT
5mA
l 0.06 0.25 1 4 LSB/mA
ZSE Zero-Scale Error l 1 3 1 3 mV
V
OS
Offset Error V
REF
= 1.25V (Note 4) l 1 2 1 2 mV
V
OS
Temperature Coefcient 5 5 V/C
GE Gain Error l 0.02 0.1 0.02 0.1 %FSR
Gain Temperature Coefcient 1 1 ppm/C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OUT
DAC Output Span Internal Reference
External Reference = V
EXTREF
0 to 2.5
0 to 2V
EXTREF
V
V
PSR Power Supply Rejection V
CC
10% 80 dB
R
OUT
DC Output Impedance V
CC
= 5V 10%, Internal Reference, Mid-Scale,
15mA I
OUT
15mA
V
CC
= 3V 10%, Internal Reference, Mid-Scale,
7.5mA I
OUT
7.5mA
l
l
0.04
0.04
0.15
0.15

DC Crosstalk (Note 5) Due to Full-Scale Output Change

Due to Load Current Change
Due to Powering Down (per Channel)
1.5
2
1
V
V/mA
V
I
SC
Short-Circuit Output Current (Note 6) V
CC
= 5.5V V
EXTREF
= 2.8V
Code: Zero-Scale; Forcing Output to V
CC

Code: Full-Scale; Forcing Output to GND
l
l
20
20
65
65
mA
mA
V
CC
= 2.7V V
EXTREF
= 1.4V
Code: Zero-Scale; Forcing Output to V
CC

Code: Full-Scale; Forcing Output to GND
l
l
10
10
45
45
mA
mA
LTC2655
6
2655f
ELECTRICAL CHARACTERISTICS The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at T
A
= 25C. V
CC
= 2.7V to 5.5V, V
OUT
unloaded unless otherwise specied.
LTC2655B-L16/LTC2655-L12 (Internal Reference = 1.25V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference
Reference Output Voltage 1.248 1.25 1.252 V
Reference Temperature Coefcient (Note 7) 2 10 ppm/C
Reference Line Regulation V
CC
10% 80 dB
Reference Short-Circuit Current V
CC
= 5.5V, Forcing REFIN/OUT to GND l 3 5 mA
REFCOMP Pin Short-Circuit Current V
CC
= 5.5V, Forcing REFCOMP to GND l 65 200 A
Reference Load Regulation V
CC
= 3V10% or 5V10%, I
OUT
= 100A Sourcing 40 mV/mA
Reference Output Voltage Noise Density C
REFCOMP
= C
REFIN/OUT
= 0.1F, at f = 1kHz 30 nV/Hz
Reference Input Range External Reference Mode (Note 14) l 0.5 V
CC
/2 V
Reference Input Current l 0.001 1 A
Reference Input Capacitance (Note 9) 20 pF
Power Supply
V
CC
Positive Supply Voltage For Specied Performance l 2.7 5.5 V
I
CC
Supply Current (Note 8) V
CC
= 5V, Internal Reference On
V
CC
= 5V, Internal Reference Off
V
CC
= 3V, Internal Reference On
V
CC
= 3V, Internal Reference Off
l
l
l
l
1.7
1.3
1.6
1.2
2.5
2
2.2
1.7
mA
mA
mA
mA
I
SD
Supply Current in Shutdown Mode (Note 8) V
CC
= 5V l 3 A
Digital I/O
V
IL
Low Level Input Voltage (SDA and SCL) l 0.3V
CC
V
V
IH
High Level Input Voltage (SDA and SCL) l 0.7V
CC
V
V
IL(LDAC)
Low Level Input Voltage (LDAC) V
CC
= 4.5V to 5.5V l 0.8 V
V
CC
= 2.7V to 4.5V l 0.6 V
V
IH(LDAC)
High Level Input Voltage (LDAC) V
CC
= 3.6V to 5.5V l 2.4 V
V
CC
= 2.7V to 3.6V l 2 V
V
IL(CA)
Low Level Input Voltage (CA0 to CA2) See Test Circuit 1 l 0.15V
CC
V
V
IH(CA)
High Level Input Voltage (CA0 to CA2) See Test Circuit 1 l 0.85V
CC
V
R
INH
Resistance from CAn (n = 0,1,2)
to V
CC
to Set CAn = V
CC
See Test Circuit 2 l 10 k
R
INL
Resistance from CAn (n = 0,1,2)
to GND to Set CAn = GND
See Test Circuit 2 l 10 k
R
INF
Resistance from CAn (n = 0,1,2)
to V
CC
or GND to Set Can = FLOAT
See Test Circuit 2 l 2 M
V
OL
Low Level Output Voltage Sink Current =3mA l 0 0.4 V
t
OF
Output Fall Time V
O
= V
IH(MIN)
to V
O
= V
IL(MAX)
,
C
B
= 10pF to 400pF (Note 13)
20+0.1C
B
250 ns
t
SP
Pulse Width of Spikes Suppressed by Input
Filter
l 0 50 ns
I
IN
Input Leakage 0.1V
CC
V
IN
0.9V
CC
l 1 A
C
IN
I/O Pin Capacitance (Note 9) l 10 pF
C
B
Capacitance Load for Each Bus Line l 400 pF
C
CAn
External Capacitive Load on Address Pins
CA0, CA1 and CA2
l 10 pF
LTC2655
7
2655f
ELECTRICAL CHARACTERISTICS The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at T
A
= 25C. V
CC
= 4.5V to 5.5V, V
OUT
unloaded unless otherwise specied.
LTC2655B-H16/LTC2655-H12 (Internal Reference = 2.048V)
SYMBOL PARAMETER CONDITIONS
LTC2655-12 LTC2655B-16
UNITS MIN TYP MAX MIN TYP MAX
DC Performance
Resolution l 12 16 Bits
Monotonicity (Note 3) l 12 16 Bits
DNL Differential Nonlinearity (Note 3) l 0.1 0.5 0.3 1 LSB
INL Integral Nonlinearity (Note 3) V
CC
= 5.5V, V
REF
= 2.5V l 0.5 1 2 4 LSB
Load Regulation V
CC
= 5V 10%, Internal Reference,
Mid-Scale, 15mA I
OUT
15mA
l 0.04 0.125 0.6 2 LSB/mA
ZSE Zero-Scale Error l 1 3 1 3 mV
V
OS
Offset Error V
REF
= 2.048V (Note 4) l 1 2 1 2 mV
V
OS
Temperature Coefcient 5 5 V/C
GE Gain Error l 0.02 0.1 0.02 0.1 %FSR
Gain Temperature Coefcient 1 1 ppm/C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OUT
DAC Output Span Internal Reference
External Reference = V
EXTREF
0 to 4.096
0 to 2V
EXTREF
V
V
PSR Power Supply Rejection V
CC
10% 80 dB
R
OUT
DC Output Impedance V
CC
= 5V 10%, Internal Reference, Mid-Scale,
15mA I
OUT
15mA
l 0.04 0.15
DC Crosstalk Due to Full Scale Output Change
Due to Load Current Change
Due to Powering Down (per Channel)
1.5
2
1
V
V/mA
V
I
SC
Short-Circuit Output Current (Note 4) V
CC
= 5.5V V
EXTREF
= 2.8V
Code: Zero-Scale; Forcing Output to V
CC

Code: Full-Scale; Forcing Output to GND
l
l
20
20
65
65
mA
mA
LTC2655
8
2655f
ELECTRICAL CHARACTERISTICS The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at T
A
= 25C. V
CC
= 4.5V to 5.5V, V
OUT
unloaded unless otherwise specied.
LTC2655B-H16/LTC2655-H12 (Internal Reference = 2.048V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference
Reference Output Voltage 2.044 2.048 2.052 V
Reference Temperature Coefcient (Note 7) 2 10 ppm/C
Reference Line Regulation V
CC
10% 80 dB
Reference Short-Circuit Current V
CC
= 5.5V, Forcing REFIN/OUT to GND l 3 5 mA
REFCOMP Pin Short-Circuit Current V
CC
= 5.5V, Forcing REFCOMP to GND l 65 200 A
Reference Load Regulation V
CC
= 5V10%, I
OUT
= 100A Sourcing 40 mV/mA
Reference Output Voltage Noise Density C
REFCOMP
= C
REFIN/OUT
= 0.1F, at f = 1kHz 35 nV/Hz
Reference Input Range External Reference Mode (Note 14) l 0.5 V
CC
/2 V
Reference Input Current l 0.001 1 A
Reference Input Capacitance (Note 9) l 20 pF
Power Supply
V
CC
Positive Supply Voltage For Specied Performance l 4.5 5.5 V
I
CC
Supply Current (Note 8) V
CC
= 5V, Internal Reference On
V
CC
= 5V, Internal Reference Off
l
l
1.9
1.5
2.5
2
mA
mA
I
SD
Supply Current in Shutdown Mode (Note 8) V
CC
= 5V l 3 A
Digital I/O
V
IL
Low Level Input Voltage (SDA and SCL) l 0.3V
CC
V
V
IH
High Level Input Voltage (SDA and SCL) l 0.7V
CC
V
V
IL(LDAC)
Low Level Input Voltage (LDAC) V
CC
= 4.5V to 5.5V l 0.8 V
V
IH(LDAC)
High Level Input Voltage (LDAC) V
CC
= 4.5V to 5.5V l 2.4 V
V
IL(CA)
Low Level Input Voltage (CA0 to CA2) See Test Circuit 1 l 0.15V
CC
V
V
IH(CA)
High Level Input Voltage (CA0 to CA2) See Test Circuit 1 l 0.85V
CC
V
R
INH
Resistance from CAn (n = 0,1,2)
to V
CC
to Set CAn = V
CC
See Test Circuit 2 l 10 k
R
INL
Resistance from CAn (n = 0,1,2)
to GND to Set CAn = GND
See Test Circuit 2 l 10 k
R
INF
Resistance from CAn (n = 0,1,2)
to V
CC
or GND to Set CAn = FLOAT
See Test Circuit 2 l 2 M
V
OL
Low Level Output Voltage Sink Current = 3mA l 0 0.4 V
t
OF
Output Fall Time V
O
= V
IH(MIN)
to V
O
= V
IL(MAX)
,
C
B
= 10pF to 400pF (Note 13)
l 20+0.1C
B
250 ns
t
SP
Pulse Width of Spikes Suppressed by Input
Filter
l 0 50 ns
I
IN
Input Leakage 0.1V
CC
V
IN
0.9V
CC
l 1 A
C
IN
I/O Pin Capacitance (Note 9) l 10 pF
C
B
Capacitance Load for Each Bus Line l 400 pF
C
CAn
External Capacitive Load on Address Pins
CA0, CA1 and CA2
l 10 pF
LTC2655
9
2655f
ELECTRICAL CHARACTERISTICS
LTC2655B-L16/LTC2655-L12/LTC2655B-H16/LTC2655-H12
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AC Performance
t
s
Settling Time ( Note 10) 0.024%(1LSB at 12 Bits)
0.0015%(1LSB at 16 Bits)
3.9
9.1
s
s
Settling Time for 1LSB Step 0.024%(1LSB at 12 Bits)
0.0015%(1LSB at 16 Bits)
2.4
4.5
s
s
Voltage Output Slew Rate 1.8 V/s
Capacitive Load Driving 1000 pF
Glitch Impulse (Note 11) At Mid-Scale Transition, -L Option 4 nVs
At Mid-Scale Transition, -H Option 7 nVs
DAC to DAC Crosstalk (Note 12) C
REFCOMP
= C
REFIN/OUT
= 0.22F 0.5 nVs
Multiplying Bandwidth 150 kHz
e
n
Output Voltage Noise Density At f = 1kHz
At f = 10kHz
85
80
nV/Hz
nV/Hz
Output Voltage Noise 0.1Hz to 10Hz, Internal Reference (-L Options)
0.1Hz to 10Hz, Internal Reference (-H Options)
0.1Hz to 200KHz, Internal Reference (-L Options)
0.1Hz to 200KHz, Internal Reference (-H Options)
8
12
400
450
V
P-P
V
P-P
V
P-P
V
P-P
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at T
A
= 25C. V
CC
= 2.7V to 5.5V (LTC2655B-L16/LTC2655-L12), V
CC
= 4.5V to 5.5V (LTC2655B-H16,
LTC2655-H12), V
OUT
unloaded unless otherwise specied.
LTC2655B-L16/LTC2655-L12/LTC2655B-H16/LTC2655-H12 (see Figure 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SCL
SCL Clock Frequency l 0 400 kHz
t
HD(STA)
Hold Time (Repeated) Start Condition l 0.6 s
t
LOW
Low Period of the SCL Clock Pin l 1.3 s
t
HIGH
High Period of the SCL Clock Pin l 0.6 s
t
SU(STA)
Set-Up Time for a Repeated Start Program l 0.6 s
t
HD(DAT)
Data Hold Time l 0 0.9 s
t
SU(DAT)
Data Set-Up Time l 100 ns
tr Rise Time of Both SDA and SCL Signals (Note 13) l 20+0.1C
B
300 ns
tf Fall Time of Both SDA and SCL Signals (Note 13) l 20+0.1C
B
300 ns
t
SU(STO)
Set-Up Time for Stop Condition l 0.6 s
t
BUF
Bus Free Time Between a Stop and Start Condition l 1.3 s
t1 Falling edge of the 9th Clock of the 3rd Input Byte
to LDAC High or Low Transition
l 400 ns
t2 LDAC Low Pulse Width l 20 ns
The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at T
A
= 25C. V
CC
= 2.7V to 5.5V (LTC2655B-L16/LTC2655-L12), V
CC
= 4.5V to 5.5V
(LTC2655B-H16, LTC2655-H12), V
OUT
unloaded unless otherwise specied.
LTC2655
10
2655f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND.
Note 3: Linearity and monotonicity are dened from code k
L
to code 2
N
1,
where N is the resolution and k
L
is the lower end code for which no output
limiting occurs. For V
REF
= 2.5V and N = 16, k
L
= 128 and linearity is
dened from code 128 to code 65535. For V
REF
= 2.5V and N = 12, k
L
=8
and linearity is dened from code 8 to code 4095.
Note 4: Inferred from measurement at code 128 (LTC2655-16), or code 8
(LTC2655-12).
Note 5: DC Crosstalk is measured with V
CC
= 5V and using internal
reference, with the measured DAC at mid-scale.
Note 6: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specied maximum operating junction temperature may impair
device reliability.
Note 7: Temperature coefcient is calculated by dividing the maximum
change in output voltage by the specied temperature range. Maximum
temperature coefcient is guaranteed for C-grade only.
Note 8: Digital inputs at 0V or V
CC
.
Note 9: Guaranteed by design and not production tested.
Note 10: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 11: V
CC
= 5V (-H Options) or V
CC
= 3V (-L Options), internal
reference mode. DAC is stepped 1 LSB between half-scale and
half-scale 1. Load is 2k n parallel with 200pF to GND.
Note 12: DAC to DAC Crosstalk is the glitch that appears at the output
of one DAC due to a full scale change at the output of another DAC. It is
measured with V
CC
= 5V and using internal reference, with the measured
DAC at mid-scale.
Note 13: C
B
= Capacitance of one bus line in pF.
Note 14: Gain error specication may be degraded for reference input
voltages less than 1V. See Gain Error vs Reference Input Curve in the
Typical Performance Characteristics section.
ELECTRICAL CHARACTERISTICS
LTC2655
11
2655f
DNL vs Temperature
REFIN/OUT Output Voltage
vs Temperature
Settling to 1LSB Rising Settling to 1LSB Falling
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
INL vs Temperature
CODE
128
I
N
L

(
L
S
B
)
4
3
2
3
1
2
1
0
4
32768 49152 16384
2655 G01
65535
V
CC
= 3V
CODE
128
D
N
L

(
L
S
B
)
1.0
0.5
0.5
0
1.0
32768 49152 16384
2655 G02
65535
V
CC
= 3V
TEMPERATURE (C)
50
I
N
L

(
L
S
B
)
4
2
2
3
1
1
3
0
4
50 30 10 110 90 70 10 30
2655 G03
130
V
CC
= 3V
INL(POS)
INL(NEG)
TEMPERATURE (C)
50
D
N
L

(
L
S
B
)
1.0
0.5
0.5
0
1.0
50 30 10 110 90 70 30 10
2655 G04
130
V
CC
= 3V
DNL(POS)
DNL(NEG)
TEMPERATURE (C)
50
V
R
E
F

(
V
)
1.253
1.248
1.249
1.252
1.251
1.250
1.247
50 30 10 110 90 70 30 10
2655 G05
130
V
CC
= 3V
2s/DIV
V
OUT
250V/DIV
SCL
3V/DIV
2655 G06
9TH CLOCK OF
3RD DATA BYTE
7.8s
1/4 SCALE TO
3/4 SCALE STEP
V
CC
= 3V, V
FS
= 2.50V
2s/DIV
V
OUT
200V/DIV
SCL
3V/DIV
2655 G07
9TH CLOCK OF
3RD DATA BYTE
7.3s
3/4 SCALE TO
1/4 SCALE STEP
V
CC
= 3V, V
FS
= 2.50V
R
L
= 2k, C
L
= 200pF
AVERAGE OF 2048 EVENTS
TYPICAL PERFORMANCE CHARACTERISTICS T
A
= 25C unless otherwise noted.
LTC2655-L16
LTC2655
12
2655f
TYPICAL PERFORMANCE CHARACTERISTICS T
A
= 25C unless otherwise noted.
LTC2655-H16
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
CODE
128
I
N
L

(
L
S
B
)
4
2
1
3
2
3
1
0
4
32768 49152 16384
2655 G08
65535
V
CC
= 5V
CODE
128
D
N
L

(
L
S
B
)
1.0
0.5
0.5
0
1.0
32768 49152 16384
2655 G09
65535
V
CC
= 5V
Settling to 1LSB Rising Settling to 1LSB Falling
2s/DIV
V
OUT
250V/DIV
SCL
5V/DIV
2655 G13
9TH CLOCK OF
3RD DATA BYTE
7.9s
1/4 SCALE TO
3/4 SCALE STEP
V
CC
= 5V, V
FS
= 4.096V
R
L
= 2k, C
L
= 200pF
2s/DIV
V
OUT
250V/DIV
SCL
5V/DIV
2655 G14
9TH CLOCK OF
3RD DATA BYTE
5.5s
3/4 SCALE TO
1/4 SCALE STEP
V
CC
= 5V, V
FS
= 4.096V
R
L
= 2k, C
L
= 200pF
INL vs Temperature DNL vs Temperature
Reference Output Voltage
vs Temperature
TEMPERATURE (C)
50
I
N
L

(
L
S
B
)
4
2
2
3
1
1
3
0
4
50 30 10 110 90 70 10 30
2655 G10
130
V
CC
= 3V
INL(POS)
INL(NEG)
TEMPERATURE (C)
50
D
N
L

(
L
S
B
)
1.0
0.5
0.5
0
1.0
50 30 10 110 90 70 30 10
2655 G11
130
V
CC
= 3V
DNL(POS)
DNL(NEG)
TEMPERATURE (C)
50
V
R
E
F

(
V
)
2.054
2.044
2.046
2.052
2.050
2.048
2.042
50 30 10 110 90 70 30 10
2655 G12
130
V
CC
= 5V
LTC2655
13
2655f
TYPICAL PERFORMANCE CHARACTERISTICS
Current Limiting
Headroom at Rails
vs Output Current
Offset Error vs Temperature
Integral Nonlinearity (INL) Differential Nonlinearity (INL) Settling to 1LSB Falling
Load Regulation
CODE
8
I
N
L

(
L
S
B
)
1.0
0.5
0.5
0
1.0
2048 3072 1024
2655 G15
4095
V
CC
= 5V
V
REF
= 2.048V
CODE
8
D
N
L

(
L
S
B
)
1.0
0.5
0.5
0
1.0
2048 3072 1024
2655 G16
4095
V
CC
= 3V
V
REF
= 1.25V
2s/DIV
V
OUT
1mV/DIV
SCL
3V/DIV
2655 G17
4.0s
3/4 TO 1/4 SCALE STEP
V
CC
= 3V, V
FS
= 2.5V
R
L
= 2k, C
L
= 200pF
AVERAGE OF 2048 EVENTS
I
OUT
(mA)
50

V
O
U
T

(
m
V
)
10
6
8
4
2
8
6
4
2
0
10
0 10 20 30 40 20 10 40 30
2655 G18
50
INTERNAL REF
CODE = MID-SCALE
V
CC
= 5V (LTC2655-H)
V
CC
= 3V (LTC2655-L)
I
OUT
(mA)
50

V
O
U
T

(
V
)
0.20
0.10
0.15
0.05
0.15
0.10
0.05
0
0.20
0 10 20 30 40 20 10 40 30
2655 G19
50
INTERNAL REF
CODE = MID-SCALE
V
CC
= 5V (LTC2655-H)
V
CC
= 3V (LTC2655-L)
I
OUT
(mA)
0
V
O
U
T

(
V
)
5.0
1.0
0.5
1.5
2.0
4.5
4.0
3.5
3.0
2.5
0
5 4 3 8 9 7 6 1 2
2655 G20
10
5V (LTC2655-H) SOURCING
3V (LTC2655-L) SOURCING
5V (LTC2655-H) SINKING
3V (LTC2655-L) SINKING
TEMPERATURE (C)
50
O
F
F
S
E
T

E
R
R
O
R

(
m
V
)
3
2
1
2
1
0
3
50 30 10 110 90 70 30 10
2655 G21
130
T
A
= 25C unless otherwise noted.
LTC2655-12
LTC2655
Zero-Scale Error vs Temperature Gain Error vs Temperature
TEMPERATURE (C)
50
Z
E
R
O
-
S
C
A
L
E

E
R
R
O
R

(
m
V
)
3.0
2.0
0.5
2.5
1.5
1.0
0
50 30 10 110 90 70 30 10
2655 G22
130
TEMPERATURE (C)
50
G
A
I
N

E
R
R
O
R

(
L
S
B
)
64
32
16
48
48
0
32
16
64
50 30 10 110 90 70 30 10
2655 G23
130
LTC2655-16
LTC2655
14
2655f
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs Reference Input
REFERENCE VOLTAGE (V)
0.5
O
F
F
S
E
T

E
R
R
O
R


(
m
V
)
2.0
1.0
1.5
0.5
1.5
1.0
0.5
0
2
2 1 1.5
2655 G24
2.5
V
CC
= 5V
OFFSET ERROR OF 4 CHANNELS
T
A
= 25C unless otherwise noted.
LTC2655
Supply Current vs Temperature I
CC
Shutdown vs Temperature
Multiplying Bandwidth
TEMPERATURE (C)
50
S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
3.0
2.0
2.5
1.5
1.0
50 30 10 110 90 70 30 10
2655 G28
130
LTC2655-H
V
CC
= 5V, CODE = MS
INTERNAL REFERENCE
LTC2655-L
V
CC
= 3V, CODE = MS
INTERNAL REFERENCE
TEMPERATURE (C)
50
I
C
C

S
H
U
T
D
O
W
N

(

A
)
5
3
4
2
1
0
50 30 10 110 90 70 30 10
2655 G29
130
LTC2655-H
V
CC
= 5V
LTC2655-L
V
CC
= 3V
FREQUENCY (Hz)
A
M
P
L
I
T
U
D
E

(
d
B
)
2655 G30
8
2
0
4
6
2
4
6
8
10
12
1k 100k 1M 10k
V
S
= 5V
V
REF(DC)
= 2V
V
REF(AC)
= 0.2V
P-P
CODE = FULL-SCALE
Gain Error vs Reference Input I
CC
Shutdown vs V
CC
Supply Current vs Logic Voltage
REFERENCE VOLTAGE (V)
0.5
G
A
I
N

E
R
R
O
R


(
L
S
B
)
64
32
48
16
48
32
16
0
64
2 1 1.5
2655 G25
2.5
LTC2655-16
V
CC
= 5.5V
GAIN ERROR OF 4 CHANNELS
V
CC
(V)
2.5
I
C
C

(
n
A
)
450
150
100
50
200
400
350
300
250
0
5 3.5 3 4.5 4
2655 G26
5.5
LOGIC VOLTAGE (V)
0
I
C
C

(
m
A
)
2.6
1.6
2.4
2.2
2.0
1.8
1.4
2 1 4 3
2655 G27
SWEEP SCL AND SDA
BETWEEN
0V AND V
CC
V
CC
= 3V
(LTC2655-L)
V
CC
= 5V
(LTC2655-H)
5
Large-Signal Response Mid-Scale Glitch Impulse
2s/DIV
V
OUT
1V/DIV
2655 G31
V
CC
= 5V, V
REF
= 2.048V
ZERO-SCALE TO FULL-SCALE
2s/DIV
V
OUT
5mV/DIV
SCL
5V/DIV
2655 G32
LTC2655-H16, V
CC
= 5V
7nV-s TYP
LTC2655-L16, V
CC
= 3V
4nV-s TYP
9TH CLOCK OF
3RD DATA BYTE
LTC2655
15
2655f
TYPICAL PERFORMANCE CHARACTERISTICS
DAC Output 0.1Hz to
10Hz Voltage Noise
Reference 0.1Hz to
10Hz Voltage Noise
DAC to DAC Crosstalk (Dynamic) Power-On Reset Glitch
Power-On Reset to Mid-Scale Noise Voltage vs Frequency
2s/DIV
V
OUT
0.5mV/DIV
ONE DAC
SWITCH 0-FS
1V/DIV
2655 G33
LTC2655-L16, V
CC
= 5V, 0.4nVs TYP
C
REFCOMP
= C
REFOUT
= 0.22F
200s/DIV
V
OUT
10mV/DIV
V
CC
2V/DIV
2655 G34
ZERO-SCALE
1ms/DIV
V
OUT
1V/DIV
V
CC
2V/DIV
2655 G35
LTC2655-L
FREQUENCY (Hz)
N
O
I
S
E

V
O
L
T
A
G
E

(
n
V
/

H
z
)
2655 G36
400
300
200
100
0
10 100 100k 1M 10k 1k
V
CC
= 5V
CODE = MID-SCALE
INTERNAL REF
C
REFCOMP
= C
REFOUT
= 0.1F
LTC2655-H
LTC2655-L
1s/DIV
5V/DIV
2655 G37
V
CC
= 5V, LTC2655-H
CODE = MID-SCALE
INTERNAL REF
C
REFCOMP
= C
REFOUT
= 0.1F
1s/DIV
2V/DIV
2655 G38
V
REFOUT
= 2.048V
C
REFCOMP
= C
REFOUT
= 0.1F
T
A
= 25C unless otherwise noted.
LTC2655
LTC2655
16
2655f
PIN FUNCTIONS
REFLO (Pin 1/Pin 20): Reference Low. The voltage at this
pin sets the zero-scale voltage of all DACs. This pin should
be tied to GND.
V
OUTA
to V
OUTD
(Pins 2,4,13,14/Pins 1, 3, 13, 14): DAC
Analog Voltage Outputs. The output range is 0V to 2 times
the voltage at the REFIN/OUT pin.
REFCOMP (Pin 3/Pin 2): Internal Reference Compensation.
For low noise and reference stability, tie 0.1F capacitor
to GND. Connect to GND to use an external reference at
start-up. Command 0111b must still be issued to turn off
internal reference.
REFIN/OUT (Pin 5/Pin 4): This pin acts as the internal
reference output in internal reference mode and acts as
the reference input pin in external reference mode. When
acting as an output the nominal voltage at this pin is
1.25V for -L options and 2.048V for -H options. For low
noise and reference stability tie a capacitor from this pin
to GND. Capacitor value must be C
REFCOMP
. In external
reference mode, the allowable reference input voltage
range is 0.5V to V
CC
/2.
LDAC (Pin 6/Pin 5): Asynchronous DAC Update. A fall-
ing edge on this input after four bytes have been written
into the part, immediately updates the DAC register with
the contents of the input register. A low on this input
without a complete 32-bit (four bytes including the slave
address) data write transfer to the part does not update
the DAC output. Software power-down is disabled when
LDAC is low.
CA2 (Pin 7/Pin 6): Chip Address Bit 2. Tie this pin to V
CC
,
GND or leave it oating to select an I
2
C slave address for
the part (Table 2).
SCL (Pin 8/Pin 7): Serial Clock Input. Data is shifted
into the SDA pin at the rising edges of the clock. This
high impedance pin requires a pull-up resistor or current
source to V
CC
.
SDA (Pin 9/Pin 9): Serial Data Bidirectional. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This is
a high impedance pin while data is shifted in. It is an open-
drain N-channel output during acknowledgement. This pin
requires a pull-up resistor or current source to V
CC
.
CA1 (Pin 10/Pin 10): Chip Address Bit 1. Tie this pin to
V
CC
, GND or leave it oating to select an I
2
C slave address
for the part (Table 2).
CA0 (Pin 11/Pin 11): Chip Address Bit 0. Tie this pin to
V
CC
, GND or leave it oating to select an I
2
C slave address
for the part (Table 2).
PORSEL (Pin 12/Pin 12): Power-On-Reset Select. If tied
to GND, the part resets to zero-scale at power-up, if tied
to V
CC
, the part resets to mid-scale.
V
CC
(Pin 15/Pin 18): Supply Voltage Input. For -L options,
2.7V V
CC
5.5V, and for -H options, 4.5V V
CC
5.5V.
Bypass to ground with a 0.1F capacitor placed as close
to pin as possible.
GND (Pin 16/Pin 19, Exposed Pad Pin 21): Ground. Must
be soldered to PCB Ground.
DNC (NA/Pins 8, 15, 16, 17): Do not connect these
pins.
(GN/UF)
LTC2655
17
2655f
BLOCK DIAGRAM
2655 BD
GND
V
OUTA
V
OUTB
SCL
CA2
LDAC
REFLO
CA1
CA0
REFIN/OUT
REFCOMP
V
CC
V
OUTD
V
OUTC
PORSEL
SDA
INTERNAL REFERENCE
DAC A
POWER-ON
RESET
DAC B
DAC D
DAC C
R
E
G
I
S
T
E
R
32-BIT SHIFT REGISTER
2-WIRE INTERFACE
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
LTC2655
18
2655f
TIMING DIAGRAM
Figure 1
V
IH(CA
n
)
/V
IL(CA
n
)
CAn
100
2655 TC01
GND
R
INH
/R
INL
/R
INF
V
DD
2655 TC02
Test Circuit 1
Test Circuit 2
TEST CIRCUITS
SDA
t
f
S
t
r
t
LOW
t
HD(STA)
ALL VOLTAGE LEVELS REFER TO V
IH(MIN)
AND V
IL(MAX)
LEVELS
t
HD(DAT)
t
SU(DAT)
t
SU(STA)
t
HD(STA)
t
SU(STO)
t
SP
t
BUF
t
r
t
f
t
HIGH
SCL
S P S
2655 F01
9TH CLOCK
OF 3RD
DATA BYTE
t
1
SCL
LDAC
LTC2655
19
2655f
The LTC2655 is a family of quad voltage output DACs in
20-lead 4mm 4mm QFN and in 16-lead narrow SSOP
packages. Each DAC can operate rail-to-rail in external
reference mode, or with its full-scale voltage set by an
integrated reference. Four combinations of accuracy (16-bit
and 12-bit), and full-scale voltage (2.5V or 4.096V) are
available. The LTC2655 is controlled using a 2-wire I
2
C
compatible interface.
Power-On Reset
The LTC2655-L/LTC2655-H clear the output to zero-scale
if PORSEL pin is tied to GND, when power is rst applied,
making system initialization consistent and repeatable. For
some applications, downstream circuits are active during
DAC power-up, and may be sensitive to nonzero outputs
from the DAC during this time. The LTC2655 contains
circuitry to reduce the power-on glitch. The analog outputs
typically rise less than 10mV above zero-scale during power
on if the power supply is ramped to 5V in 1ms or more.
In general, the glitch amplitude decreases as the power
supply ramp time is increased. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Alternatively, if PORSEL pin is tied to V
CC
, The LTC2655-L/
LTC2655-H set the output to mid-scale when power is
rst applied.
Power Supply Sequencing and Start-Up
For the LTC2655 family of parts, the internal reference is
powered up at start-up by default. If an external reference
is to be used, REFCOMP (Pin 3/Pin 2, GN/UF) must be
hardwired to GND. This conguration allows the use of an
external reference at start-up and converts the REFIN/OUT
pin to an input. However, the internal reference will still be
ON and draw supply current. In order to use an external
reference, command 0111b should be used to turn the
internal reference off (see Table 1).
The voltage at REFIN/OUT (Pin 5/Pin 4, GN/UF) should be
kept within the range 0.3V REFIN/OUT V
CC
+ 0.3V
(see the Absolute Maximum Ratings section). Particular
care should be taken to observe these limits during power
supply turn-on and turn-off sequences, when the voltage
at V
CC
(Pin 15/Pin 18, GN/UF) is in transition.
Transfer Function
The digital-to-analog transfer function is
V
OUT(IDEAL)
= 2 k/2
N
[V
REF
REFLO] + REFLO
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and V
REF
is the voltage at the
REFIN/OUT Pin. The resulting DAC output span is 0V to
2V
REF
, as it is necessary to tie REFLO to GND. V
REF
is
nominally 1.25V for LTC2655-L and 2.048V for LTC2655-H,
in internal reference mode.
Table 1
COMMAND*
C3 C2 C1 C0
0 0 0 0 Write to Input Register n
0 0 0 1 Update (Power-Up) DAC Register n
0 0 1 0 Write to Input Register n, Update (Power-Up) All
0 0 1 1 Write to and Update (Power-Up) n
0 1 0 0 Power-Down n
0 1 0 1 Power-Down Chip (All DACs and Reference)
0 1 1 0 Select Internal Reference (Power-Up Reference)
0 1 1 1 Select External Reference (Power-Down Reference)
1 1 1 1 No Operation
ADDRESS (n)*
A3 A2 A1 A0
0 0 0 0 DAC A
0 0 0 1 DAC B
0 0 1 0 DAC C
0 0 1 1 DAC D
1 1 1 1 All DACs
* Command and address codes not shown are reserved and should not
be used.
Serial Interface
The LTC2655 communicates with a host using the stan-
dard 2-wire I
2
C interface. The Timing Diagram (Figure 1)
shows the timing relationship of the signals on the bus.
The two bus lines, SDA and SCL, must be high when the
bus is not in use. External pull-up resistors or current
sources are required on these lines. The value of these
pull-up resistors is dependent on the power supply and
can be obtained from the I
2
C specications. For an I
2
C
bus operating in the fast mode, an active pull-up will be
OPERATION
LTC2655
20
2655f
necessary if the bus capacitance is greater than 200pF.
The LTC2655 is a receive-only (slave) device. The master
can write to the LTC2655. The LTC2655 does not respond
to a read command from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be high.
A bus master signals the beginning of a communication
to a slave device by transmitting a START condition (see
Figure 1). A START condition is generated by transitioning
SDA from high to low while SCL is high. When the master
has nished communicating with the slave, it issues a STOP
condition. A STOP condition is generated by transitioning
SDA from low to high while SCL is high. The bus is then
free for communication with another I
2
C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the lat-
est byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
bus line during the Acknowledge clock pulse so that it
remains a stable LOW during the HIGH period of this clock
pulse. The LTC2655 responds to a write by a master in
this manner. The LTC2655 does not acknowledge a read
(retains SDA HIGH during the period of the Acknowledge
clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set
to any one of three states: V
CC
, GND or oat. This results
in 27 selectable addresses for the part. The slave address
assignments are shown in Table 2.
In addition to the address selected by the address pins,
the parts also respond to a global address. This address
allows a common write to all LTC2655 parts to be accom-
plished with one 3-byte write transaction on the I
2
C bus.
The global address is a 7-bit on-chip hardwired address
and is not selectable by CA0, CA1 and CA2. The addresses
corresponding to the states of CA0, CA1 and CA2 and
the global address are shown in Table 2. The maximum
capacitive load allowed on the address pins (CA0, CA1
and CA2) is 10pF, as these pins are driven during address
detection to determine if they are oating.
Table 2. Slave Address Map
CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0
GND GND GND 0 0 1 0 0 0 0
GND GND FLOAT 0 0 1 0 0 0 1
GND GND V
CC
0 0 1 0 0 1 0
GND FLOAT GND 0 0 1 0 0 1 1
GND FLOAT FLOAT 0 1 0 0 0 0 0
GND FLOAT V
CC
0 1 0 0 0 0 1
GND V
CC
GND 0 1 0 0 0 1 0
GND V
CC
FLOAT 0 1 0 0 0 1 1
GND V
CC
V
CC
0 1 1 0 0 0 0
FLOAT GND GND 0 1 1 0 0 0 1
FLOAT GND FLOAT 0 1 1 0 0 1 0
FLOAT GND V
CC
0 1 1 0 0 1 1
FLOAT FLOAT GND 1 0 0 0 0 0 0
FLOAT FLOAT FLOAT 1 0 0 0 0 0 1
FLOAT FLOAT V
CC
1 0 0 0 0 1 0
FLOAT V
CC
GND 1 0 0 0 0 1 1
FLOAT V
CC
FLOAT 1 0 1 0 0 0 0
FLOAT V
CC
V
CC
1 0 1 0 0 0 1
V
CC
GND GND 1 0 1 0 0 1 0
V
CC
GND FLOAT 1 0 1 0 0 1 1
V
CC
GND V
CC
1 1 0 0 0 0 0
V
CC
FLOAT GND 1 1 0 0 0 0 1
V
CC
FLOAT FLOAT 1 1 0 0 0 1 0
V
CC
FLOAT V
CC
1 1 0 0 0 1 1
V
CC
V
CC
GND 1 1 1 0 0 0 0
V
CC
V
CC
FLOAT 1 1 1 0 0 0 1
V
CC
V
CC
V
CC
1 1 1 0 0 1 0
GLOBAL ADDRESS 1 1 1 0 0 1 1
OPERATION
LTC2655
21
2655f
OPERATION
Write Word Protocol
The master initiates communication with the LTC2655
with a START condition and a 7-bit slave address followed
by the Write bit (W) = 0. The LTC2655 acknowledges by
pulling the SDA pin low at the 9th clock if the 7-bit slave
address matches the address of the part (set by CA0, CA1
and CA2) or the global address. The master then transmits
three bytes of write data. The LTC2655 acknowledges each
byte of data by pulling the SDA line low at the 9th clock of
each data byte transmission. After receiving three com-
plete bytes of data, the LTC2655 executes the command
specied in the 24-bit input word. If more than three data
bytes are transmitted after a valid 7-bit slave address, the
LTC2655 does not acknowledge the extra bytes of data
(SDA is high during the 9th clock). The rst byte of the
input word consists of the 4-bit command followed by
the 4-bit address. The next two bytes consist of the 16-bit
data word. The 16-bit data word consists of the 16-bit, or
12-bit input code, MSB to LSB, followed by 0 or 4 dont
care bits (LTC2655-16 and LTC2655-12 respectively). A
typical LTC2655 write transaction is shown in Figure 2.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The rst four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register into
the input register. In an update operation, the data word
is copied from the input register to the DAC register and
converted to an analog voltage at the DAC output. The
update operation also powers up the DAC if it had been in
power-down mode. The data path and registers are shown
in the Block Diagram.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than four outputs are needed. When in power-down, the
buffer ampliers, bias circuits and integrated reference
circuits are disabled, and draw essentially zero current.
The DAC outputs are put into a high-impedance state, and
the output pins are passively pulled to ground through
individual 80k resistors. Input- and DAC-register contents
are not disturbed during power-down.
Any channel or combination of channels can be put into
power-down mode by using command 0100b in combina-
tion with the appropriate DAC address, (n). The integrated
reference is automatically powered down when external
reference mode is selected using command 0111b. In ad-
dition, all the DAC channels and the integrated reference
together can be put into power-down mode using the
Power-Down Chip command 0101b. For all power-down
commands the 16-bit data word is ignored, but still required
in order to complete a full communication cycle.
Normal operation resumes by executing any command
which includes a DAC update, in software as shown in
Table 1 or using the asynchronous LDAC pin. The selected
DAC is powered up as its voltage output is updated. When
a DAC which is in a powered-down state is powered up and
updated, normal settling is delayed. If less than four DACs
are in a powered-down state prior to the update command,
the power-up delay time is approximately 12s. If on the
other hand, all four DACs and the integrated reference
are powered down, then the main bias generation circuit
block has been automatically shut down in addition to the
individual DAC ampliers and the integrated reference.
LTC2655
22
2655f
In this case, the power-up delay time is approximately
14s. The power-up of the integrated reference depends
on the command that powered it down. If the reference is
powered down using the Select External Reference com-
mand (0111b), then it can only be powered back up by
sending the Select Internal Reference command (0110b).
However if the reference was powered down by sending
the Power-Down Chip command (0101b), then in addition
to the Select Internal Reference command (0110b), any
command that powers up the DACs will also power-up
the integrated reference.
Reference Modes
For applications where an accurate external reference is
not available, the LTC2655 has a user-selectable, inte-
grated reference. The LTC2655-L has a 1.25V reference
that provides a full-scale output of 2.5V. The LTC2655-H
has a 2.048V reference that provides a full-scale output
of 4.096V. Both references exhibit a typical temperature
drift of 2ppm/C. Internal reference mode can be selected
by using command 0110b, and is the power-on default. A
buffer is needed if the internal reference is required to drive
external circuitry. For reference stability and low noise, it
is recommended that a 0.1F capacitor be tied between
REFCOMP and GND. In this conguration, the internal
reference can drive up to 0.1F capacitive load without any
stability problems. In order to ensure stable operation, the
capacitive load on the REFIN/OUT pin should not exceed
the capacitive load on the REFCOMP pin.
The DAC can also operate in external reference mode using
command 0111b. In this mode, the REFIN/OUT pin acts
as an input that sets the DACs reference voltage. This
input is high impedance and does not load the external
reference source. The acceptable voltage range at this
pin is 0.5V REFIN/OUT V
CC
/2. The resulting full-scale
output voltage is 2V
REFIN/OUT
. For using external refer-
ence at start-up, see the Power Supply Sequencing and
Start-Up Sections.
Integrated Reference Buffers
Each of the four DACs in LTC2655 has its own integrated
high performance reference buffer. The buffers have very
high input impedance and do not load the reference volt-
age source. These buffers shield the reference voltage
from glitches caused by DAC switching and thus minimize
DAC-to-DAC dynamic crosstalk. By tying 0.22F capacitors
between REFCOMP and GND, and also between REFIN/OUT
and GND, the crosstalk can be reduced to less than 1nVs.
See the curve DAC-to-DAC Crosstalk (Dynamic) in the
Typical Performance Characteristics section.
Voltage Outputs
Each of the four rail-to-rail ampliers contained in LTC2655
has guaranteed load regulation when sourcing or sinking
up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the ampliers ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The ampliers DC output
impedance is 0.040 when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30 typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The ampliers are stable driving capacitive loads of up
to 1000pF.
OPERATION
LTC2655
23
2655f
Board Layout
The excellent load regulation and DC crosstalk performance
of these devices is achieved in part by keeping signal and
power grounds separate.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the devices ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. The REFLO pin should be connected to system
star ground. Resistance from the REFLO pin to system
star ground should be as low as possible.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur in external refer-
ence mode near full scale when the REFIN/OUT pin is at
V
CC
/2. If V
REFIN/OUT
= V
CC
/2 and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits
at V
CC
as shown in Figure 3c. No full-scale limiting can
occur if V
REFIN/OUT
(V
CC
F
SE
)/2.
Offset and linearity are dened and tested over the region
of the DAC transfer function where no output limiting can
occur.
OPERATION
LTC2655
24
2655f
OPERATION
F
i
g
u
r
e

2
.

T
y
p
i
c
a
l

L
T
C
2
6
5
5

I
n
p
u
t

W
a
v
e
f
o
r
m

P
r
o
g
r
a
m
m
i
n
g

D
A
C

O
u
t
p
u
t

f
o
r

F
u
l
l
-
S
c
a
l
e
A
C
K
A
C
K
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
2
6
5
5
F
0
2
A
C
K
S
T
A
R
T
S
T
O
P
F
U
L
L
-
S
C
A
L
E
V
O
L
T
A
G
E
Z
E
R
O
-
S
C
A
L
E
V
O
L
T
A
G
E
S
D
A
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
S
C
L
V
O
U
T
C
2
C
3
C
3
C
2
C
1
C
0
A
3
A
2
A
1
A
0
C
1
C
0
A
3
A
2
A
1
A
0
A
C
K
C
O
M
M
A
N
D
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
M
S

D
A
T
A
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
L
S

D
A
T
A
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
W
R
S
L
A
V
E

A
D
D
R
E
S
S
LTC2655
25
2655f
OPERATION
2655 F03
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
32, 768 0 65, 535
INPUT CODE
OUTPUT
VOLTAGE
(a)
V
REF
= V
CC
V
REF
= V
CC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function,
(b) Effect of Negative Offset for Codes Near Zero-Scale, (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
LTC2655
26
2655f
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0204
1 2 3 4 5 6 7 8
.229 .244
(5.817 6.198)
.150 .157**
(3.810 3.988)
16 15 14 13
.189 .196*
(4.801 4.978)
12 11 10 9
.016 .050
(0.406 1.270)
.015 .004
(0.38 0.10)
45
0 8 TYP
.007 .0098
(0.178 0.249)
.0532 .0688
(1.35 1.75)
.008 .012
(0.203 0.305)
TYP
.004 .0098
(0.102 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 .165
.0250 BSC .0165 .0015
.045 .005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
LTC2655
27
2655f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UF Package
20-Lead (4mm 4mm) Plastic QFN
(Reference LTC DWG # 05-08-1710 Rev A)
4.00 0.10
4.00 0.10
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
20 19
1
2
BOTTOM VIEWEXPOSED PAD
2.00 REF
2.45 0.10
0.75 0.05 R = 0.115
TYP
R = 0.05
TYP
0.25 0.05
0.50 BSC
0.200 REF
0.00 0.05
(UF20) QFN 01-07 REV A
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 0.05
0.25 0.05
0.50 BSC
2.00 REF
2.45 0.05
3.10 0.05
4.50 0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 45
CHAMFER
2.45 0.10
2.45 0.05
LTC2655
28
2655f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900

FAX: (408) 434-0507

www.linear.com LINEAR TECHNOLOGY CORPORATION 2010
LT 0710 PRINTED IN USA
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2655 TA02
LDAC
GND GND REFLO
LTC2655IUF-L16*
PORSEL
5V
*PIN NUMBERS SHOWN ARE FOR THE QFN PACKAGE.
V
CC
REFCOMP REFIN/OUT DNC DNC
DNC DNC
SCL
SDA
CA0
CA1
CA2
7
9
11
10
6
5 18 17 16 2 4
TO
MICROCONTROLLER
V
OUTA
V
OUTB
V
OUTC
V
OUTD
1
3
13
14
M9
M3
M1
8
9
10
1
2
3
P1
P3
P9
+5V C1
0.1F
C3
0.1F
C2
0.1F
+

450k
150k
150k
450k
50k
50k
450k
4pF
450k
V
OUT
5V
6
4 5
7
4pF
12V
+12V
LT1991

+
LTC6240IS5
+5V
19 21 20 12 8 15
3
4
5
2
1
V
CC
V
EE
REF
5V Bipolar Output DAC