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Chap. 5 Gate-Level Modeling

March 2003
http://edda.csie.dyu.edu.tw
Spring2003 Dept. of CSIE, DYU 2
Learning Objectives
Identify logic gate primitives provided in Verilog
Understand instantiation of gates, gate symbols and
truth tables for and/or and buf/not type gates
Understand how to construct a Verilog description
from the logic diagram of the circuit
Describe rise, fall, and turn-off delays in the gate-
level design
Explain min, max, ant typdelays in the gate-level
design
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Gate-Level Modeling
Gate Types
And/Or Gates
Buf/Not Gates
Examples
Gate Delays
Rise, Fall, and Turn-off Delays
Min/Typ/Max Values
Delay Example
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Gate Types
Verilog supports basic logic gates as
predefined primitives
Can be instantiated like modules and do not need
a module definition
Two classes of basic gates in Verilog
And/or gates
Buf/not gates
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And/ Or Gates
And/Or gates
Have one scalar output and multiple scalar inputs
The first terminal in the port list is connected to
the output and other terminals are to inputs
The output is evaluated as soon as one of the
inputs changes
The and/or gates available in Verilog
and, or, xor, nand, nor, xnor
logic symbol
in1
in2
out
and
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Gate Instantiation of And/ Or Gates
wi r e OUT, I N1, I N2, I N3;
and a1 ( OUT, I N1, I N2) ;
nand na1 ( OUT, I N1, I N2) ;
or or 1 ( OUT, I N1, I N2) ;
nor nor 1( OUT, I N1, I N2) ;
xor x1 ( OUT, I N1, I N2) ;
xnor nx1 ( OUT, I N1, I N2) ;
/ / mor e t han 2 i nput s
nand na1_3i np( OUT, I N1, I N2, I N3) ;
/ / wi t hout i nst ance name
and ( OUT, I N1, I N2) ;
more than 2
inputs can
be specified
instance name
does not need
to be specified
a1
I N1
I N2
OUT
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Truth Table of And/ Or Gates
0
x z 1 0
i1
and
0 z
0 x
1 0 1
0 0 0 0
i2
1
x z 1 0
i1
nand
1 z
1 x
0 1 1
1 1 1 0
i2
x z 1 0
i1
xor
z
x
0 1 1
1 0 0
i2
1
x z 1 0
i1
or
1 z
1 x
1 1 1 1
1 0 0
i2
0
x z 1 0
i1
nor
0 z
0 x
0 0 0 1
0 1 0
i2
x z 1 0
i1
xnor
z
x
1 0 1
0 1 0
i2
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Buf/ Not Gates
Buf/Not gates
Have one scalar output and one scalar input
The last terminal in the port list is connected to the input
and other terminals are to outputs
Two basic buf/not gates primitives in Verilog
buf, not
out in buf
z
x
1 1
0 0
buf b1( OUT1, I N) ;
not n1( OUT1, I N) ;
/ / mor e t han 2 out put s
buf b1_2out ( OUT1, OUT2, I N) ;
/ / wi t hout i nst ance name
not ( OUT1, I N) ;
out in not
z
x
0 1
1 0
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Bufif/ Notif Gates
Bufif/Notif gates
gates with additional control signal on buf and not
Two basic bufif/notif gates primitives in Verilog
bufif1, bufif0, notif1, notif0
propagate only if control signal is asserted
propagate z if control signal is deasserted
in
ctr1
out
bufif1
in
ctr1
out
notif1
in
ctr1
out
bufif0
in
ctr1
out
notif0
buf i f 1 b1( out , i n, ct r 1) ;
buf i f 0 b0( out , i n, ct r 1) ;
not i f 1 n1( out , i n, ct r 1) ;
not i f 0 n0( out , i n, ct r 1) ;
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Truth Table of Bufif/ Notif Gates
H
L
x z 1 0
ctr1
bufif0
z z
z x
H z 1 1
L z 0 0
in
H
L
x z 1 0
ctr1
bufif1
z z
z x
H 1 z 1
L 0 z 0
in
L
H
x z 1 0
ctr1
notif0
z z
z x
L z 0 1
H z 1 0
in
L
H
x z 1 0
ctr1
notif1
z z
z x
L 0 z 1
H 1 z 0
in
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Examples
Gate-level multiplexer
a 4-to-1 multiplexer with 2 select signals
4-to-1
Mux
i0
i1
i2
i3
s1 s0
out
i3
i2
i1
i0
out s0 s1
1 1
0 1
1 0
0 0
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Logic Diagram for 4-to-1 Multiplexer
4-to-1
Mux
i0
out
y0
y1
y2
y3
i1
i2
i3
s1
s0
s0n
s1n
module mux4_t o_1
endmodule
?
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Verilog Description of 4-to-1 Multiplexer
module mux4_t o_1( out , i 0, i 1, i 2, i 3, s1, s0) ;
out put out ;
i nput i 0, i 1, i 2, i 3;
i nput s1, s0;
wi r e s1n, s0n;
wi r e y0, y1, y2, y3;
not ( s1n, s1) ;
not ( s0n, s0) ;
and ( y0, i 0, s1n, s0n) ;
and ( y0, i 0, s1n, s0n) ;
and ( y0, i 0, s1n, s0n) ;
and ( y0, i 0, s1n, s0n) ;
or ( out , y0, y1, y2, y3) ;
endmodule
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Stimulus for 4-to-1 Multiplexer
module st i mul us;
r eg I N0, I N1, I N2, I N3;
r eg s1, s0;
wi r e OUTPUT;
mux4_t o_1 mymux( OUTPUT, I N0, I N1, I N2, I N3, S1, S0) ;
i ni t i al
begi n
I N0=1; I N1=0; I N2=1; I N3=0;
#1 $di spl ay( I N0=%b, I N1=%b, I N2=%b, I N3=%b\ n,
I N0, I N1, I N2, I N3) ;
s1=0; s0=0;
#1 $di spl ay( s1=%b, s0=%b, OUTPUT=%b\ n, s1, s0, OUTPUT) ;
s1=0; s0=1;
#1 $di spl ay( s1=%b, s0=%b, OUTPUT=%b\ n, s1, s0, OUTPUT) ;
s1=1; s0=0;
#1 $di spl ay( s1=%b, s0=%b, OUTPUT=%b\ n, s1, s0, OUTPUT) ;
s1=1; s0=1;
#1 $di spl ay( s1=%b, s0=%b, OUTPUT=%b\ n, s1, s0, OUTPUT) ;
end
endmodule
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Gate-Level Modeling
Gate Types
And/Or Gates
Buf/Not Gates
Examples
Gate Delays
Rise, Fall, and Turn-off Delays
Min/Typ/Max Values
Delay Example
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Gate Delays
10
10
t
t
in
out
not #10 (out, in)
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rise, fall, turn-off delays
0, x, or z to 1
1, x, or z to 0
0, 1 or x to z
t_rise
t_fall
t_turnoff
0, 1 or z to x
?
Min (t_rise,
t_fall,
t_trunoff)
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Types of Delay Specification
if nodelays are specified
the default value is zero
If only onedelay is specified
this value is used for all transitions
If twodelays are specified
they refer to the rise and fall delay values
the turn-off value is the minimum of the two delays
If threedelays are specified
they refer to the rise, fall, and turn-off delay values
and a0( out , i 1, i 2) ;
and #( 5) a1( out , i 1, i 2) ;
and #( 4, 6) a2( out , i 1, i 2) ;
and #( 3, 4, 5) a3( out , i 1, i 2) ;
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Example -- twodelays are specified
and #(3, 2) (out, in1, in2);
in1
in
2
out 3
2
t
t
t
1
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Example -- threedelays are specified
bufif1 #(3, 4, 7) (out, in ctrl);
in
1
ctrl
out
t
t
t
z
3 4 3 7
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Min / Typ/ Max Values
three values, min, typ, and max, can be specified
for each type of delays (rise, fall, and turn-off)
used to model devices whose delays vary within a min and
max range because of the IC fabrication process variations
any one value can be chosen at Verilog run time
method of choosing a value may vary for different simulator or OS
for Verilog-XL : by specifying +maxdelays, +typdelays, and
+mindelays with the command-line options
> verilog test.v +maxdelays
and #( 4: 5: 6) a1( out , i 1, i 2) ;
and #( 3: 4: 5, 5: 6: 7) a2( out , i 1, i 2) ;
and #( 2: 3: 4, 3: 4: 5, 4: 5: 6) a3( out , i 1, i 2) ;
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Delay Example
A simple module D
implements the logic
equations:
out = (a b)+c
#5
#4
e
out
a
b
c
D
modul e D( out , a, b, c) ;
out put out ;
i nput a, b, c;
wi r e e;
and #( 5) a1( e, a, b) ;
or #( 4) o1( out , e, c) ;
endmodul e
modul e st i mul us;
wi r e OUT;
r eg A, B, C;
D d1( OUT, A, B, C) ;
i ni t i al
begi n
A=1 b0; B=1 b0; C=1 b0;
#10 A=1 b1; B=1 b1; C=1 b1;
#10 A=1 b1; B=1 b0; C=1 b0;
#20 $f i ni sh;
end
endmodul e
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Waveforms for Delay Simulation
simulation using SILOS