Memory Test

Manuel dAbreu Santa Clara University

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Outline
Introduction Memory modeling Failure mechanisms and fault modeling Test algorithms for RAM Memory Built In Self Test (MemBIST)

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Growth Trends
1G

Number of transistor per chip

Number of bit per chip

100B 10B 1B 100M 10M 1M

RAMs

Microprocessors
100K 10K 1K

1970 74 78 82 86 90 94 98 02 06 10 14 Year
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Introduction

Memories (esp. RAM) are at the forefront of commercial electronic designs DRAMs are the technology driver for the semiconductor industry Memories are the most numerous IPs used in SOC designs (hundreds ! and >90% of an SoC in 2010)

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Main Types of Semiconductor Memory RAMs: Random Access Memories

Dynamic Random Access Memory (DRAM)

Highest possible density Slow access time (typically 20ns) Information stored as charge on capacitor and should be refreshed

Static Random Access Memory (SRAM)

Fastest (typically 2ns) Information stored in cross coupled latches

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Number of Memory Cells per Chip 10G Dynamic Random Acess Memory (DRAM)
Highest 1G

Main Types of Semiconductor Memory RAMs: Random Access Memories

4M Static 1M Random Acess Memory (SRAM)

512M 1G possible density Slow access time 128M (typically 20ns) 256M 100M Information stored as charge on capacitor and 16M 64M should be refreshed 10M

Fastest 256k (typically 2ns) 100k Information stored in cross coupled latches

1M

82

86

90

94

98

02

06

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Memory Architecture
Memory Address Register

Decoder
c

Decoder

Array of Cells r

Memory cell

Read/write Controls

Sense Amplifiers/ Write Drivers

Memory Data Register

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Functional SRAM Chip Model

Address Refresh Address latch Column decoder Refresh logic

Row decoder

Memory Cell Array

Write driver

Sense amplifiers

Data register R/W and CE

8

Data out Data in

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Functional SRAM Chip Model

Address Address latch Column decoder

Row decoder

Memory Cell Array Write driver

Sense amplifiers

Data register
R/W and CE

Data out
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Data in

Functional RAM Chip Model

Vdd Vdd Address Address latch Column decoder BL BL WL Refresh WL Refresh logic Vss Vss BL BL

6-device SRAM cell CMOS 6-devices SRAM cell 6-device SRAM cell

Row decoder

Memory Cell Array

poly depletion

Write driver

Sense amplifiers

Data register

R/W and CE
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Data out Data in

Functional RAM Chip Model

Address Address latch Refresh

Data in

Write
Column decoder Refresh logic

BL BL RAM write circuit

Row decoder Memory Cell Array Write driver

Sense amplifiers

Data register

R/W and CE
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Data out Data in

Functional RAM Chip Model

Address Address latch Column decoder Refresh Refresh logic

Row decoder

WL C

Memory Cell Array

Write driver

BL
single-device DRAM cell

Sense amplifiers

Data register

R/W and CE

Data out Data in

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Functional RAM Chip Model

Address Address latch Column decoder Refresh Refresh logic

Two dimensional decoding scheme Memory Row (saves decoder and wiring area) decoder row decoder selectCell row Array of cells via WL column decoder

Write driver

Sense amplifiers

Data register

R/W and CE

Data out Data in

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Memory Cell Designs

SET D Q

BL

WL Cbit
Q

CLR (a)

CBL (c) WL

Bit

BL

BL

Drain

Drain

(b)

NP1 PL1 NL1

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NP2 PL2 NL2

14

Bitbar

Reduced Functional Model

Address Address latch Column decoder Refresh Refresh logic

Read / Write logic

Row decoder Memory Cell Array

Write driver

Memory Cell Array Address decoder

Sense amplifiers Data register R/W and CE
15

Data out Data in

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Reduced Functional Model (cont)

Address Address decoder

Memory cell array

Read/write logic Data

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Memory testing

Memory testing has to prove that the circuits under test behave as designed, it consists of:

Parametric tests which concern voltage/current levels and delays on the IO pins of the chip Functional testing including dynamic testing

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Parametric (Electrical) Testing

DC Parametric testing

AC Parametric testing

Contact test Power consumption Leakage test Threshold test Output drive current test Output short current test

Rise and fall time Setup and hold time Delay test Speed test

IDDQ

testing (CMOS memories only)

Zero defect approach Use to detect some defects not handle by functional testing

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Functional faults

Cell stuck Driver stuck Read/write line stuck Chip-select line stuck Data line stuck Open in data line Shorts between data lines Crosstalk between data lines

Address line stuck Open in address line Shorts between address lines Open decoder Wrong access Multiple access Cell can be set to 0 and not to 1 (or vice versa) Pattern sensitive interaction between cells
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Either a memory cell or a data register

Functional faults

Cell stuck Driver stuck Read/write line stuck Chip-select line stuck Data line stuck Open in data line Shorts between data lines Crosstalk between data lines

Address line stuck Open in address line Shorts between address lines Open decoder Wrong access Multiple access Cell can be set to 0 and not to 1 (or vice versa) Pattern sensitive interaction between cells
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Either a memory cell or a data register

Functional faults
Any wiring connection in the memory

Cell stuck Driver stuck Read/write line stuck Chip-select line stuck Data line stuck Open in data line Shorts between data lines Crosstalk between data lines

Address line stuck Open in address line Shorts between address lines Open decoder Wrong access Multiple access Cell can be set to 0 and not to 1 (or vice versa) Pattern sensitive interaction between cells
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Fault Models: Address decoder Fault AF

4 Address decoder Faults which cannot stand alone
(assuming same fault during read and write operations and no sequential
behavior of the faulty decoder)
1. A certain address access no cell Ax 2. A certain cell is never accessed

Cx Cx

3. A certain address access multiple cells Ax

Cy

4. A certain cell is accessed by multiple addresses

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Ax Ay

Cx
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Fault Models: Address decoder Fault AF

4 Combinations of Address decoder Faults

Fault A: 1+2 Fault B: 1+3 Fault C: 2+4 Fault D: 3+4

Ax Ax Ay Ax Ay

Cx Cx Cy Cx Cy Cx Cy
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Ax Ay

Conditions for detecting address faults AF

The March test should contain the two following march elements (rx, , wx) (rx, , wx)

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Functional Memory Faults

A functional fault model is a non-empty set of fault primitives A fault primitive is a difference between the observed and the expected memory behavior A fault primitive is denoted by <S/F/R>

S describes the sensitizing operation sequence F describes the state stored in the faulty cell R describes the output of the read operation For example <1/0/-> is a stuck-at 1 and <0w1/0/-> is a rising transition fault
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Static and Dynamic faults

Static faults: sensitization needs only one operation (Testable by common March Tests)

Static Single-Cell Faults (S1CF) Static Two-Cell Faults (S2CF)

Dynamic faults: sensitization needs more than one operation (Not testable by common March Tests)

Dynamic Single-Cell Faults (D1CF) Dynamic Two-Cell Faults (D2CF)

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S1CF: Stuck-at fault (SAF)

The

logic value of (a line or) a cell is always 0 (SA0) or 1 (SA1) To detect memory cell's SAFs:
SA0:

Write 1 Read 1 (w1 r1) SA1: Write 0 Read 0 (w0 r0)

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S1CF: Transition Fault

A cell fails to undergo a 0 1 transition (TFrise) or a 1 0 transition (TFfall) when it is written To detect transition fault:
TF

: w0 w1 r1 TF : w1 w0 r0 fall
rise

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Basic Transitions
W0 W0 W0 0 Stuck-at 0 Write 0 on cell C(j) Read C(j) Write 1 on cell C(j) Read C(j)

W1

W1

W1 W0 1 Stuck-at 1 W1

Requires accessing each cell 4 times (2 writes and 2 reads). If access time is ta the testing time is 4Nta
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Transition Fault

W0

W0

W1

W1 0 to 1 Transition Fault

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Coupling Faults
Cell j a a W N b S Inversion W (b) NW N NE a Idempotent (a)
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Cell i

SW S SE (c)
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S1CF: Read Disturb Faults (RDF)

A Cell is said to have a RDF if the read operation performed on the cell returns an incorrect value while changing the contents of the cell to the wrong value To detect Read Disturb Fault from each cell a 1 and a 0 should be read

r0 r1

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S1CF: Deceptive Read Disturb Faults (DRDF)

A Cell is said to have a DRDF if the read operation performed on the cell returns the expected value while changing the contents of the cell to the wrong value To detect Deceptive Read Disturb Fault each cell should be read twice successively. The first read sensitize the fault and the second detects it

r0r0 r1r1

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S1CF: Incorrect Read Faults (IRF)

A Cell is said to have a IRF if a read operation performed on the cell returns the incorrect value while keeping the correct stored value in the cell To detect Incorrect Read Fault from each cell a 1 and a 0 should be read

r0 r1

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S1CF: Write Disturb Faults (WDF)

A Cell is said to have a WDF if a non transition write operation causes a transition in the cell To detect Write Disturb Fault each cell should be read after a non-transition write

0w0r0 1w1r1

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Fault models: Coupling Fault (2 cells)

Implies two cells: the victim cell and the aggressor cell Different kinds of coupling faults:

Inversion coupling faults Idempotent coupling faults State coupling faults Dynamic coupling faults Bridging faults ..
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S2CF: Inversion Coupling Fault

Inversion Coupling Fault (CFin): The content of the victim cell is inverted if the aggressor cell has a transition According to the kind of transition (0 1 or 1 0) there is two possible CFin types: <

; ><; >

To detect CFin between cell x (victim) and y (aggressor)

CFin (y rise x inverted): w0x w0y w1y r0x. CFin (y fall x inverted): w0x w1y w0y r0x.

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S2CF: Idempotent Coupling Fault

Idempotent Coupling Fault (CFid): The victim is forced to 0 or 1 if the aggressor has a 0 1 or 1 0 transition According to the kind of transition (0 1 or 1 0) there is four possible CFid types: <;0 ><;0 ><;1 ><;1 > To detect CFid between cell x (victim) and cell y (aggressor) CFid (y rise x=0): w1x w0y w1y r1x CFid (y fall x=1): w0x w1y w0y r0x CFid (y rise x=1): w0x w0y w1y r0x CFid (y fall x=0): w1x w1y w0y r1x

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S2CF: State Coupling Fault

State Coupling Fault (CFst): The coupled cell (victim) is forced to 0 or 1 if the coupling cell (aggressor) is in a certain state There is four possible CFst types: <0;0 ><0;1 ><1;0 ><1;1 > To detect CFst between cell x (victim) and y (aggressor)

CFst (y=0 x=0): w1x w0y r1x CFst (y=0 x=1): w0x w0y r0x CFst (y=1 x=0): w1x w1y r1x CFst (y=1 x=1): w0x w1y r0x

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S2CF: Dynamic Coupling Fault

Dynamic Coupling Fault (CFdyn): The victim is forced to 0 or 1 if the aggressor cell has a read or write operation More general case of the Idempotent Coupling Fault (CFid) because it can be sensitized by any read or write operation There are four CFdyn faults
<r0 w0;0> <r0 w0;1> <r1 w1;0> <r1 w1;1>

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S2CF: Write (read) disturb coupling fault

Write disturb coupling (CFwd): A cell is said to have a CFwd if a non transition write perform on the victim results in a transition when the aggressor is set into a logic state There are four types of CFwd faults Read disturb coupling (CFrd): Two cells are said to have a CFrd if a read performed on the victim destroys the data stored in the victim if a given state is present in the aggressor There are four types of CFrd faults
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S2CF: Incorrect read coupling fault

Incorrect read coupling fault (CFir): Two cells are said to have an CFir if a read performed on the victim returns the incorrect logic value when the aggressor is sent into a given state There are four types of CFir faults

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S2CF: Deceptive read disturb coupling fault

Deceptive read disturb coupling fault (CFdr): A cells is said to have an CFdr if a read performed on the victim returns the correct logic value and changes the content of the victim, when the aggressor is sent into a given state There are four types of CFdr faults

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Fault models: Bridging Faults (BF)

A short between cells or lines (2 or more) This is a bidirectional fault caused by logic level rather than a transition Two sorts of bridging faults (BFs) exist:

AND-type (ABF): the shorted cells/lines take the AND value of their fault-free values (four possible ABFs) OR-type (OBF): the shorted cells/lines take the OR value of their fault-free values (four possible OBFs) "Cell x is the victim of cell y" and "Cell y is the victim of cell x" The faults are linked. It is possible that they will hide each other.

Can be made equivalent to a number of linked CFs, i.e.

To detect a BF, it might be necessary to write a certain pattern on adjacent memory cells, see checkerboard algorithm using (010101) pattern.
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Pattern Sensitive (PSF)

The victim cell is forced to 0 or 1 if a certain number of neighbors show a particular pattern The PSF is the most general k-coupling fault with k=n With the Neighborhood Pattern Sensitive Fault (NPSF), the neighborhood is limited to all the cells in a single position surrounding the base cell

Equivalent to an N-coupling fault involving more than one aggressor (up to 8 adjacent locations) Extremely hard to detect

For each memory cell: the effect of all the possible combinations (28) of the adjacent cells should be tested.
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Neighborhood Pattern Sensitive (NPSF)

In practice two types of NPSF are used The type-1 NPSF with 4 neighborhood cells (north, west, south, east) The type-2 NPSF with 8 neighborhood cells

Base cell Type-1 neighborhood cell

Base cell Type-2 neighborhood cell

Type-1
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Type-2
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Neighborhood Pattern Sensitive (NPSF)

Active NPSF (ANPSF):

change of the base cell due to a transition in the neighborhood cells Each base cell must be read in state 0 and in state 1, for all possible changes in the neighborhood pattern the change of the base cell is impossible due to a certain neighborhood cells configuration Each base cell must be written and read in state 0 and in state 1, for all permutations in the neighborhood pattern The content of the base cell is forced to a certain state due to a certain neighborhood pattern Each base cell must be read in state 0 and in state 1, for all permutations in the neighborhood pattern
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Passive NPSF (PNPSF):

Static NPSF (SNPSF):

Dynamic Fault models: examples

Sense Amplifier (SA) Recovery Fault

The SA saturates after a long sequence of 0s or 1s

Write Recovery Fault (addressing fault in the decoder)

Write followed by a read/write to another location affects the previously accessed location

Detection needs At-Speed testing !!

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Single-Cell Dynamic Fault Models: Dynamic RDF, IRF and DRDF

Definition similar to the static Read Disturb Fault, Incorrect Read Fault and Deceptive Read Disturb Faults with an initial write follows by one or more read operation

dRDF: A Cell is said to have a dRDF if a write followed by one or more read performed on the cell returns (on the last read) an incorrect value while changing the contents of the cell to the wrong value dIRF: A Cell is said to have a dIRF if a write followed by one or more read performed on the cell returns (on the last read) incorrect value while keeping the correct stored value in the cell dDRDF: A Cell is said to have a dDRRF if a write followed by one or more read performed on the cell returns (on the last read) the expected value while changing the contents of the cell to the wrong value
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Fault models: Data Retention (DRF)

A cell fails to retain its logic value after some time Due to a defective pull-up within a SRAM cell A cell loses its value due to leakage current: the cell lose its charge due to this leakage current Two different DRFs exist (loss of 1 and loss of 0) and may coexist To detect DRF => a delay has to be inserted before reading back memory content (usually ~ 10-100 ms) Can be easily add to any test algorithm Test time increase dramatically !
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Fault models: linked faults

Linked faults are two or more faults (coupling faults) that affect the same cell
<;1> <;1> <;0> <;0>

i

k 2 CFid linked faults

2 CFid faults

Can be of the same type ( i.e. CF x->y and CF z->y ) or of different types ( i.e. CF x->y and TFrise y ) They can hide each other (fault masking): Extremely difficult to detect
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Relation between functional faults and fault models

Cell stuck Driver stuck Read/write line stuck Chip-select line stuck Data line stuck Open in data line

SAF

Address line stuck Open in address line Shorts between address lines Open decoder AF Wrong access Multiple access

Shorts between data lines Crosstalk between data lines

Cell can be set to 0 and not to 1 (or vice versa) Pattern sensitive interaction between cells

TF
52

CF

NPSF

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Relation between functional faults and fault models (examples)

Vdd

7 1
WL

5 2
BL

3
Vss

6
BL

1, 2, 3: SA0 4: AF for cells after the open 5, 6: State Coupling Faults 7: SAF (depending on the cell content and the technology)

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Dynamic Read Destructive Fault in the Core Cell [ETS04]

BL WL Defect 1 COLUMN DECODER Tn2 Tn3 S Tp1 Tn1 DECODER ROW SB Tn4 Tp2 BLB

Defect
MEMORY ARRAY

Fault Model dRDF RDF; DRDF RDF; DRDF TF IRF; TF TF

Min Res(k) ~130 ~8 ~3 ~25 ~100 ~2000

1 2 3

I / O DATA

4 5 6

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Defect 1 involves a dynamic Read Destructive Fault

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Memory Built-In Self-Testing

Definitions Cell Transitions Basic Built-In-Self-Test Architecture Summary

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Definitions

Concurrent BIST Memory test that happens concurrently with normal system operation Transparent testing Memory test that is nonconcurrent, but preserves the original memory contents from before testing began

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Functional Testing

1. 2.

Galpat Algorithm
Solid all 0 (1) pattern is written to all N cells For each cell C(j): Complement C(j) Repeat the following sequence for k not equal to j Read C(j) Read C(k) Restore the contests of C(j) Looks like a sliding 1 across the array Requires N write operations For each iteration of step 2 C(j) is complemented twice There are 2(N-1) read operations Total number of operation is: N+ N[2+2(n-1)] = N+N(2N+1)

Since test is repeated for array initialized to 1, total test time is T = 2(2N2 +N)
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Marching Test

Special version of walking 1/0 minimizes excessive reading operations. March-C Test

Solid 0 pattern places in RAM. Contents read in ascending order. Check made to assert that content of each cell C(j) is 0 and then a 1 is written in the location Process repeated until all 1s are written on all cells. The cells are then read in descending order to verify that they contain 1s The 1s are then changed to 0s

Requires 11 read/write operations. Test time is T = 11N

Detects faults on decoders, transition faults (since it verifies that the cell can undergo transitions from 1 to 0 and vice versa), and some coupling faults

Variations like March C- and March C+ reduce operation times or add coverage (stuck-opens and some timing faults)
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Marches and Backgrounds

0 0 0 1 1 0 0 0 0 0 1 0 (a) 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 1 0 1 (d) 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1
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0 1 0 0

1 0 0 0 0 0 1 0 (c) 0 0 1 0

0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0

0 0 1 1 (b) 0 1 0 0

0 1 1 1 0 0 1 0 0 0 0 1

1 1 1 1 1 0 0 0

Memory Bist
Address decoder Test/ Normal Clk decoder Control & Timing MAR Memory Cell

Address Counter

MDR

Data Generator

Compactor & Comparator

Good/ No-good

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MBIST Architecture

MBIST insertion: after

system R/W control Bist_en system address R/W control

Addr

Slave
Array array data out comparator pass/fail BIST fail register

Master

system data in

Bist_en array data in Bist_en

background data generator

address generator

MBIST Controller

JTAG

clock, reset etc.

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LFSR and Inverse Pattern LFSR

NOR gate forces LFSR into all-0 state

Get all 2n patterns

Normal LFSR: G ( x) = x3 + x + 1

Inverse LFSR: G ( x) = x3 + x2 + 1
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Up / Down LFSR

Preferred memory BIST pattern generator

Satisfies March test conditions

0 M

0 M

U 1 X

D Q
X0

0 M

U 1 X

D Q
X1

0 M

U 1 X

D Q
X2

U 1 X

Up/Down
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Up / Down LFSR Pattern Sequences

Up Counting 000 100 110 111 011 101 010 001 Down Counting 000 001 010 101 011 111 110 100

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Mutual Comparator

Test 4 or more memory arrays at same time:

Apply same test commands & addresses to all 4 arrays at same time Assess errors when one of the di (responses) disagrees with the others

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Mutual Comparator System

Memory BIST with mutual comparator

Benefit: Need not have good machine response stored or generated

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Summary

BIST is gaining acceptance for testability insertion due to:

Reduced chip area overhead (only 1-3 % chip area for memory BIST) Allows partitioning of testing problem

Memory BIST widely used, < 1 % overhead Random logic BIST, 13 to 20 % area overheads

Experimental method has only 6.5 % overhead Used by IBM and Lucent Technologies in selected products
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SUMMARY
Introduction Memory modeling Failure mechanisms and fault modeling Test algorithms for RAM

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Test Algorithms: notation used

: indicates address ascending order : indicates address descending order : write 0 at current location : write 1 at current location

w0 w1 r0 r1

: read current location, expecting a 0 : read current location, expecting a 1 algorithm element full algorithm
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(.):

{(),(),,()}:

Test algorithms

Full Behavioral test is definitively too consuming (3.n.2n) Classical and early memory testing methods with test time proportional to

n (zero-one, checkerboard, ) n2 and n.log2(n) (walking1/0, ping-pong, Galpat, Galcol, )

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Test algorithm: Zero-One

This minimal test consists of writing 0s and 1s in the memory

Step1: write 0 in all cells Step2: read all cells (0 expected) Step3: write 1 in all cells Step4: read all cells (1 expected)

O(n) test Fault coverage:

Not all AFs detected SAFs detected if the adress decoder is fault free Not all TFs and CFs detected
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Test algorithm: Checkerboard

Cell are divided in two groups

Step1: write 1 in all green cells and 0 in pink cells Step2: read all cells Step3: write 0 in all green cells and 1 in pink cells Step4: read all cells

O(n) test Fault coverage:

Not all AFs detected SAFs detected if the address decoder is fault free Not all TFs and CFs detected

This test is able to detect bridging faults

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Test algorithms: GALPAT and Walking 1/0

Memory is filled with 0s (or 1s) except for the basecell which contains a 1 (0) During the test the base cell walks through the memory Difference between GALPAT and W 1/0 is in reading the base cell 0 0 0 0 1 0 GALPAT 0 0 0
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0000 0 1 00

0000

Walking 1/0

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Test algorithms: GALPAT and Walking 1/0

All AFs are detected and located All SAFs are detected and located All TFs are detected and located All CFs are also detected and located But both are O(n2) tests other tests have been proposed as a shorter alternative 0(n3/2):

Sliding diagonal Butterfly (only neighborhood cells of the base cell are read) GALCOL
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Test algorithms: GALPAT and Walking 1/0

1 1 0 0 0 1 0 All AFs are detected and located 0 0 All SAFs are detected and located 1 0 0 All TFs are detected and located 0 1 1 0
But both are O(n2) tests

0 1 0 1 1 0 0 0

0 1 0 0 1 1 0 0

0 0 1 0 0 1 1 0

All CFs are also detected and located other tests have been proposed as a shorter alternative (0(n3/2):

Sliding diagonal Butterfly (only neighborhood cells of the base cell are read) GALCOL

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Test algorithms test time

Number of operations n 1Mb 16Mb 256Mb 2Gb n 0.063 1.01 16.11 128.9 n.log2n 1.26 24.16 451 3994.4 n2 (hr!!) 18.33 4691.3 1200959.9 76861433.7

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Test algorithms test time

Number of operations n 1Mb 16Mb 256Mb 2Gb n 0.063 1.01 16.11 128.9 n.log2n 1.26 n2 (hr!!) 18.33 4691.3 1200959.9 76861433.7
77

8774 Years !!
451 3994.4
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March tests

The test is "marching" through the memory The test is composed of March elements represented between () March tests are the simplest tests (optimal ?) to detect most of the functional faults

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March tests: example of MATS++

{(w0); (r0,w1); (r1,w0,r0)}

For i=0 to n-1

Write 0 in cell Ci Read cell Ci and check its content (0 expected) Write 1 in cell Ci Read cell Ci and check its content (1 expected) Write 0 in cell Ci Read cell Ci and check its content (0 expected)

For i=0 to n-1 For i=n-1 to 0

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Testing of Neighborhood PatternSensitive Faults

Active NPSF (ANPSF):

Each base cell must be read in state 0 and in state 1, for all possible transitions in the neighborhood pattern (k-1).2k possible patterns, (type-1: k=5, type-2: k=9) Each base cell must be written and read in state 0 and in state 1, for all permutations in the neighborhood pattern 2k possible patterns Each base cell must be read in state 0 and in state 1, for all permutations in the neighborhood pattern 2k possible patterns

Passive NPSF (PNPSF):

Static NPSF (SNPSF):

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Testing of Neighborhood PatternSensitive Faults

It is essential to minimize the number of writes during NPSF testing SNPSF patterns are produced following an Hamiltonian sequence (Hamiltonian distance of 1 between patterns, Gray code for example): k+2k-1 writes

ANPSF and PNPSF patterns are produced following an Eulerian sequence : k+k.2k writes
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Testing of Neighborhood PatternSensitive Faults

Number of writes further reduced by testing the neighborhoods simultaneously

Tilling method: number of writes divided by k

Two-group method (type-1 only): number of writes divided by 4

a d B b c

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Group 1

Group 2

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Basic NPSF location algorithm

write base-cells with 0; loop apply a pattern; {it could change the base-cell from 0 to 1} read base-cell; endloop; write base-cells with 1; loop apply a pattern; {it could change the base-cell from 1 to 0} read base-cell; endloop;
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Basic NPSF detection algorithm

write base-cells with 0; loop apply a pattern; {it could change the base-cell from 0 to 1} read base-cell; endloop; write base-cells with 1; loop apply a pattern; {it could change the base-cell from 1 to 0} endloop; read base-cell;

Only valid for ANPSF or SNPSF for which no transition is needed in the base cell Tilling method cannot be used as base cells are changing
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NPSF testing algorithm summary

Algorithm Location SAF TDANPSF1G TLAPNPSF1G TLAPNPSF2T TLAPNPSF1T TLSNPSF1G TLSNPSF1T TLSNPSF2T TDSNPSF1G N Y Y Y Y Y Y N L L L L L L L L
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Fault coverage TF A D L L L L L L L L L L L L D L NPSF P S

Operation count

163.5 n 195.5 n 5122 n 194 n 43.5 n 39.2 n 569.8 n 36.125 n

85

NPSF testing algorithm summary

Detection Algorithm Location or Location
TDANPSF1G TLAPNPSF1G TLAPNPSF2T TLAPNPSF1T TLSNPSF1G TLSNPSF1T TLSNPSF2T TDSNPSF1G N Y Y Y Y Y Y N Fault coverage SAF L L L L L L L L
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TF A D L L L L L L

NPSF P L L L L L L D S

Operation count

163.5 n L 195.5 n 5122 n 194 n 43.5 n 39.2 n 569.8 n 36.125 n

86

NPSF testing algorithm summary

Detection Algorithm Location or Location Active Passive N TDANPSF1G Static
Y Y Y Y Y Y N Fault coverage SAF L L L L L L L L
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TF A D L L L L L L

NPSF P L L L L L L D S

Operation count

163.5 n L 195.5 n 5122 n 194 n 43.5 n 39.2 n 569.8 n 36.125 n

87

TLAPNPSF1G TLAPNPSF2T TLAPNPSF1T TLSNPSF1G TLSNPSF1T TLSNPSF2T TDSNPSF1G

NPSF testing algorithm summary

Detection Algorithm Location or Location Active Passivetype-1 TDANPSF1G N Static or Y TLAPNPSF1G type -2 T illing TLAPNPSF2T Y or
TLAPNPSF1T TLSNPSF1G TLSNPSF1T TLSNPSF2T TDSNPSF1G Fault coverage SAF L L L L L L L L
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TF A D L L L L L L

NPSF P L L L L L L D S

Operation count

163.5 n L 195.5 n 5122 n 194 n 43.5 n 39.2 n 569.8 n 36.125 n

88

2-Group Y method Y
Y Y N

Test Time Complexity (100MHz)

Size 1M 16M 64M 256M 1G 4G 16G N 0.01s 0.16s 0.66s 2.62s 10.5s 42s 2.8m 10N 0.1s 1.6s 6.6s 26s 1.8m 7m 28m NlogN 0.2s 3.9s 17s 1.23m 5.3m 22.4m 1.6h
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1.5

11s 11m 1.5h 12h 4d 32d 255d

3h 33d 1.43y 23y 366y 57c 915c

89

Classical Test Algorithms

Checkerboard Algorithm

Zero-one algorithm with checkerboard pattern Complexity is 4N For SAF and DRF

1 0 1 0 1 0 1 0 1

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90

Classical Test Algorithms

Galloping Pattern (GALPAT)

Complexity is 4N**2---only for characterization All AFs,TFs, CFs, and SAFs are located 1. Write background 0; 2. For BC = 0 to N-1 { Complement BC; For OC = 0 to N-1, OC != BC; { Read BC; Read OC; } Complement BC; } 3. Write background 1; 4. Repeat Step 2;
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BC

91

Classical Test Algorithms

Sliding (Galloping) Row/Column/Diagonal

Based on GALPAT, but instead of a bit, a complete row, column, or diagonal is shifted Complexity is 4N**1.5

1 1 1 1 1
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Classical Test Algorithms

Butterfly Algorithm

Complexity is 5NlogN

1. Write background 0; 2. For BC = 0 to N-1 { Complement BC; dist = 1; While dist <= mdist /* mdist < 0.5 col/row length */ 6 { Read cell @ dist north from BC; 1 Read cell @ dist east from BC; Read cell @ dist south from BC; 9 4 5 ,1 0 2 Read cell @ dist west from BC; 3 Read BC; dist *= 2; } 8 Complement BC; } 3. Write background 1; repeat Step 2;
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93

Classical Test Algorithms

Moving Inversion (MOVI) Algorithm [De Jonge &

Smeulders 1976]

For functional and AC parametric test

Functional

(13N): for AF, SAF, TF, and most CF

{ ( w0); ( r 0, w1, r1); ( r1, w0, r 0); ( r 0, w1, r1); ( r1, w0, r 0)}
Parametric

(12NlogN): for Read access time

2 successive Reads @ 2 different addresses with different data for all 2-address sequences differing in 1 bit Repeat T2~T5 for each address bit GALPAT---all 2-address sequences
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Classical Test Algorithms

Surround Disturb Algorithm

Examine how the cells in a row are affected when complementary data are written into adjacent cells of neighboring rows 1. For each cell[p,q] /* row p and column q */ { Write 0 in cell[p,q-1]; Write 0 in cell[p,q]; Write 0 in cell[p,q+1]; 0 Write 1 in cell[p-1,q]; Read 0 from cell[p,q+1]; Write 1 in cell[p+1,q]; Read 0 from cell[p,q-1]; Read 0 from cell[p,q]; } 2. Repeat Step 1 with complementary data;
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1 0 1 0

95

Classical Test Algorithms

Zero-one and checkerboard algorithms do not have sufficient coverage Other algorithms are too time-consuming for large RAM

Test time is the key factor of test cost Complexity ranges from N2 to NlogN

Need linear-time test algorithms with small constants

March test algorithms

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