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EC1362 MICROPROCESSOR AND MICROCONTROLLER

PERIPHERAL INTERFACING III UNIT

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8255 Programmable Peripheral Interface Introduction

8255 is a widely used programmable, parallel I/O device Can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O Has 24 I/O pins that can be grouped in two 8 bit parallel ports: A and B, with the remaining eight bits as port C. The 8 bits of port C can be used as individual bits or be grouped in two 4-bit ports: CUPPER(CU) and CLOWER(CL) Port A
CU CL

Port B
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Two Modes Bit Set/Reset (BSR) mode is used to set or reset the bits in port C I/O mode Mode 0 Mode 1 Mode 2 In mode 0 all ports function as simple I/O ports Mode 1 is a handshake mode whereby ports A and/or B use bits from port C as handshake signals. Handshake mode (two types of I/O data transfer) status check & interrupt In Mode 2, port A can be set up for bidirectional data transfer using handshake signals from port C and port B can be set up in either Mode 0 or Mode1. 2/17/2008

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Modes of 8255
D7 D6 0/1
BSR Mode (Bit set/Reset) For Port C No effect on I/O mode Mode 0 Simple I/O For ports A,B and C

D5 D4 D3

D2 D1

D0

I/O Mode

Mode 1 Handshake I/O for ports A and/or B Port C bits are used for handshake

Mode 2 Bidirectional data bus for port A Port B either in Mode 0 or 1 Port C bits are used for handshake

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Pin Configuration

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Signals of 8255

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It has a 40 pins of 4 groups. 1. Data bus buffer 2. Read Write control logic 3. Group A and Group B controls 4. Port A, B and C Data bus buffer: This is a tristate bidirectional buffer used to interface the 8255 to system data bus. Data is transmitted or received by the buffer on execution of input or output instruction by the CPU. Read/Write control logic: This unit accepts control signals ( RD , WR ) and also inputs from address bus and issues commands to individual group of control blocks ( Group A, Group B). 2/17/2008

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8255 block diagram

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RD(active low): Read signal enables the read operation. When this signal is low, the MPU reads data from a selected I/O port of the 8255 WR(active low): Write control signal enables the write operation. When this signal is low, the MPU writes into a selected I/O port or the control register RESET(active high): This signal clears the control register and sets all ports in the input mode. CS,A0 and A1: Device select signals: chip select is connected to a decoded address and A0 and A1 are generally connected to MPU address lines respectively
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The CS signal is the master chip select & A1 and A0 specify one of the I/O ports

CS 0 0 0 0 1

A1 0 0 1 1 X

A0 0 1 0 1 X

Selected Port A Port B Port C Control Register 8255 is not selected

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Group A and Group B controls : These block receive control from the CPU and issues commands to their respective ports. Group A - PA and PCU ( PC7 PC4) Group B PB and PCL ( PC3 PC0) Control word register can only be written into & no read operation of the CW register is allowed.

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a) Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be programmed in 3 modes mode 0, mode 1, mode 2. b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be programmed in mode 0, mode1. c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer. This port can be divided into two 4 bit ports and can be used as control signals for port A and port B. it can be programmed in mode 0.
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Expanded version of the control logic and I/O ports

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CONTROL WORD
The contents of the control register called the control word specify an I/O function for each port. This register can be accessed to write a control word when A0 & A1 are at logic 1 Control word register can only be written into and no read operation of the CW register is allowed. Bit D7 of the control register specifies either the I/O function or the Bit Set/Reset function. If Bit D7 =1, bits D6- D1 determine I/O functions in various mode If bit D7 = 0, port C operates in the Bit Set/Reset(BSR)mode.
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BSR (Bit Set/Reset) Mode

BSR mode is concerned only with the eight bits of port C, which can be set or reset by writing an appropriate control word in the control register. This control word when written in the control register, sets or resets one bit at a time as specified in the diagram In the BSR mode, individual bits of port C can be used for applications such an on/off switch.

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Control Word Format in the BSR Mode

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Mode 0: Simple Input or Output

In this mode, ports A and B are used as two simple 8 bit ports and port C as two 4 bit ports. Each port can be programmed to function as simply an input port or an output port. The input/output features in Mode 0 are Outputs are latched Input are not latched 16 different Input/output configurations possible

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Mode 0:Input or Output

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Mode 1: Input or Output with handshake

The features of this mode are Two ports (A and B) function as 8 bit I/O ports. They can be configured either as input or output ports. Each port uses three lines from port C as handshake signals. The remaining two lines of port C can be used for simple I/O functions. Input and output data are latched Interrupt logic is supported.

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Mode 1: Input Control Signals

Ports A and B are configured as input ports Port A uses the upper three signals PC3 ,PC4 and PC5 as handshake signals Port B uses the lower three signals PC2, PC1 and PC0 as handshake signals. STB (Strobe Input):This active low signal is generated by a peripheral device to indicate that it has transmitted a byte of data. The 8255A in response to STB, generates IBF and INTR.

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IBF(Input Buffer Full):This signal is an acknowledgement by the 8255A to indicate that the input latch has received the data byte. This is reset when the MPU reads the data INTR(Interrupt Request): This is an output signal that may be used to interrupt the MPU. This signal is generated if STB,IBF and INTE(Internal flip-flop) are all at logic 1. This is reset by the falling edge of the RD signal. INTE(Interrupt Enable): This is an internal flip-flop used to enable or disable the generation of the INTR signal. The two flip flops INTEA and INTEB are set/reset using the BSR mode. The INTEA is enabled or disabled through PC4 & INTEB is enabled or disabled through PC2.
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Mode 1 Input Configuration

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Mode 1: Output Control Signals

OBF (Output buffer full ) This status signal, whenever falls to low, indicates that CPU has written data to the specified output port. The OBF flip-flop will be set by a rising edge of WR signal and reset by a low going edge at the ACK input. ACK ( Acknowledge input ) ACK signal acts as an acknowledgement to be given by an output device. ACK signal, whenever low, informs the CPU that the data transferred by the CPU to the output device through the port is received by the output device.

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Output Control Signals( cont.)

INTR ( Interrupt request ) Thus an output signal that can be used to interrupt the CPU when an output device acknowledges the data received from the CPU. INTR is set when ACK, OBF and INTE are 1. It is reset by a falling edge on WR input. INTE(Interrupt Enable):The INTEA and INTEB flags are controlled by the bit set-reset mode of PC6 and PC2 respectively. PC4,5 :These two lines can be set up either as input or output.
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Mode 2 Bidirectional Data Transfer

The Salient features of Mode 2 of 8255 are listed as follows: The single 8-bit port in group A is available. The 8-bit port is bidirectional and additionally a 5-bit control port is available. Three I/O lines are available at port C.( PC2 PC0 ) Inputs and outputs are both latched. The 5-bit control port C (PC3-PC7) is used for generating / accepting handshake signals for the 8-bit data transfer on port A.

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CONTROL WORD FORMATS

Mode 1 Input Mode 1 Output

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Mode 2: Bidirectional Input/Output

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Mode 2: Bidirectional Input/Output

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REFERENCES
Microprocessor Architecture, Programming and Applications Ramesh Gaonkar Intel 8255 datasheet www.DatasheetCatalog.com

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Introduction
8254 programmable interval timer/counter is functionally similar to software designed counters and timers

Generates accurate time delays can be used for applications such as a real time clock, event counter, digital one-shot, square wave generator & a complex waveform generator Includes 3 identical counters that can operate in any one of 6 modes
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Introduction(cont.)
A 16 bit count is loaded in its register and, on command, begins to decrement the count until it reaches 0 At the end of count it generates a pulse that can be used to interrupt the MPU The counter can count either in binary or BCD. 8254 is an upgraded version of 8253 and they are pincompatible

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SPECIFICATIONS
Compatible with All Intel and Most other Microprocessors Handles Inputs from DC to 2 MHz 8 MHz 8254 10 MHz 8254-2 8254 includes Status Read-Back Command that can latch the count and the status of the counters. Single 5V Supply

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BLOCK DIAGRAM OF 8254

Three counters (0,1 and2) Data Bus buffer Read/Write control logic Control Register Each counter has two input signals clock(CLK) and GATE and one output signal OUT.

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CLK 0
8 Data Bus Buffer Counter =0

GATE

OUT 0 OUT 0

Internal Bus
RD WR A0 A1
Read/Write Logic Counter =1

CLK 1 GATE 1 OUT 1

OUT 1

CS
Control Word Register
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CLK 2 GATE 2 GATE 2 Counter

=2

OUT 2

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DATA BUS BUFFER:

This 3-state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus.

READ/WRITE CONTROL LOGIC :

The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 8254. A1and A0 select one of the three counters or the Control Word Register to be read from/written into. The control section has five signals: RD(Read),WR(Write), CS(Chip Select), and address lines A1and A0
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In peripheral I/O mode, the RD & WR signals are connected to IOR and IOW respectively In memory mapped I/O, these are connected to MEMR(Memory Read) and MEMW (Memory Write) Address lines A1and A0 of the MPU are usually connected to A1and A0 lines of the 8254, & CS is tied to a decoded address Control word register and counters are selected according to the signals on lines A1and A0 as shown
A1 0 0 1 1
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A0 0 1 0 1

Selection Counter 0 Counter 1 Counter 2 Control Register

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Control Word Register

This register is accessed when lines A1and A0 are at logic 1. It is used tow rite a command word which specifies the counter to be used, its mode and either a Read or Write operation

Mode
8254 can operate in 6 different modes, and the gate of a counter is used either to disable or enable counting

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D7 SC1 SC1 0 0 1 1 SC0 0 1 0 1

D6 SC0

D5 RW1

D4 RW0

D3 M2 M2

D2 M1 M1 0 0 1 1 0 0 M0 0 1 0 1 0 1

D1 M0

D0 BCD

Select Counter 0 Select Counter 1 Select Counter 2 Read-Back command

0 0 X X 1 1

Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5

RW1 0 0 1 1

RW0 0 1 0 1 Counter Latch Command Read/Write least significant byte Read/Write most significant byte Read/Write least significant byte first and then most significant byte

BCD: 0 1 Binary Counter Binary Coded Decimal

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Programming the 8254

8254 can be programmed to provide various types of output through Write operations or to check a count while counting through Read operations.

Write Operation
Write a control word into the control register Load the low-order byte of a count in the counter register Load the high-order byte of a count in the counter register With a clock and an appropriate gate signal to one of the counters, the above steps should start the counter and provide appropriate output according to the control word
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Read Operations
In some applications, especially in event counters it is necessary to read the value of the count in progress. Reading a count after inhibiting the counter to be read Counting is stopped by controlling the gate input or the clock input of the selected counter and the two I/O read operations are performed by the MPU. The first I/O operation reads the low-order byte and the second I/O operation reads the high-order byte. Reading a count while the count is in progress An appropriate control word is written into the control register to latch a count in the output latch, and two I/O Read operations are performed by the MPU.
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Gate Settings of a Counter

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MODE 0 : Interrupt on Terminal Count

In this mode, initially the OUT is low. Once the count Is loaded in the register, the counter is decremented every cycle and when the count reaches zero, the OUT goes high. This can be used as an interrupt The OUT remains high until a new count or a command word is loaded.

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INTERRUPT ON TERMINAL COUNT

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MODE 1: Hardware Retriggerable One-Shot

In this mode, the OUT is initially high When the Gate is triggered, the OUT goes low, and at the end of the count, the OUT goes high again, thus generating a one-shot pulse

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Hardware Retrigger able One-Shot

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MODE 2 : Rate Generator

This mode is used to generate a pulse equal to the clock period at a given interval. When a count is loaded, the OUT stays high until the count reaches 1, and then the OUT goes low for one clock period The count is reloaded automatically, and the pulse is generated continuously. The count = 1 is illegal in this mode.

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RATE GENERATOR

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MODE 3: Square-Wave Generator

In this mode, when a count is loaded, the OUT is high. The count is decremented by two at every clock cycle, and when it reaches zero, the OUT goes low, and the count is reloaded again. This is repeated continuously; thus a continuous square wave with period equal to the period of the count is generated
The frequency of the square wave is equal to the frequency of the clock divided by the count
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Square-Wave Generator

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MODE 4: Software Triggered Strobe

In this mode, the OUT is initially high; it goes low for one clock period at the end of the count. The count must be reloaded for subsequent outputs.

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Software Triggered Strobe

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MODE 5:Hardware Triggered Strobe

Thus mode is similar to Mode 4, except that it is triggered by the rising pulse at the gate Initially, the OUT is low, and when the Gate pulse is triggered from low to high, the count begins. At the end of the count, the OUT goes low for one clock period.
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Hardware Triggered Strobe

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READ BACK COMMAND FORMAT

The read back command allows the user to read the count and the status of the counter
D7 D6 D5 D4 D3 D2 D1 D0

COUNT

STATUS

CNT 2

CNT 1

CNT 0

D5 =Latch Count of Selected Counter(s) D4 =Latch Count of Selected Counter(s) D3 =Select Counter 2 D2 =Select Counter 1 D1 =Select Counter 0

A0,A1 =11 CS = 0 RD = 1 WR = 0

D0 =Reserved for Future Expansion; Must be 0

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The command is written in the control register, and the count of the specified counter can be latched if COUNT(bit D5 is 0) A counter or a combination of counters is specified by keeping the respective CNT bits (D1,D2, and D3)high For example the control word 1 1 0 1 0 1 1 0(D6H) written in the control register will latch the counts of Counter 0 and Counter 1, and these counts can be obtained by reading respective counter port addresses. The latched counts are held until they are read or the counters are reprogrammed.

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STATUS BYTE
The status of the counter can be read if STATUS bit (D4) of the Read Back Command Is low
D7
OUTPUT

D6
NULL COUNT

D5
RW1

D4
RW0

D3 D2
M2

D1
M1

D0
M0 BCD

D7:1 = Out Pin is 1 :0 = Out Pin is 0 D6:1 = Null Count :0 = Count Available for Reading D5 D0 = Counter Programmed Mode

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References
Microprocessor Architecture, Programming and Applications Ramesh Gaonkar Intel 8255 datasheet www.DatasheetCatalog.com PPT by Dr. Khurram Waheed San Diego State University

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Introduction
8259 Programmable interrupt controller can
Manage eight interrupts according to the instructions written into its control registers Vector an interrupt request anywhere in the memory map.(Eight interrupts are spaced at the interval of either 4 or 8 memory locations. Resolve 8 levels of interrupt priorities in a variety of modes, such as fully nested mode, automatic rotation mode & specific rotation mode Mask each interrupt request individually Read the status of pending interrupts, in-service interrupts & masked interrupts

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Introduction(cont.)
Be set up to accept either the level-triggered or the edge-triggered interrupt request Be expanded to 64 priority levels by cascading additional 8259As Be set up to work with either the 8085 microprocessor mode or the 8086/8088 microprocessor mode.

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PIN CONFIGURATION

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PIN DETAILS
D0-D7 Bi-directional, tristated, buffered data lines. Connected to data bus directly or through buffers RD-bar Active low read control WR-bar Active low write control A0 Address input line, used to select control register CS-bar Active low chip select CAS0-2 Bi-directional, 3 bit cascade lines. In master mode, PIC places slave ID no. on these lines. In slave mode, the PIC reads slave ID no. from master on these lines. It may be regarded as slave-select.

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PIN DETAILS(cont.)
SP-bar / EN-bar Slave program / enable. In non-buffered mode, it is SP-bar input, used to distinguish master/slave PIC. In buffered mode, it is output line used to enable buffers INT Interrupt line, connected to INTR of microprocessor INTA-bar Interrupt ack, received active low from microprocessor IR0-7 Asynchronous IRQ input lines, generated by peripherals.

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Architecture of 8259
It includes 8 blocks Control Logic Read/Write logic Data bus buffer Three registers(IRR,ISR,IMR) Priority Resolver and Cascade Buffer

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Block diagram

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INTA

INT

D7 D0
Data Bus Buffer Control Register

RD WR A0

Read/ Write Logic

In Service Register ISR

Priority Resolver

Interrupt Request Register

IRR CS

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

CAS0 CAS1 CAS2

Cascade Buffer/ Comparator

Interrupt Mask Register IMR

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Block diagram(cont.)
CONTROL LOGIC Has two pins INT as an output, & INTA as an input INT pin is connected to the interrupt pin of MPU. Whenever a valid interrupt is asserted, this signal goes high. INTA is the interrupt acknowledge signal from MPU

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Block diagram(cont.)
READ/WRITE LOGIC
When the address line A0 is at logic 0, the controller is selected to write a command or read a status Chip Select logic and A0 determine the port address of the controller

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Block diagram(cont.)
DATA BUS BUFFER
This 3-state, bidirectional 8-bit buffer is used to interface the 82C59A to the System Data Bus. Control words and status information are transferred through the Data Bus Buffer.

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Block diagram(cont.)
INTERRUPT REGISTERS & PRIORITY RESOLVER Interrupt Request Register (IRR) has 8 input lines (IR0 IR7) for interrupt When these lines go high, the requests are stored in the register. In-Service Register (ISR) stores all the levels that are currently being serviced Interrupt Mask Register (IMR) stores the masking bits of the interrupt lines to be masked. Priority Resolver(PR)examines these 3 registers and determine whether INT should be sent to MPU
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Block diagram(cont.)
CASCADE BUFFER/COMPARATOR
Expands the number of interrupt levels by cascading two or more 8259As

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Interfacing with 8085

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INTERRUPT OPERATION
To enable interrupts the Interrupt Enable flip-flop in the P should be enabled by writing the EI instruction & 8259A should be initialized by writing control words in control register Two types of control words Initialization Command Words(ICWs) Operational Command Words(OCWs) ICWs are used to set up the proper conditions & specify RST vector addresses OCWs are used to perform functions such as masking interrupts, setting up status-read operations etc.
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INTERRUPT OPERATION
(Sequence of Events) The IRR stores the requests The priority resolver checks 3 registers: IRR for interrupt requests IMR for masking bits ISR for serving the interrupt request It resolves the priority & sets the INT high when appropriate o MPU acknowledges the interrupt by sending INTA o After receiving the INTA, the appropriate bit in the ISR is set to indicate which interrupt level is being served and the corresponding bit in the IRR is reset to indicate that the request is accepted. The opcode for CALL instruction is placed on data bus
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Sequence of Events(CONT.)
When the MPU decodes the CALL instruction, it places two more INTA signals on the data bus When the 8259A receives the 2nd INTA, it places the low-order byte of the CALL address on data bus At 3rd INTA it places the higher order byte on the data bus The CALL address is the vector memory location for the interrupt & it is placed in the control register during initialization o During the 3rd INTA pulse , the ISR bit is reset either automatically(Automatic-End-of-Interrupt--AEOI) or by a command word that must be issued at the end of the service routine(End-of- Interrupt-EOI) o Program sequence is transferred to the memory location specified by CALL instruction
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PRIORITY MODES
1. Fully Nested Mode: General purpose mode All IRs are arranged from highest to lowest (IR0 highest & IR7 lowest) In addition any IR can be assigned highest priority & priority sequence will begin at that IR. Ex.
IR0 4 IR1 5 IR2 6 IR3 7 IR4 0 IR5 1 IR6 2 IR7 3

Lowest Priority
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Highest Priority

PRIORITY MODES(CONT.)
AUTOMATIC ROTATION MODE A device after being serviced, receives the lowest priority Ex. Assuming that IR2 has just been services, it will receive the seventh priority as shown
IR0 5 IR1 6 IR2 7 IR3 0 IR4 1 IR5 2 IR6 3 IR7 4

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PRIORITY MODES(CONT.)
SPECIFIC ROTATION MODE
This mode is similar to the automatic rotation mode, except that the user can select any IR for the lowest priority, thus fixing all other priorities.

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END OF INTERRUPT
After the completion of an interrupt service, the corresponding ISR bit needs to be reset to update the information in the ISR Three formats Nonspecific EOI Command: When this command is sent to the 8259A, it resets the highest priority ISR bit Specific EOI Command: This command specifies which ISR bit to reset. Automatic EOI: In this mode no command is necessary. During 3rd INTA the ISR bit is reset.

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PROGRAMMING THE 8259A

8259A Requires 2 types of command words: Initialization command words Operational command words The ICW1 specifies Single or multiple 8259As in the system 4 or 8 bit interval between the interrupt vector locations Address bits A7 A5 of the CALL location; the rest are supplied by 8259A

A7 0
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A6 1

A5 1

A4 0

A3 0

A2 0

A1 0

A0 0

= 60 H

PROGRAMMING THE 8259A(cont.)

The address bits A4 A0 are supplied by the 8259A. The subsequent addresses are four locations apart The port address of the 8259A for ICW1 is 80H; A0 should be at logic 0, & the other bits are determined by the decoder Command word ICW2 is 20H, which specifies the high order byte of the Call address The port address of ICW2 is 81H;A0 should be at logic 1

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ICW1
A0 0 D7 A7 D6 A6 D5 A5 D4 1 D3 LTIM D2 ADI D1 SNGL D0 IC4
1 ICW4 needed 0 Not needed 1 Single 0 Cascade Mode

Call Address Interval 1 Interval of 4 0 Interval of 8

A7 A5 of Interrupt Vector Address

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1 = Level triggered mode 0 = Edge-triggered mode

ICW2
A0 1 D7 A15 D6 A14 D5 A13 D4 A12 D3 A11 D2 A10 D1 A9 D0 A8

A15 A8 of Interrupt Vector Address

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A programmable keyboard and display interfacing chip. Scans and encodes up to a 64-key keyboard. Controls up to a 16-digit numerical display. Keyboard section has a built-in FIFO 8 character buffer. The display is controlled from an internal 16x8 RAM that stores the coded display information.

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PIN DESCRIPTION
A0: Selects data (0) or control/status (1) for reads and writes between micro and 8279. BD: Output that blanks the displays. CLK: Used internally for timing. Max is 3 MHz. CN/ST: Control/strobe, connected to the control key on the keyboard. CS: Chip select that enables programming, reading the keyboard, etc. DB7-DB0: Consists of bidirectional pins that connect to data bus on micro.
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PIN DESCRIPTION(cont.)
IRQ: Interrupt request, becomes 1 when a key is pressed, data is available. OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least significant nibble of display. RD(WR): Connects to micro's IORC or RD signal, reads data/status registers. RESET: Connects to system RESET. RL7-RL0: Return lines are inputs used to sense key depression in the keyboard matrix. Shift: Shift connects to Shift key on keyboard. SL3-SL0: Scan line outputs scan both the keyboard and displays.
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Four major sections of 8279 Keyboard Scan Display MPU interface

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CLK RESET DB0 DB7 RD WR CS A0 IRQ

Data Buffers

I/O Control

FIFO / Sensor RAM Status

Display Address Registers 16x8 Display RAM

INTERNAL DATA BUS(8)

8x8 FIFO/ Sensor RAM

Control & Timing Registers

Keyboard Debounce & Control

Display Registers
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OUT A0 A3 OUT B0 B3

TIMING & CONTROL

SCAN COUNTER

Return

BD

SL0 SL

RL0 RL7 SHIFT CNTL/STB

KEYBOARD SECTION

Has 8 lines(RL0 RL7) which can be connected to 8 columns of a keyboard, + 2 additional lines: Shift & CNTL/STB(Control/Strobe) Status of the SHIFT key and the control key can be stored along with a key closure The keys are automatically debounced, & the keyboard can operate in two modes Two-key lockout N key rollover In two key lockout mode, if two keys are pressed almost simultaneously, only the 1st key is recognized
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KEYBOARD SECTION(CONT.)
N key rollover mode, simultaneous keys are recognized & their codes are stored in internal buffer Also includes 8 x 8 FIFO RAM FIFO consists of 8 registers that can store 8 keyboard entries that can be read in the order of entries. The status logic keep track of the number of entries & provides an IRQ(Interrupt Request) signal when the FIFO is not empty. The status logic keep track of the number of entries & provides an IRQ(Interrupt Request) signal when the FIFO is not empty

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SCAN SECTION
Has a scan counter & 4 scan lines(SL0 - SL3) These 4 scan lines are decoded using 4 to 16 decoder to generate 16 lines for scanning These lines can be connected to the rows of a matrix keyboard & the digit drivers of a multiplexed display

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DISPLAY SECTION
Has 8 output lines divided into 2 groups A0 A7 & B0 B7 These lines can be used either as a group of 8 lines or as 2 groups of 4 in conjunction with the scan lines for a multiplexed display The display can be blanked by using the BD line Includes 16 x 8 display RAM MPU can read from or write into any of these registers

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MPU INTERFACE SECTION

Includes 8 bidirectional data lines(DB0 DB7) 1 Interrupt Request line(IRQ) 6 lines for interfacing which includes the buffer address line(A0) When A0 is high, signals are interpreted as control words or status When A0 is low signals are interpreted as data. The IRQ line goes high whenever data entries are stored In FIFO This signal is used to interrupt MPU to indicate availability of data
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USART (Universal Synchronous/Asynchronous Receiver/Transmitter) INTEL 8251

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FEATURES OF 8251A(USART)
8251A is an universal synchronous & asynchronous communication controller supports standard asynchronous protocol with 5 to 8 bit character format Odd, even or no parity generation & detection Baud rate from DC to 19.2kbaud False rate bit detection Automatic break detect and handling

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FEATURES OF 8251A(USART)(cont.)
Has built in baud rate generator Supports standard synchronous protocol with 5 to 8 bit character format Internal or external character synchronization Automatic sync insertion Baud rate from dc to 64kbaud Allows full duplex transmission & reception

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FEATURES OF 8251A (USART)(cont.)

Provides double buffering of data both in transmission section & in receiver section Provides error detection logic, which detects parity, overrun & framing errors Has modern control logic, which supports basic data set control signals Provides separate clock inputs for receiver & transmitter sections thus providing an option of fixing different baud rates for transmitter & receiver section

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PIN DIAGRAM OF 8251A

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PIN DETAILS OF 8251A(cont.)

D 0 to D 7 (l/O terminal) This is bidirectional data bus which receive control words and transmits data from the CPU and sends status words and received data to CPU. RESET (Input terminal) A "High" on this input forces the 8251 into idle mode. The device will remain until a new set of control words is written into the 8251A to program its functional definition.

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PIN DETAILS OF 8251A(cont.)

CLK (Input terminal) CLK signal is used to generate internal device timing. The frequency of CLK must be greater than 30 times the RXC and TXC

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PIN DETAILS OF 8251A(cont.)

WR (Input terminal) This is the "active low" input terminal which receives a signal for writing transmit data and control words from the CPU into the 8251. RD (Input terminal) This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251.

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PIN DETAILS OF 8251A(cont.)

C/D (Input terminal) This is an input terminal which receives a signal for selecting data or command words and status words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed.

C/D 0 0 1 1
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RD 0 1 0 1 1

WR 1 0 1 0 1

Operation CPU reads data from USART CPU sends data to USART CPU reads status from USART CPU writes command to USART USART Bus timing

PIN DETAILS OF 8251A(cont.)

CS (Input terminal) This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses. TXD (output terminal) This is an output terminal for transmitting data from which serial-converted data is sent out.

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PIN DETAILS OF 8251A(cont)

TXRDY (output terminal) This is an output signal which indicates that the 8251 is ready to accept a transmitted data character. TXEMPTY (Output terminal) This is an output terminal which indicates that the 8251 has transmitted all the characters and had no data character

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PIN DETAILS OF 8251A(cont.)

TXC (Input terminal) This is a clock input signal which determines the transfer speed of transmitted data. RXD (input terminal) This is a terminal which receives serial data. RXRDY (Output terminal) This is a terminal which indicates that the 8251 contains a character that is ready to READ. If the CPU reads a data character, RXRDY will be reset by the leading edge of RD signal.

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PIN DETAILS OF 8251A(cont.)

RXC (Input terminal) This is a clock input signal which determines the transfer speed of received data. In "synchronous mode," the baud rate is the same as the frequency of RXC. In "asynchronous mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC

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PIN DETAILS OF 8251A(cont.)

SYNDET/BD (Input or output terminal) This pin is used in synchronous mode for detection of synchronous characters and may be used as either input or output. In asynchronous mode this pin goes high if receiver line stays low for more than 2 character times. If then indicates a break in the data stream. When used as an input a positive signal will cause the 8251A to start receiving data characters on the rissing edge of the next RxC

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PIN DETAILS OF 8251A(cont.)

DSR (Input terminal) This is an input port for MODEM interface. The input status of the terminal can be recognized by the CPU reading status words. DTR (Output terminal) This is an output port for MODEM interface. It is possible to set the status of DTR by a command.

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PIN DETAILS OF 8251A(cont.)

CTS (Input terminal) This is an input terminal for MODEM interface which is used for controlling a transmit circuit. The terminal controls data transmission if the device is set in "TX Enable" status by a command. Data is transmitable if the terminal is at low level. RTS (Output terminal) This is an output port for MODEM interface. It is possible to set the status RTS by a command.

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BLOCK DIAGRAM (cont.)

Data Bus Buffer: Tri state, bidirectional, 8 bit buffer is used to interface 8251 to the system data bus. Along with the data, control word, command words and status information are also transferred through the Data bus buffer

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BLOCK DIAGRAM(cont.)
Read/Write control logic: The functional block accepts inputs from the system control bus and generates control signals for overall device operation. It decodes control signals on the 8085 control bus into signals which controls the internal and external I/O bus. It contains the control word register and command word register that stores the various control formats for the device functional definition.

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BLOCK DIAGRAM(cont.)
Transmit Buffer The transmit buffer accepts parallel data from the CPU adds the appropriate framing information, serializes it, and transmits it on the TxD pin the falling edge of TxC Has two registers Buffer register to hold 8 bits & an output register to convert 8 bits into a stream of serial bits. The CPU writes a byte in the buffer register, which is transferred to the output register when it is empty. The output register then transmits serial data on the TxD pin
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BLOCK DIAGRAM(cont.)
In the asynchronous mode the transmitter always adds START bit; depending on how the init is programmed, it also adds an optional even or odd parity bit, and either 1, 11/2 or 2 STOP bits. In synchronous mode no extra bits (other than parity, if enable) are generated by the transmitter.

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BLOCK DIAGRAM (cont.)

TRANSMIT CONTROL
It manages all activities associated with the transmission of serial data. It accepts and issues signals both externally and internally to accomplish this function TxRDY (Transmit Ready) This output signal indicates CPU that buffer register is empty and the USART is ready to accept a data character. It can be used as an interrupt to the system or for polled operation The CPU can check TxRDY using the status read operation.

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Block diagram (cont.)

TRANSMIT CONTROL
This signal is reset when a data byte is loaded into the buffer register. TxE(Transmitter Empty): This is an output signal. A high on this line indicates that the output buffer is empty. In the synchronous mode, if the CPU has failed to load a new character in time, TxE will go high momentarily as SYNC characters are loaded into the transmitter to fill the gap in transmission.

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BLOCK DIAGRAM(cont.)
TRANSMIT CONTROL
TxC(Transmitter Clock) This clock controls the rate at which characters are transmitted by USART. In the synchronous mode TxC is equivalent to the baud rate, and is supplied by the modem. In asynchronous mode TxC is equivalent to the baud rate,, and is supplied by the modem. In asynchronous mode TxC is 1,16, or 64 times the baud rate. The clock division is programmable. It can be programmed by writing proper mode word in the mode set register.

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BLOCK DIAGRAM(cont.)
TRANSMIT CONTROL
Receiver Buffer: The receiver accepts serial data on the RxD line, converts this serial data to parallel format, checks for bits or characters that are unique to the communication technique and sends an assembled character to the CPU When 8251 is in the asynchronous mode and it is ready to accept a character, it looks for a low level on the RxD line. When it receives the low level, it assumes that it is a START bit and enables an internal counter.

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BLOCK DIAGRAM(cont.)
TRANSMIT CONTROL
At a count equivalent to one-half of a bit time, the RxD line is sampled again. If the line is still low, a valid START bit is detected & the 8251A proceeds to assemble the character. After successful reception of a START bit the 8251A receives data, parity & STOP bits, and then transfers the data on the receiver input register. The data is then transferred into the receiver buffer register. In synchronous mode the receiver simply receives the specified no. of data bits & transfers them to the receiver input register & then to the receiver buffer register.
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BLOCK DIAGRAM(cont.)
RECEIVER CONTROL
It manages all receiver-related activities. Along with data reception, it dos false start bit detection, parity error detection, framing error detection, sync detection & break detection. RxRDY(Receiver Ready): This is an output signal. It goes high when the USART has a character in the buffer register and is ready to transfer it to the CPU.

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BLOCK DIAGRAM(cont.)
RECEIVER CONTROL
This line can be used either to indicate the status in the status register or to interrupt the CPU. This signal is reset when a data byte from receiver buffer is read by the CPU. RxC(Receiver Clock): This clock controls the rate at which the character is to be received by USART in the synchronous mode. RxC is equivalent to the baud rate, and is supplied by the modem.

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BLOCK DIAGRAM(cont.)
RECEIVER CONTROL

In asynchronous mode RxC is 1,16 or 64 times the baud rate. The clock division is programmable. It can be programmed by writing proper mode word in the mode set register.

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BLOCK DIAGRAM(cont.)
MODEM CONTROL
It provides control circuitry for the generation of RTS & DTR and the reception of CTS and DSR. In addition, a general purpose inverted output & a general purpose input are provided. The output is labeled DTR and the input is labeled DSR. DTR can be asserted by setting bit 2 of the command instruction; DSR can be sensed as bit 7 of the status register. When used as a modem control signal DTR indicates that the terminal is ready to communicate and DSR indicates that it is ready for communication

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Programming 8251 Mode Instruction Foramt

8251 mode register

D7

D6

D5

D4

D3

D2

D1

D0

Mode register

Number of Stop bits 00: 01: 10: 11: invalid 1 bit 1.5 bits 2 bits

Parity Control 0: disable 1: enable Character length 00: 01: 10: 11: 5 bits 6 bits 7 bits 8 bits

Baud Rate Factor 00: Syn. Mode 01: Async x 1 10: Async x 16 11: Async x 64

Parity 0: odd 1: even

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Programming 8251
8251 command register

EH

IR

RTS

ER

SBRK

RxE

DTR

TxE

command register

TxE: transmit enable DTR: data terminal ready RxE: receiver enable SBPRK: send break character ER: error reset RTS: request to send IR: internal reset EH: enter hunt mode
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1=Enable 0 = Disable 1= Enable DTR 1=Enable 0=Disable 1=Forces TxD low 0=Normal Operation 1=Reset error flags (PE.OE.FE) 1=Enable RTS 1=Resets 8251 to mode 1=Enable search for synch characters

Programming 8251
8251 status register

DSR

SYNDET

FE

OE

PE

TxEMPTY RxRDY TxRDY

status register

TxRDY: RxRDY: TxEMPTY: PE: OE: FE: SYNDET: DSR:

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transmit ready receiver ready transmitter empty parity error overrun error framing error sync. character detected data set ready

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Serial Data Transfer

Asynchronous vs.. Synchronous
Asynchronous transfer does not require clock signal. However, it transfers extra bits
(start bits and stop bits) during data communication Synchronous transfer does not transfer extra bits. However, it requires clock signal Frame Asynchronous Data transfer data Start bit B0 B1 B2 B3 B4 B5 B6 Stop bits Parity

Synchronous Data transfer

clk

data B0
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B1

B2

B3

B4

B5

Summary
8255 PPI 8254 PIT 8259 PIC 8279 Keyboard/Display Interface 8251 USART

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