Computer Organization Jan 2014
Uploaded by
Prasad C MComputer Organization Jan 2014
Uploaded by
Prasad C MUSN
06cs46
Fourth Semester B.E. Degree Examination, Dec. 20l3/Jan.2OL4
Gomputer Organization
Time: 3 hrs. Max. Marks:100
Note: Answer FIYEfull questions, selecting
utlesst TWO questions
from
each part.
PART
-
A ,''',,,.,"""'
I a.
,,
*t n a general block diagram, explain the functions of each of the processor ret*o?[i
*r*,
b. Highlighting important technological features and advances, explain
:"the
evolution of
computer over different generations.
(08 Marks)
c. With suitable example, explain how performance is measured using SPEC rating and give its
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2 a. Convert the followjng pair of decimal numbers into 5 bft singed 2's complement binary
numbers and perform operations indicated. Also state if overflow occurs.
i)
-
10 and
-_
13 (additio.n) ii)
-
14 and 11 (subtraction) iiD
-
3 and
-
8 (addition)
iv)
-
10and
-
13
(subtraction)
.
.:,,
(08 Marks)
b. Given the following instrtrotion, rewrite using only,difect, indirect and immediate addressing
significanCe.
memory ohips.
Explain the working of a dynamic memory cell.
PARr-B
""i".."6tS;:
(04 Marks)
(05 Marks)
(07 Marks)
(06 Marks)
(08 Marks)
(10 Marks)
modes to achieve the same effest : move 123 (Rr, R
),
(&,
&).
c. What is a stack frame? Explain its use in subroutines.
3 a. What is an interrupt? Explain its ;oncepts and the hardware used to realize it. (06 Marks)
b. What is the necessity of DMA? Explain the two modes in which DMA interface operates to
transfer data.
,
'
c. Explain the bus arbitration approaches with thoihelp of neat sketches.
4 a. Explain the combined input/output interface circuit, with help of a neat logic block diagram.
b. With respect to USB, di;;;r the USB architecture, addressing and protocol adopted.
'
:'':' ':: ffi
:E
>\(10
Marks)
5a. With a block diagram, explain the organization of 8 M x 32{iffiSfflgSpg
{f2fiK
x 8 ;lr2ix
tpl:*
.I05
M
(08 Nlarks)
(08 Marks)
(04 Marks) ,,
b.
c.
d.
What is memory interleaving? Explain.
\aS$S
{Gp---(on
uarrrs)
- - J -- ---e- r
-_
Calculate the average access time experienced by a processor if cache hit rate is
0.88,
miss
penalty is 0.015 milliseconds and cache access time is 10 micros seconds. "".
{{4
Marks)
Explain how virtual memory addres-s translation based on fixed - length pages is organized
and achieved.
Explain the design of a 4
-
bit carry
-
lookahead adder.
Write a note on optical technology used in CD systems.
(10 Marks)
(10 Marks)
6',, a.
b.
c.
7a.
b.
8a.
Draw the circuit diagram for binary division. Explain the non
-
restoring division algorithm,
with suitable example.
Explain the IEEE standard for floating point number representation.
Mention and explain the control sequences for execution of an unconditional branch
instruction. (10 Marks)
b. With a block diagram, explain the basic organization of a micro-programmed control unit.
(10 Marks)
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