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Mosfet Transistor Equations: University of Edinburgh EE4 Electrical Engineering

The document contains information about MOSFET transistor equations, small signal parameters, noise equations, physical constants, MOSFET capacitances, a generic CMOS process parameters, SPICE syntax and models. It provides the key electrical characteristics, parameters and equations for modeling and simulating MOS transistors and basic CMOS circuits.

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Shachi P Gowda
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0% found this document useful (0 votes)
73 views5 pages

Mosfet Transistor Equations: University of Edinburgh EE4 Electrical Engineering

The document contains information about MOSFET transistor equations, small signal parameters, noise equations, physical constants, MOSFET capacitances, a generic CMOS process parameters, SPICE syntax and models. It provides the key electrical characteristics, parameters and equations for modeling and simulating MOS transistors and basic CMOS circuits.

Uploaded by

Shachi P Gowda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

University of Edinburgh

EE4
LSI Circuits

Electrical Engineering

MOSFET TRANSISTOR EQUATIONS


n-type V DS K' W I D = --------- V GS V t -------- V ( 1 + V DS ) L 2 DS K' W I D = --------- ( V V t ) 2 ( 1 + V DS ) 2 L GS V t = V t 0 + ( ( V BS ) ) p-type V DS K' W I D = --------- V GS V t -------- V ( 1 V DS ) L 2 DS K' W I D = --------- ( V V t ) 2 ( 1 V DS ) 2 L GS V t = V t 0 ( ( + V BS ) ) both (in saturation) 2 ID W ---- -------------------------------L K' ( V GS V t ) 2 V GS 2 ID L V t + ----------K' W n type V GS 2 ID L V t ----------K' W p type linear saturation 0 > VDS > VGS - Vt VDS < VGS - Vt VGS < Vt VGS < Vt linear saturation 0 < VDS < VGS - Vt VDS > VGS - Vt VGS > Vt VGS > Vt

Small signal parameters of MOSFETs in Saturation - assuming | VDS | << 1


nMOS Transconductance g m = ( V GS V t ) ( 1 + V DS ) 2 ID g m 2 I D ---------------------V GS V t Bulk transconductance gm g mb = ---------------------------2 V BS 2 g ds = ------ ( V GS V t ) 2 g ds I D pMOS g m = ( V GS V t ) ( 1 V DS ) gm 2 ID gm g mb = ---------------------------2 + V BS 2 g ds = ------ ( V GS V t ) 2 g ds I D

Drain conductance

Other Useful Equations


K = 0 C OX n = 2 ( kT q ) ln ( N D n i )
18 September 1994
Modified 1/12/08

= K(W L) p = 2 ( kT q ) ln ( n i N A )
D. Renshaw

C OX = OX t OX = ( 2 Si qN ) C OX

VE = 1 ( L )

page 1 of 5

[email protected]:\D430dar2oo8-9\ee3\Part2\src\MOSData-2.fm

University of Edinburgh

EE4
LSI Circuits

Electrical Engineering

NOISE, PHYSICAL CONSTANTS & MOS CAPACITANCE


Noise Equations
4 kT S iR = -------R 8 kTg m ( 1 + ) S iRS = --------------------------------3 S if
AF K F I DQ = ---------------fC ox L 2

thermal thermal 1/f noise

ohmic saturation both where g mb = -------gm

Miscellaneous Physical Constants & Other Process Information


Symbol q k 0 Si ox Eg Value 1.610-19 1.3810-23 8.8510-12 11.70 3.90 1.16 Units coulombs joule/Kelvin farad/meter farad/meter farad/meter Volts Tnom ni Nsub_n Nsub_p AF KF Symbol 27 1.451010 91015 71015 1 10-28 farad*amps Value C cm-3 cm-3 cm-3 Units

MOSFET Capacitances (where : Leff = L - 2LD )


Region Cut-off
CGC CGD CGS CBG CBD CBS 0 CoxWLD CoxWLD CoxWLeff AD Cj + PDCjSW AS Cj + PSCjSW

Saturation
CoxWLeff CoxWLD CoxW(LD + 2Leff / 3) 0 AD Cj + PDCjSW AS Cj + PSCjSW + 2WLeff Cj / 3

Ohmic
CoxWLeff CoxW(LD + Leff / 2) CoxW(LD + Leff / 2) 0 AD Cj + PDCjSW + WLeff Cj / 2 AS Cj + PSCjSW + WLeff Cj / 2

where

Cj0 C j = C j ( V ) = -------------------------n (1 V )

V = V BD or V = V BS or V = V BC

1 1 and n = -- -3 2

18 September 1994
Modified 1/12/08

D. Renshaw
[email protected]:\D430dar2oo8-9\ee3\Part2\src\MOSData-2.fm

page 2 of 5

University of Edinburgh

EE4
LSI Circuits

Electrical Engineering

GENERIC CMOS PROCESS - Electrical Characteristics


Transistor Characteristics
Parameter Vt0 Transistor n p K n p Value +1.0 -1.0 35 14 0.8 0.7 0.01 0.02 0.7 0.6 500 200 4 (8) 8 (4)

20%
Units V V

Interlayer Capacitances
Layers poly-diff gateoverlap capacitance poly-subs diff-subs Value 0.7 0.3 0.02 0.2 0.4 diff-subs in well M2 - subs M2 - diff M2 - poly M2 - M1 M1 - subs M1 - diff M1 - poly well 0.3 0.5 0.02 0.03 0.03 0.05 0.02 0.04 0.04 0.2 1.6 Units fF/(m)2 fF/(m) fF/(m)2 fF/(m)2 fF/(m) fF/(m)2 fF/(m) fF/(m)2 fF/(m)2 fF/(m)2 fF/(m)2 fF/(m)2 fF/(m)2 fF/(m)2 fF/(m)2 fF/(m)

20%
Comment gate oxide gate-source gate-drain

A/V2 A/V2
V1/2 V1/2 V-1 V-1 V V cm2/(V.s) cm2/(V.s) V/m V/m

0 VE

n p n p n p n p n p

area (Cj) perimeter (CjSW) area (Cj) perimeter (CjSW)

(L10m)

Operating Voltage = 5 Volts ; n-well , p-well processes

area (Cj) perimeter (CjSW)

Sheet & Contact Resistances


diff in well diff poly M1 M2 well M2-M1 M1 - poly M1 - diff substrate 40 80 25 0.005 0.005 5000 1 10 5 25

20%

/sq. /sq. /sq. /sq. /sq. /sq. /via /contact /contact /sq.
2m2m 2m2m 2m2m bulk Si

Maximum current densities


poly M2 M1 M2 - M1 M1 - poly M1 - diff 40 1 1 40 1 1

A/m
mA/m mA/m

A/via
mA/contact mA/contact

2m2m 2m2m 2m2m per bond

bond wire inductance

7.5

nH

18 September 1994
Modified 1/12/08

D. Renshaw
[email protected]:\D430dar2oo8-9\ee3\Part2\src\MOSData-2.fm

page 3 of 5

University of Edinburgh

EE4
LSI Circuits

Electrical Engineering

SUMMARY OF SPICE SYNTAX & MODELS


Abbreviated List of Syntax
Rxxx n1 n2 Rval <TC=tcval> Cxxx n1 n2 Cval <IC=icval> Lxxx n1 n2 Lval <IC=icval> Vxxx n+ n- <DC=dcval> + <AC=acmag, acphase> Ixxx n+ n- <DC=dcval> +<AC=acmag, acphase> Dxxx n+ n- mname <area> Qxxx nc nb ne ns mname <area> Jxxx nd ng nb mname <area> Mxxx nd ng ns nb mname L=Lval W=wval + <AD=adval> <AS=asval> + <PD=pdval> <PS=psval> Exxx n+ n- <VCVS> cin+ cin- gain Fxxx n+ n- <CCCS> vname gain Gxxx n+ n- <VCCS> cin+ cin- transcon Hxxx n+ n- <CCVS> vname transres .SUBCKT subname n1 <n2 n3 ... > + <param=val1 val2 ... > .ENDS <subname> Xyyy n1 <n2 n3 ... > subname <param=val1 val2 ... > + <M=val> PULSE(v1 v2 td tr pw per) SIN(vo va freq td theta) PWL(t1 v1 <t2 v2 ... >) * comment .ALTER .AC type nopts fstart fstop .DATA dataname pname1 <pname2 ... > .DC srcnam vstart vstop vincr .DEL LIB <filepath>filename entryname .DISTO rload .END .FOUR freq ov1 <ov2 ... > .GLOBAL node1 <node2 ... > .GRAPH .IC V(nodnam1)=val <V(nodnam2)=val ... > .INCLUDE <filepath>filename .LIB <filepath>filename entryname .MEASURE .MODEL mname TYPE <Pname1=pval1 ... > .NOISE outv insrc nums .OP <format> <time> .OPTIONS opt1 <opt2 ... > .PARAM paramnam1=val1 <parmnam2=val2 ... > .PLOT pltype ov1 <ov2 ... > .PRINT prtype ov1 <ov2 ... > .PROBE .SENS ov1 <ov2 ... > .TEMP T1 <T2 <T3 ...>> .TF outvar insrc .TRAN tstep tstopn <tstart <tmax>> <UIC>

SCALE FACTORS: T = 1E12 M = 1E-3 G = 1E9 U = 1E-6 MEG = 1E6 N = 1E-9 K = 1E3 P = 1E-12 MIL = 25.4E-6 F = 1E-15

MOSFET Level 1 Models [ simple instance syntax:


.MODEL NMOSL1 NMOS + LEVEL=1 + TOX=5.0E-8 U0=500 + XJ=0.3U LD=0.3U WD=0.2U + LAMBDA=0.01 GAMMA=0.8 PHI=0.7 VT0=1.0 + CJ=400U CJSW=300P CGDO=300P CGSO=300P RSH=50

Mxx nd ng ns nb model W=xx L=xx ]


.MODEL PMOSL1 PMOS + LEVEL=1 + TOX=5.0E-8 U0=200 + XJ=0.3U LD=0.3U WD=0.2U + LAMBDA=0.02 GAMMA=0.7 PHI=0.6 VT0=-1.0 + CJ=400U CJSW=300P CGDO=300P CGSO=300P RSH=100

18 September 1994
Modified 1/12/08

D. Renshaw
[email protected]:\D430dar2oo8-9\ee3\Part2\src\MOSData-2.fm

page 4 of 5

University of Edinburgh

EE4
LSI Circuits

Electrical Engineering

18 September 1994
Modified 1/12/08

D. Renshaw
[email protected]:\D430dar2oo8-9\ee3\Part2\src\MOSData-2.fm

page 5 of 5

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