Finite State Machine Design

Motivation - Counters: Sequential Circuits where State = Output - Generalizes to Finite State Machines: Outputs are Function of State (and Inputs) Next States are Functions of State and Inputs Used to implement circuits that control other circuits "Decision Making" logic - Application of Sequential Logic Design Techniques Word Problems Mapping into formal representations of FSM behavior Case Studies

Overview Concept of the State Machine - Partitioning into Datapath and Control

- When Inputs are Sampled and Outputs Asserted

Basic Design Approach - Six Step Design Process Alternative State Machine Representations - State Diagram, ASM Notation, VHDL, ABEL Description Language Moore and Mealy Machines - Definitions, Implementation Examples Word Problems - Case Studies

Concept of the State Machine

Computer Hardware = Datapath + Control

Qualifiers

Registers Combinational Functional Units (e.g., ALU) Busses

Control

FSM generating sequences of control signals Instructs datapath what to do next

Control
State Qualifiers and Inputs

"Puppeteer who pulls the strings"

Control Signal Outputs

"Puppet"

Datapath

Concept of the State Machine Example: Odd Parity Checker Assert output whenever input bit stream has odd # of 1's

Reset 0

Even [0] 1 Odd [1] 1

Present State Even Even Odd Odd

Input 0 1 0 1

Next State Even Odd Odd Even

Output 0 0 1 1

Symbolic State Transition Table

Present State 0 0 1 1 Input 0 1 0 1 Next State Output 0 0 1 0 1 1 0 1

State Diagram

Encoded State Transition Table

Concept of the State Machine Example: Odd Parity Checker Next State/Output Functions NS = PS xor PI; OUT = PS
NS Input CLK R \Reset Q D Q PS/Output

Input CLK

T R

Q Q

Output

\Reset
T FF Implementation

D FF Implementation
Input Clk 1 0 0 1 1 0 1 0

Output

Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

Concept of State Machine

Timing: When are inputs sampled, next state computed, outputs asserted?
State Time: Time between clocking events - Clocking event causes state/outputs to transition, based on inputs - For set-up/hold time considerations: Inputs should be stable before clocking event

- After propagation delay, Next State entered, Outputs are stable

NOTE: Asynchronous signals take effect immediately Synchronous signals take effect at the next clocking event

E.g., tri-state enable: effective immediately sync. counter clear: effective at next clock event

Concept of State Machine Example: Positive Edge Triggered Synchronous System

State T ime

On rising edge, inputs sampled outputs, next state computed

After propagation delay, outputs and next state are stable

Clock

Inputs

Immediate Outputs: affect datapath immediately could cause inputs from datapath to change
Delayed Outputs: take effect on next clock edge propagation delays must exceed hold times

Outputs

Concept of the State Machine Communicating State Machines One machine's output is another machine's input
X FSM 1 Y FSM 2

CLK FSM 1 X A A B

Y=0 Y=0 A [1] Y=1 X=0 C [0]

X=0

FSM 2 Y

X=1 X=1

Y=0,1

B [0]

X=0

D [1]

Machines advance in lock step Initial inputs/outputs: X = 0, Y = 0

Basic Design Approach Six Step Process 1. Understand the statement of the Specification 2. Obtain an abstract specification of the FSM 3. Perform a state mininimization 4. Perform state assignment 5. Choose FF types to implement FSM state register 6. Implement the FSM

1, 2 covered now; 3, 4, 5 covered later; 4, 5 generalized from the counter design procedure

Basic Design Approach Example: Vending Machine FSM General Machine Concept: deliver package of gum after 15 cents deposited single coin slot for dimes, nickels no change Step 1. Understand the problem: Draw a picture! Block Diagram
N Coin Sensor D Reset Clk Vending Machine FSM Open Gum Release Mechanism

Vending Machine Example Step 2. Map into more suitable abstract representation

Tabulate typical input sequences: three nickels nickel, dime dime, nickel two dimes two nickels, dime
Draw state diagram: Inputs: N, D, reset Output: open
S3 N

Reset S0 N S1 D S2

D S4 [open]

N S5 [open]

D S6 [open]

N S7 [open]

D S8 [open]

Vending Machine Example

Step 3: State Minimization

Reset 0

Present State

Inputs D N

Next State

Output Open

0
N 5 D N 10 D N, D 15 [open]

10

15

0 0 1 1 0 0 1 1 0 0 1 1 X

0 1 0 1 0 1 0 1 0 1 0 1 X

0 5 10 X 5 10 15 X 10 15 15 X 15

0 0 0 X 0 0 0 X 0 0 0 X 1

reuse states whenever possible

Symbolic State Table

Vending Machine Example Step 4: State Encoding

Present State Q1 Q0 0 0 Inputs D N 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Next State D1 D0 0 0 1 X 0 1 1 X 1 1 1 X 1 1 1 X 0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X Output Open 0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X

Vending Machine Example

Step 5. Choose FFs for implementation D FF easiest to use

Q1 Q0 DN Q1 Q1 Q0 DN Q1 Q1 Q0 DN Q1

0
0
D

0
1

1
1

1
1
N D

0 1
1 X 0 0 X 1

1 0
1 1 1 1
N D

0
0 X 0

0
0 X 0

1
1 X 1

0
0 X 0
N

X X X X 1 1 1 1
Q0 K-map for D1
Q1 D D1 D CLK R \reset Q Q1

X X

Q0 K-map for D0

Q0 K-map for Open

Q0 N N \ Q0 Q0 \N Q1 N Q1 D

Q \ Q1

D1 = Q1 + D + Q0 N
OPEN

D0 = N Q0 + Q0 N + Q1 N + Q1 D

D0 CLK

D R

Q0

OPEN = Q1 Q0

Q \ Q0

\reset

8 Gates

Vending Machine Example Step 5. Choosing FF for Implementation

J-K FF
Present State Q1 Q0 0 0 Inputs D N 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Next State D1 D0 0 0 1 X 0 1 1 X 1 1 1 X 1 1 1 X 0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X J1 0 0 1 X 0 1 1 X X X X X X X X X K1 X X X X X X X X 0 0 0 X 0 0 0 X J0 K 0 0 1 0 X X X X X 0 1 1 X X X X X X X X X 0 1 0 X X X X X 0 0 0 X

Remapped encoded state transition table

Vending Machine Example

Implementation:
Q1 Q0 DN Q1 Q1 Q0 DN Q1

J1 = D + Q0 N 0 0 X 0 0 0 X 0
N

0 0 X 1

0 1 X 1

X X X X

X X X X

N D

X X X X X X X X

K1 = 0 J0 = Q0 N + Q1 D K0 = Q1 N

Q0 K-map for J1 Q1 Q1 Q0 DN

Q0 K-map for K1 Q1 Q1 Q0 DN

0 X X 0
D

X 0 0 X
N

1 X X 1 X X X X 0 X X 1
Q0 K-map for J0

X 1 0 X X X X X X 0 0 X
Q0 K-map for K0

N Q0 D \ Q0 N Q1 D \ Q1 N \reset CLK CLK

Q1 \ Q1

K RQ

OPEN Q0 \ Q0

J K R

Q Q

7 Gates

Alternative State Machine Representations Why State Diagrams Are Not Enough Not flexible enough for describing very complex finite state machines Not suitable for gradual refinement of finite state machine Do not obviously describe an algorithm: that is, well specified sequence of actions based on input data algorithm = sequencing + data manipulation

separation of control and data

Gradual shift towards program-like representations:

- Algorithmic State Machine (ASM) Notation

- Hardware Description Languages (e.g., VHDL)

Alternative State Machine Representations

Algorithmic State Machine (ASM) Notation

Three Primitive Elements: - State Box - Decision Box - Output Box
State Entry Path State Code

*
State Name State Output List T

***
State Box

State Machine in one state block per state time

Single Entry Point Unambiguous Exit Path for each combination of inputs Outputs asserted high (.H) or low (.L); Immediate (I) or delayed till next clock

Condition

ASM Block

Condition Box Conditional Output List

Output Box

Exits to other ASM Blocks

Alternative State Machine Representations

ASM Notation
Condition Boxes: Ordering has no effect on final outcome Equivalent ASM charts: A exits to B on (I0 I1) else exit to C
A 010 A 010

I0 T I1 T B

F T

I1

F I0

T C B C

Alternative State Machine Representations Example: Parity Checker Input X, Output Z

Even 0

Nothing in output list implies Z not asserted

Z asserted in State Odd
X T Odd H.Z F T 1 F

Symbolic State Table: Present Next Input State State Output F Even Even T Even Odd F A Odd Odd T A Odd Even Encoded State Table:

Trace paths to derive state transition tables

Present Next Input State State Output 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1 0

Alternative State Machine Representations ASM Chart for Vending Machine

00

10

10

D
F F N T

D
F

N T

01

15
H.Open

11

N F F D

Reset T

Alternative State Machine Representations Hardware Description Languages: VHDL

ENTITY parity_checker IS PORT ( x, clk: IN BIT; z: OUT BIT); END parity_checker; ARCHITECTURE behavioral OF parity_checker IS BEGIN main: BLOCK (clk = 1and not clkTABLE) TYPE state IS (Even, Odd); SIGNAL state_register: state := Even; BEGIN state_even: BLOCK ((state_register = Even) AND GUARD) BEGIN state_register <= Odd WHEN x = 1 ELSE Even END BLOCK state_even; BEGIN state_odd: BLOCK ((state_register = Odd) AND GUARD) BEGIN state_register <= Even WHEN x = 1 ELSE Odd; END BLOCK state_odd;

Interface Description Architectural Body

Guard Expression

Determine New State

z <= 0WHEN state_register = Even ELSE 1WHEN state_register = Odd; END BLOCK main; END behavioral;

Determine Outputs

Alternative State Machine Representations ABEL Hardware Description Language

module parity test_vectors ([clk, RESET, X] -> [SREG]) title 'odd parity checker state machine' [0,1,.X.] -> [S0]; u1 device 'p22v10'; [.C.,0,1] -> [S1]; [.C.,0,1] -> [S0]; "Input Pins [.C.,0,1] -> [S1]; clk, X, RESET pin 1, 2, 3; [.C.,0,0] -> [S1]; [.C.,0,1] -> [S0]; "Output Pins [.C.,0,1] -> [S1]; Q, Z pin 21, 22; [.C.,0,0] -> [S1]; [.C.,0,0] -> [S1]; Q, Z istype 'pos,reg'; [.C.,0,0] -> [S1]; end parity; "State registers SREG = [Q, Z]; S0 = [0, 0]; " even number of 0's S1 = [1, 1]; " odd number of 0's equations [Q.ar, Z.ar] = RESET; "Reset to state S0 state_diagram SREG state S0: if X then S1 else S0; state S1: if X then S0 else S1;

Moore and Mealy Machine Design Procedure Definitions

State Register Xi Inputs Combinational Logic for Next State (Flip-flop Inputs) Clock Comb. Logic for Outputs Zk Outputs

Moore Machine

Outputs are function solely of the current state

Outputs change synchronously with state changes

state feedback

Mealy Machine
Xi Inputs Combinational Logic for Outputs and Next State Zk Outputs

Outputs depend on state AND inputs Input change causes an immediate output change Asynchronous signals

State Register

Clock

State Feedback

Moore and Mealy Machines State Diagram Equivalents

Moore Machine

N D + Reset Reset 0 [0] Reset 5 ND [0] N 10 D [0] N+D 15 [1] Reset ND D N

Reset/0 0

(N D + Reset)/0

Mealy Machine

Reset/0 5 N D/0 N/0

N/0

D/0

10 D/1 N D/0 N+D/1 15 Reset/1

Outputs are associated with State

Outputs are associated with Transitions

Moore and Mealy Machines States vs. Transitions Mealy Machine typically has fewer states than Moore Machine for same output sequence
0 0 [0] 0 0/0

Same I/O behavior Different # of states

0 1 [0]

1 0

0/0 1

1/0

1/1 1

2 [1] 1

F T T

Equivalent ASM Charts

F T F T F

Moore and Mealy Machines Timing Behavior of Moore Machines Reverse engineer the following:
X X \B J Q C KR Q FFa Clk \Reset A \A

Input X Output Z State A, B = Z

X X \A

J Q C KR Q FFb \Reset

Z \B

Two Techniques for Reverse Engineering:

- Ad Hoc: Try input combinations to derive transition table - Formal: Derive transition by analyzing the circuit

Moore and Mealy Machines Ad Hoc Reverse Engineering Behavior in response to input sequence 1 0 1 0 1 0:
100 X Clk A Z \Reset Reset X=1 X=0 X=1 X= 0 X=1 X= 0 X= 0 AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00
A B 0 0 X 0 1 0 1 0 1 0 1 A+ ? 1 0 ? 1 0 1 1 B+ ? 1 0 ? 0 1 1 0 Z 0 0 1 1 0 0 1 1

Partially Derived State Transition Table

0 1 1 0 1 1

Moore and Mealy Machines Formal Reverse Engineering Derive transition table from next state and output combinational functions presented to the flipflops! Ja = X Jb = X Ka = X B Kb = X xor A Z=B

FF excitation equations for J-K flipflop: A+ = Ja A + Ka A = X A + (X + B) A B+ = Jb B + Kb B = X B + (X A + X A) B Next State K-Maps: AB X 00 01 11 10 0 0 1 1 1 AB 1

01

A+

1
11

0
10

State 00, Input 0 -> State 00 State 01, Input 1 -> State 01

00

0 1

0 1

B+

0 1

Moore and Mealy Machines Complete ASM Chart for the Mystery Moore Machine

S0

00

S3 H.Z

11

X S1 H.Z 01

1 1 S2

X 10

Note: All Outputs Associated With State Boxes No Separate Output Boxes ?Intrinsic in Moore Machines

Moore and Mealy Machines Reverse Engineering a Mealy Machine

Clk A \A R Q \Reset \A X J C K Q R Q \Reset B \B

D DA C

\X

A X B \X

DA

\X B Z X A

Input X, Output Z, State A, B State register consists of D FF and J-K FF

Moore and Mealy Machine Ad Hoc Method Signal Trace of Input Sequence 101011:
100 X Clk A B Z \Reset Reset AB =00 Z =0 X =1 AB =00 Z =0 X =0 AB =00 Z =0 X =1 AB =01 Z =0 X =0 AB =11 Z=1 X =1 AB =10 Z =1 X =1 AB =01 Z =0

Note glitches in Z!
Outputs valid at following falling clock edge

A B 0 0

Partially completed state transition table based on the signal trace

0 1 1 0 1 1

X 0 1 0 1 0 1 0 1

A+ 0 0 ? 1 ? 0 1 ?

B+ 1 0 ? 1 ? 1 0 ?

Z 0 0 ? 0 ? 1 1 ?

Moore and Mealy Machines Formal Method A+ = B (A + X) = A B + B X B+ = Jb B + Kb B = (A xor X) B + X B = A B X + A B X + B X Z X =A X + B X AB

00 01 11 10

A+

0
AB X
00

1
01

1
11

0
10

Missing Transitions and Outputs: State 01, Input 0 -> State 01, Output 1 State 10, Input 0 -> State 00, Output 0 State 11, Input 1 -> State 11, Output 1

B+

0
AB X 00 0

1
01

1
11

1
10

Moore and Mealy Machines ASM Chart for Mystery Mealy Machine S0 = 00, S1 = 01, S2 = 10, S3 = 11

S0

00

S2

10

0 X 0 H. Z X 1

H. Z

S1

01

S3 H.Z

11

X 0

NOTE: Some Outputs in Output Boxes as well as State Boxes This is intrinsic in Mealy Machine implementation

Moore and Mealy Machines Synchronous Mealy Machine

Clock Xi Inputs Zk Outputs

Combinational Logic for Outputs and Next State State Register

Clock

state feedback

latched state AND outputs avoids glitchy outputs!

Finite State Machine Word Problems Mapping English Language Description to Formal Specifications Four Case Studies:

- Finite String Pattern Recognizer

- Complex Counter with Decision Making - Traffic Light Controller

- Digital Combination Lock

We will use state diagrams and ASM Charts

Finite State Machine Word Problems Finite String Pattern Recognizer A finite string recognizer has one input (X) and one output (Z). The output is asserted whenever the input sequence 010 has been observed, as long as the sequence 100 has never been seen. Step 1. Understanding the problem statement Sample input/output behavior: X: 00101010010 Z: 00010101000 X: 11011010010 Z: 00000001000

Finite State Machine Word Problems

Finite String Recognizer

Step 2. Draw State Diagrams/ASM Charts for the strings that must be recognized. I.e., 010 and 100.

0 S1 [0] 1 S2 [0] 0 Outputs 1 S3 [1]

S0 [0]

Reset 1 S4 [0] 0 S5 [0] 0 S6 [0] 0,1 Loops in State Moore State Diagram Reset signal places FSM in S0

Finite State Machine Word Problems Finite String Recognizer Exit conditions from state S3: have recognized 010 if next input is 0 then have 0100! if next input is 1 then have 0101 = ..01 (state S2) Reset

0
S1 [0] 1 01 0 S3 010 [1] S2 [0] 1

S0 [0]

1
S4 [0] 0 S5 [0] 0

S6 [0] 100

0,1

Finite State Machine Word Problems Finite String Recognizer Exit conditions from S1: recognizes strings of form 0 (no 1 seen) loop back to S1 if input is 0 Exit conditions from S4: recognizes strings of form 1 (no 0 seen) loop back to S4 if input is 1 S0 [0] Reset 1 S4 [0] 0 S5 [0] 1 S3 [1] 0 100 S6 [0] 0 0,1 1

0 0 S1 [0] 1 S2 01 [0]

010

Finite State Machine Word Problems Finite String Recognizer S2, S5 with incomplete transitions S2 = 01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case! S5 = 10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case! Reset S0 [0] 0 1 0 S1 [0] 1 S2 01 [0] 1 1 S3 [1] 0 100 S4 [0] 0 1 Final State Diagram

..10

S5 [0] 0 S6 [0] 0,1

010

Finite State Machine Word Problems Finite String Recognizer

module string state_diagram SREG title '010/100 string recognizer state machine state S0: if X then Josephine Engineer, Itty Bity Machines, Inc.' state S1: if X then u1 device 'p22v10'; state S2: if X then state S3: if X then "Input Pins state S4: if X then state S5: if X then clk, X, RESET pin 1, 2, 3; state S6: goto S6; "Output Pins test_vectors ([clk, Q0, Q1, Q2, Z pin 19, 20, 21, 22; [0,1,.X.] -> [0]; [.C.,0,0] -> [0]; Q0, Q1, Q2, Z istype 'pos,reg'; [.C.,0,0] -> [0]; [.C.,0,1] -> [0]; "State registers [.C.,0,0] -> [1]; SREG = [Q0, Q1, Q2, Z]; [.C.,0,1] -> [0]; S0 = [0,0,0,0]; " Reset state [.C.,0,0] -> [1]; S1 = [0,0,1,0]; " strings of the form ...0 [.C.,0,1] -> [0]; S2 = [0,1,0,0]; " strings of the form ...01 [.C.,0,0] -> [1]; S3 = [0,1,1,1]; " strings of the form ...010 [.C.,0,0] -> [0]; S4 = [1,0,0,0]; " strings of the form ...1 [.C.,0,1] -> [0]; S5 = [1,0,1,0]; " strings of the form ...10 [.C.,0,0] -> [0]; S6 = [1,1,0,0]; " strings of the form ...100 end string; equations [Q0.ar, Q1.ar, Q2.ar, Z.ar] = RESET; "Reset to S0 S4 S2 S4 S2 S4 S2 else else else else else else S1; S1; S3; S6; S5; S6;

RESET, X] -> [Z]

ABEL Description

Finite State Machine Word Problems Finite String Recognizer Review of Process: - Write down sample inputs and outputs to understand specification

- Write down sequences of states and transitions for the sequences to be recognized
- Add missing transitions; reuse states as much as possible - Verify I/O behavior of your state diagram to insure it functions like the specification

Finite State Machine Word Problems Complex Counter A sync. 3 bit counter has a mode control M. When M = 0, the counter counts up in the binary sequence. When M = 1, the counter advances through the Gray code sequence. Binary: 000, 001, 010, 011, 100, 101, 110, 111 Gray: 000, 001, 011, 010, 110, 111, 101, 100 Valid I/O behavior: Mode Input M 0 0 1 1 1 0 0 Current State 000 001 010 110 111 101 110 Next State (Z2 Z1 Z0) 001 010 110 111 101 110 111

Finite State Machine Word Problems Complex Counter One state for each output combination Add appropriate arcs for the mode control

S0

000

S1 H.Z 0 0

001

S2

010 H.Z 1 0 1

S3

011 H.Z 1 H.Z 0

M 1 S6 H.Z 2 H.Z 1

M 0

110 S4

100 H.Z 2 1 0

S7 H.Z 2 H.Z 1 H.Z 0 0

111

S5 1 0 H.Z 2 H.Z 0

101

Finite State Machine Word Problems Complex Counter

module counter title 'combination binary/gray code upcounter Josephine Engineer, Itty Bity Machines, Inc.' u1 device 'p22v10'; state_diagram SREG state S0: goto S1; "Input Pins state S1: if M then S3 else S2; clk, M, RESET pin 1, 2, 3; state S2: if M then S6 else S3; state S3: if M then S2 else S4; "Output Pins state S4: if M then S0 else S5; Z0, Z1, Z2 pin 19, 20, 21; state S5: if M then S4 else S6; state S6: goto S7; Z0, Z1, Z2 istype 'pos,reg'; state S7: if M then S5 else S0; "State registers SREG = [Z0, Z1, Z2]; test_vectors ([clk, RESET, M] -> [Z0, Z1, Z2]) S0 = [0,0,0]; [0,1,.X.] -> [0,0,0]; S1 = [0,0,1]; [.C.,0,0] -> [0,0,1]; S2 = [0,1,0]; [.C.,0,0] -> [0,1,0]; S3 = [0,1,1]; [.C.,0,1] -> [1,1,0]; S4 = [1,0,0]; [.C.,0,1] -> [1,1,1]; S5 = [1,0,1]; [.C.,0,1] -> [1,0,1]; S6 = [1,1,0]; [.C.,0,0] -> [1,1,0]; S7 = [1,1,1]; [.C.,0,0] -> [1,1,1]; end counter; equations [Z0.ar, Z1.ar, Z2.ar] = RESET; "Reset to state S0

ABEL Description

Finite State Machine Word Problems Traffic Light Controller

A busy highway is intersected by a little used farmroad. Detectors C sense the presence of cars waiting on the farmroad. With no car on farmroad, light remain green in highway direction. If vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green. These stay green only as long as a farmroad car is detected but never longer than a set interval. When these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green. Even if farmroad vehicles are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse (TS) and a long time pulse (TL) in response to a set (ST) signal. TS is to be used for timing yellow lights and TL for green lights.

Finite State Machine Word Problems Traffic Light Controller Picture of Highway/Farmroad Intersection:

Farmroad C FL HL Highway

Highway HL FL C Farmroad

Finite State Machine Word Problems Traffic Light Controller - Tabulation of Inputs and Outputs: Input Signal reset C TS TL Output Signal HG, HY, HR FG, FY, FR ST Description place FSM in initial state detect vehicle on farmroad short time interval expired long time interval expired Description assert green/yellow/red highway lights assert green/yellow/red farmroad lights start timing a short or long interval

- Tabulation of Unique States: Some light configuration imply others State S0 S1 S2 S3

Description Highway green (farmroad red) Highway yellow (farmroad red) Farmroad green (highway red) Farmroad yellow (highway red)

Finite State Machine Word Problems Traffic Light Controller Refinement of ASM Chart: Start with basic sequencing and outputs:

S0 H.HG H.FR

S3 H.HR H.FY

S1 H.HY H.FR

S2 H.HR H.FG

Finite State Machine Word Problems Traffic Light Controller Determine Exit Conditions for S0: Car waiting and Long Time Interval Expired- C TL
S0 H.HG H.FR 0 0 S0 H.HG H.FR

TL

TL C

1
0 C 1 H.ST S1

1
H.ST

H.HY H.FR S1 H.HY H.FR

Equivalent ASM Chart Fragments

Finite State Machine Word Problems Traffic Light Controller S1 to S2 Transition: Set ST on exit from S0 Stay in S1 until TS asserted Similar situation for S3 to S4 transition

S1 H.HY H.FR 0

H.ST

S2 H.HR H.FG

TS

Finite State Machine Word Problems Traffic Light Controller S2 Exit Condition: no car waiting OR long time interval expired

S0 H.HG H.FR 0

H.ST

S3 H.HR H.FY 0

TL C 1 H.ST

TS

H.ST

S1 H.HY H.FR 0

H.ST

S2 H.HR H.FG 0 TL + C 1

TS

Complete ASM Chart for Traffic Light Controller

Finite State Machine Word Problems Traffic Light Controller Compare with state diagram:
TL + C Reset

S0
TLC/ST TS S1 TS/ST S3 TS TL + C/ST TS/ST

S0: HG S1: HY S2: FG S3: FY

S2
TL C

Advantages of State Charts:

Concentrates on paths and conditions for exiting a state

Exit conditions built up incrementally, later combined into single Boolean condition for exit Easier to understand the design as an algorithm

Finite State Machine Word Problems Traffic Light Controller

module traffic title 'traffic light FSM' u1 device 'p22v10'; "Input Pins clk, C, RESET, TS, TL pin 1, 2, 3, 4, "Output Pins Q0, Q1, HG, HY, HR, FG, FY, FR, ST pin 14, 15, 16, 17, 18, 19, 20, 21, 22; HY HR FG FY FR = = = = = !Q0 & Q1; (Q0 & !Q1) # (Q0 & Q1); Q0 & !Q1; Q0 & Q1; (!Q0 & !Q1) # (!Q0 & Q1);

5;

Q0, Q1 istype 'pos,reg'; ST, HG, HY, HR, FG, FY, FR istype 'pos,com';test_vectors ([clk,RESET, C, TS, TL]->[SREG,HG,HY,HR,FG,FY,FR,ST]) "State registers [.X., 1,.X.,.X.,.X.]->[ S0, 1, 0, 0, 0, 0, 1, 0]; SREG = [Q0, Q1]; [.C., 0, 0, 0, 0]->[ S0, 1, 0, 0, 0, 0, 1, 0]; S0 = [ 0, 0]; [.C., 0, 1, 0, 1]->[ S1, 0, 1, 0, 0, 0, 1, 0]; S1 = [ 0, 1]; [.C., 0, 1, 0, 0]->[ S1, 0, 1, 0, 0, 0, 1, 0]; S2 = [ 1, 0]; [.C., 0, 1, 1, 0]->[ S2, 0, 0, 1, 1, 0, 0, 0]; S3 = [ 1, 1]; [.C., 0, 1, 0, 0]->[ S2, 0, 0, 1, 1, 0, 0, 0]; [.C., 0, 1, 0, 1]->[ S3, 0, 0, 1, 0, 1, 0, 0]; equations [.C., 0, 1, 1, 0]->[ S0, 1, 0, 0, 0, 0, 1, 0]; [Q0.ar, Q1.ar] = RESET; end traffic; HG = !Q0 & !Q1;

state_diagram SREG state S0: if (TL & C) then S1 with ST = 1 else S0 with ST = 0 state S1: if TS then S2 with ST = 1 else S1 with ST = 0 state S2: if (TL # !C) then S3 with ST = 1 else S2 with ST = 0 state S3: if TS then S0 with ST = 1 else S3 with ST = 0

ABEL Description

Finite State Machine Word Problems Digital Combination Lock "3 bit serial lock controls entry to locked room. Inputs are RESET, ENTER, 2 position switch for bit of key data. Locks generates an UNLOCK signal when key matches internal combination. ERROR light illuminated if key does not match combination. Sequence is: (1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) & (3) two more times." Problem specification is incomplete: how do you set the internal combination?

exactly when is the ERROR light asserted?

Make reasonable assumptions: hardwired into next state logic vs. stored in internal register

assert as soon as error is detected vs. wait until full combination has been entered

Our design: registered combination plus error after full combination

Finite State Machine Word Problems Digital Combination Lock Understanding the problem: draw a block diagram
RESET

Operator Data

ENTER KEY-IN Combination Lock FSM

UNLOCK

ERROR

Internal Combination

L0 L1 L2

Inputs: Reset Enter Key-In L0, L1, L2

Outputs: Unlock Error

Finite State Machine Word Problems Digital Combination Lock Enumeration of states: what sequences lead to opening the door? error conditions on a second pass

START state plus three key COMParison states

START

START entered on RESET Exit START when ENTER is pressed

Reset 0 Enter COMP0 1 0 1

KI = L0 Y

Continue on if Key-In matches L0

Finite State Machine Word Problems Digital Combination Lock

COMP0 IDLE1

Path to unlock:
N 0 1

KI = L 0 Y IDLE0

Enter COMP2

Wait for Enter Key press

Enter COMP1 1 0 KI = L2 Y DONE H.Unlock N

Compare Key-IN

KI = L1 Y

Reset 1 START

Finite State Machine Word Problems Digital Combination Lock Now consider error paths Should follow a similar sequence as UNLOCK path, except asserting ERROR at the end:
IDLE0' IDLE1' ERROR3 H.Error 0 1 0

Enter ERROR1

Enter ERROR2 1

Reset 1 START

COMP0 error exits to IDLE0' COMP1 error exits to IDLE1' COMP2 error exits to ERROR3

Finite State Machine Word Problems Digital Combination Lock

Reset + Enter Reset Start Reset Enter Comp0

KI = L0 Enter Idle0 Enter Comp1 KI = L1 Enter Idle1 Enter Comp2 KI = L2 Reset Done [Unlock] Reset Start KI L2 KI L1

KI L0 Enter Idle0' Enter Error1

Equivalent State Diagram

Enter Idle1' Enter Error2

Error3 [Error] Reset Start

Reset

Finite State Machine Word Problems Combination Lock

module lock title 'comb. lock FSM' u1 device 'p22v10'; equations [Q0.ar, Q1.ar, Q2.ar, Q3.ar] = RESET; UNLOCK = !Q0 & Q1 & Q2 & !Q3;"asserted in DONE "Input Pins ERROR = Q0 & !Q1 & Q2 & Q3; "asserted in ERROR3 clk, RESET, ENTER, L0, L1, L2, KI pin 1, 2, 3, 4, 5, 6, 7; state_diagram SREG state START: if (RESET # !ENTER) "Output Pins then START else COMP0; Q0, Q1, Q2, Q3, UNLOCK, ERROR state COMP0: if (KI == L0) then IDLE0 else IDLE0p; pin 16, 17, 18, 19, 14, 15; state IDLE0: if (!ENTER) then IDLE0 else COMP1; state COMP1: if (KI == L1) then IDLE1 else IDLE1p; Q0, Q1, Q2, Q3 istype 'pos,reg';state IDLE1: if (!ENTER) then IDLE1 else COMP2; UNLOCK, ERROR istype 'pos,com';state COMP2: if (KI == L2) then DONE else ERROR3; state DONE: if (!RESET) then DONE else START; "State registers state IDLE0p:if (!ENTER) then IDLE0p else ERROR1; SREG = [Q0, Q1, Q2, Q3]; state ERROR1:goto IDLE1p; START = [ 0, 0, 0, 0]; state IDLE1p:if (!ENTER) then IDLE1p else ERROR2; COMP0 = [ 0, 0, 0, 1]; state ERROR2:goto ERROR3; IDLE0 = [ 0, 0, 1, 0]; state ERROR3:if (!RESET) then ERROR3 else START; COMP1 = [ 0, 0, 1, 1]; IDLE1 = [ 0, 1, 0, 0]; test_vectors COMP2 = [ 0, 1, 0, 1]; DONE = [ 0, 1, 1, 0]; end lock; IDLE0p = [ 0, 1, 1, 1]; ERROR1 = [ 1, 0, 0, 0]; IDLE1p = [ 1, 0, 0, 1]; ERROR2 = [ 1, 0, 1, 0]; ERROR3 = [ 1, 0, 1, 1];

Review Basic Timing Behavior an FSM when are inputs sampled, next state/outputs transition and stabilize Moore and Mealy (Async and Sync) machine organizations outputs = F(state) vs. outputs = F(state, inputs)

First Two Steps of the Six Step Procedure for FSM Design understanding the problem abstract representation of the FSM

Abstract Representations of an FSM ASM Charts, Hardware Description Languages

Word Problems understand I/O behavior; draw diagrams enumerate states for the "goal"; expand with error conditions reuse states whenever possible