MICROCONTROLLER DESCRIPTION The AT89S52 is designed with static logic for operation down to zero frequency and supports

two software selectable power saving modes The !dle "ode stops the #$% while allowing the &A"' timer(counters' serial port and interrupt system to continue functioning The $ower)down "ode saves the &A" contents but freezes the oscillator disabling all other chip functions until the ne*t hardware reset This gala*y of parts' the result of desire by the manufactures to leave to mar+et niche unfilled' would require many chapters to cover in a ,- pin .!$' and direct the investigation of a particular type of the data boo+s The bloc+ diagram of the 89S52 in figure shows all of the features unique to microcontrollers !nternal &/" and &A" !(/ ports with programmable pins Timers and counters Serial data #ommunication The figure also shows the usual components program counter A0%' wor+ing register' and cloc+ circuits The pin diagram and architecture of microcontroller 1AT89S522 as shown in fig 3 and fig 4

A T 8 9 S 5 2

5!6 3 $in .iagram /f AT89S52 "icrocontroller

5ig 4 "icrocontroller Architectue

AT89S52 MICROCONTROLLER

The 89S52 architecture consists of these specific features 7ight)bit #$% with register A1the accumulator2 and 8 Si*teen 9bit program counter1$#2 and data pointer1.$T&2 7ight) bit program status word1$S:2 7ight) bit stac+ pointer1S$2 5our register ban+s' each containing eight register Si*teen bytes which may be addressed at any level 7ight bytes of general 9 purpose data memory Thirty 9 two input( output pins arrange as four 8)bitt ports; $-)$< 5ull duple* serial data receiver( transmitter ;S$%5 #ontrol register ;T#/=>T"/.'S#/='$#/='!$ and !7 #ompatible with "#S?)5@ $roducts 8A 8ytes of !n)System $rogrammable 1!S$2 5lash "emory 9 7ndurance; @--- :rite(7rase #ycles , -B to 5 5B /perating &ange 5ully Static /peration; - Cz to << "Cz Three)level $rogram "emory 0oc+ 253 * 8)bit !nternal &A" Three @3)bit Timer(#ounters 7ight !nterrupt Sources 5ull .uple* %A&T Serial #hannel 0ow)power !dle and $ower)down "odes !nterrupt &ecovery from $ower)down "ode 2.3.1. PIN DESCRIPTION OF MICROCONTROLLER

PORT 0 $ort - is an 8 bit drain bi)directional !(/ port As an output port' each pin can sin+ eight TT0 inputs :hen are written to port - pins can be used as high impedance inputs $ort - may also be configured to be multiple*ed low order address( data bus during accesses to e*ternal program and data memory !n this' mode' $- has internal $ull)ups $ort - also receives the bytes during flash programming and output program verification PORT 1 $ort @ is an 8 bit bi)directional !(/ port with e*ternal pull)ups The port @ output buffer can sin+ ( source four TT0 inputs :hen @s are written to port @ pins are pulled high by the internal pull)ups and can be used as inputs As input' input port @ pin that are e*ternally pulled low will source current because of the internal pull)up PORT 2 $ort 2 is an 8 bit bi)directional !(/ port with internal pull)up The port 2 output buffer can sin+( Source four TT0 inputs :hen @ s is written to port 2 pins they are pulled high by the internal pull)up and can be used as inputs As inputs port 2 pins that are e*ternally being pulled low will source current because of the internal pull)ups $ort 2 emits the higher order address byte during fetches from e*ternal memory and during access to e*ternal data memory that uses @3 bit addresses !n this application !t uses strong internal pull)up when emitting @s

PORT 3 $ort < is an eight bit bi)directional !(/ port with internal port pull)ups The $ort output buffer can sin+ ( Source four TT0 inputs :hen @s are written to port < pins they are pulled high by the internal pull)ups and can be used as inputs As input' port < pins that are e*ternally being pulled 0ow source current because pull)ups $ort < also receive some control signals fro 5lash programming and Berification RST &eset input A high on this pin for two machine cycle while the oscillator is running reset the device ALE/PROG Address 0atch 7nable output pulse for the latching the low bytes of the address during access to e*ternal memory The pin is also the program pulse input 1$&/62 during flash programming !n normal operations A07 is enabled at a constant rate @(3 th of the oscillator frequency' any may be used for e*ternal timing or cloc+ing purpose =ote' however' that one A07 pulse is s+ipped during each access to e*ternal data memory The A07 operation can be disabled by setting bit - in S5& location 8 7C :ith the bit set' A07 is active only during a "/B D or "ov # instruction /therwise' the pin wea+ly pulled high Setting the A07)disable bit has no effect microcontroller is in e*ternal e*ecution mode PSEN $rogram Strobe 7nable is the read strobe to e*ternal program memory :hen the AT89#52 is e*ecuting code from e*ternal program

cycle' e*cept that two $S7= activations are s+ipped during each access to e*ternal data memory EA/VPP 7*ternal Access 7nable 7A must be strapped to 6=. in order to enable the device to fetch from e*ternal program memory locations starting at ----C up to 5555C =ote' however' that if loc+ bit @ bit programmed' 7A will be internal latched on reset 7A should be strapped to B## for internal programmable e*ecution that require @2 Bolt B$$ XTAL1 !nput to the inverting oscillator amplifier and input to the internal cloc+ operating circuit XTAL2 /utput from the inverting oscillator amplifier connection is as shown in the fig 8 The oscillator This pin also receives the @2 B programming enable voltage 1B$$2 during 5lash programming' f or parts

5!6 8 /S#!00AT/& #/==7#T!/=S

OSCILLATOR CHARACTERISTICS

The DTA0@ and DTA02 are the input and output' respectively' of an inverting amplifier' which can be configured for use as an on)chip oscillator' as shown in 5igure @ 7ither a quartz crystal or ceramic resonator may be used To drive the device from an e*ternal cloc+ source' DTA02 should be left unconnected while DTA0@ is driven as shown in 5igure 2 There are no requirements on the duty cycle of the e*ternal cloc+ signal' since the input to the internal cloc+ing circuitry is through a divide)by)two flip)flop' but minimum and ma*imum voltage high and low time specifications must be observed 2.3.2. FLASHMEMORY $rogramming the !# 89#52 is normally shipped with the on chip 5lash "emory array in the erased state 1i e 2 #ontentsE 55C and ready to be programmed The !# 89#52 is programmed byte 9 by) byte in programming mode 8efore the on) chip flash code memory can be re)programmed' the entire memory array must be erased electrically 2.3.3. INTERRUPTS The AT89#52 has a total of si* interrupt vectors; two e*ternal interrupts 1!=T- and !=T@2' three timer interrupts 1Timers -' @' and 22' and the serial port interrupt These interrupts are all shown in 5igure 7ach of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special 5unction &egister !7 !7 also contains a global disable bit' 7A' which disables all interrupts at once Timer 2 interrupt is generated by the logical /& of bits T52 and 7D52 in register T2#/= =either of these flags is cleared by hardware when the service routine is vectored to !n fact' the service routine may have

to determine whether it was T52 or 7D52 that generated the interrupt' and that bit will have to be cleared in software The Timer - and Timer @ flags' T5- and T5@' are set at S5$2 of the cycle in which the timers overflow The values are then polled by the circuitry in the ne*t cycle Cowever' the Timer 2 flag' T52' is set at S2$2 and is polled in the same cycle in which the timer overflows 2.3.4. SERIAL PORT USART! The serial port is full duple*' meaning it can transmit and receives simultaneously !t is also receive)buffered' meaning it can commence reception of a second byte before a previously received byte has been read from the register 1Cowever' if the first byte still hasnFt been read by the time reception of the second byte is complete' one of the bytes will be lost 2 The serial port receive and transmit registers are both accessed at Special 5unction &egister S8%5 :riting to S8%5 loads the transmit register' and reading S8%5 accesses a physically separate receive register