Data Sheet

NVIDIA C51M Mobile Integrated Graphics Processor

NVIDIA CONFIDENTIAL Prepared and Provided Under NDA

April 2005 DS-01793-001_v1.1

Document Change History

Version
1.0 1.1

Date
04/04/05 04/11/05

Responsible
JK, DV, JT, AS, MH, BH, DC, JR KK, DV

Reason for Change

Initial release. Minor edits

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Table of Contents

Preface ..........................................................................................................................ix About this Document ....................................................................................................... ix Chapter 1. Introduction to the C51M .............................................................................1 Product Overview ............................................................................................................. 1 System and Block Diagram ................................................................................................ 2 Features and Functions ..................................................................................................... 3 Primary HyperTransport Link (to CPU)............................................................................ 3 PCI Express Interface ................................................................................................... 3 DirectX 9.0c Shader Model 3.0 Graphics Processing Unit .................................................. 3 Programmable PureVideo Processor ............................................................................... 4 Display Controller ......................................................................................................... 4 Video Mixing Rendered (VMR) Scaling Pipeline ................................................................ 4 Integrated Flat Panel Interface, Dual Channel LVDS Mode ............................................... 5 Integrated Flat Panel Interface, TMDS Mode................................................................... 5 Integrated DAC CRT Mode ............................................................................................ 5 Integrated DAC SD/HDTV Encoder Mode ........................................................................ 5 Secondary HyperTransport Link ..................................................................................... 5 Integrated Clock Synthesizer ......................................................................................... 6 System and Power Management .................................................................................... 6 Power Management................................................................................................... 6 Chapter 2. Signal Descriptions .......................................................................................7 Conventions ..................................................................................................................... 8 Primary HyperTransport Interface to the CPU...................................................................... 9 Secondary HyperTransport Interface ................................................................................ 10 PCI Express Interface ..................................................................................................... 12 Integrated Flat Panel Transmitter Dual Channel LVDS Mode ............................................... 14 Integrated Flat Panel Interface TMDS Mode ...................................................................... 16 Video DAC/TV Out Signals ............................................................................................... 17 Power Supply ................................................................................................................. 18 Clocks ........................................................................................................................... 20

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TEST/JTAG Interface ...................................................................................................... 21 No Connect Interface...................................................................................................... 21 Chapter 3. Clock Domains ............................................................................................23 Clocking......................................................................................................................... 23 Chapter 4. Power Sequencing and Reset .....................................................................27 Power Sequencing and Reset Information......................................................................... 27 Chapter 5. Pin States....................................................................................................29 Signal Connections ......................................................................................................... 29 Signal States .................................................................................................................. 31 Chapter 6. Mechanical Specifications...........................................................................33 Chapter 7. AC/DC Specifications..................................................................................37 Absolute Ratings............................................................................................................. 37 Thermal Operations ........................................................................................................ 38 DC Voltage Characteristics............................................................................................... 38 AC Characteristics........................................................................................................... 39 Input Clock Characteristics .......................................................................................... 39 Output Clock Characteristics........................................................................................ 40 Interface Characteristics ............................................................................................. 41 HyperTransport Interface......................................................................................... 41 PCI Express Interface .............................................................................................. 44 Industry Standards ......................................................................................................... 49 Appendix A. Ball Listings ..............................................................................................51 Appendix B. Ballout ......................................................................................................61 Ballout (Top Left View) ................................................................................................... 62 Ballout (Top Right View) ................................................................................................. 63

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List of Figures

Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11.

System and Block Diagram .............................................................................. 2 Simple Clock Block Diagram........................................................................... 23 C51M Power Sequencing ............................................................................... 27 HyperTransport Link Sequencing.................................................................... 28 PBGA Package Drawing................................................................................. 34 Clock Timing Diagram ................................................................................... 40 HyperTransport Bus TDIFF ............................................................................ 41 HyperTransport Bus TCAD............................................................................. 42 HyperTransport Bus TSU and THD ................................................................. 42 Minimum TX Eye Timing and Voltage Compliance............................................ 46 Minimum RX Eye Timing and Voltage Compliance............................................ 49

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List of Tables

Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31.

Signal Type Codes.............................................................................................. 8 Primary HyperTransport Interface Signals to the CPU ............................................ 9 Secondary HyperTransport Interface Signals ...................................................... 10 PCI Express x16 Interface Signals...................................................................... 12 PCI Express1 x1 Interface Signals...................................................................... 12 PCI Express2 x1 Interface Signals...................................................................... 13 PCI Express Interface Signals ............................................................................ 13 Integrated Dual Channel LVDS Transmitter Interface .......................................... 14 18-Bit Single-Pixel Mode, Unbalanced ................................................................ 14 24-Bit Single-Pixel Mode, Unbalanced ................................................................ 15 18-Bit Dual-Pixel Mode, Unbalanced................................................................... 15 24-Bit Dual-Pixel Mode, Unbalanced................................................................... 16 Integrated Dual Channel TMDS Interface ........................................................... 16 Video DAC/TV Out Signals ................................................................................ 17 Power Supply Interface..................................................................................... 18 Clock Signals ................................................................................................... 20 TEST Interface Signals ..................................................................................... 21 No Connect Interface Signals ............................................................................ 21 Clock Signals ................................................................................................... 24 Signal Connections ........................................................................................... 29 Signal States.................................................................................................... 31 PBGA Package Dimensions................................................................................ 33 Absolute Ratings .............................................................................................. 37 Maximum Power Dissipation.............................................................................. 37 Thermal Operating Temperature ....................................................................... 38 Voltage Characteristics ..................................................................................... 38 AC Input Clock Characteristics........................................................................... 39 AC Output Clock Characteristics......................................................................... 40 HyperTransport Bus ......................................................................................... 43 Differential Transmitter (TX) Output Specifications.............................................. 44 Differential Receiver (RX) Output Specifications .................................................. 47

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Table 32. Table 33.

Ball Listing by Package Ball ............................................................................... 51 Ball Listing by Signal Name ............................................................................... 56

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Preface

About this Document

This document is targeted to motherboard designers and is intended to provide them with the information necessary to design an NVIDIA C51M motherboard. It contains a features list, signal description, signal states, power sequencing and RESET information, package information, AC/DC specifications, and the ball map. The information contained in this data sheet is preliminary and subject to change. Please contact your local NVIDIA Sales representative for the latest information.

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Chapter 1. Introduction to the C51M

The NVIDIA C51M is the notebook industrys first solution for providing enthusiast-class graphics features, a dedicated video processor with integrated dual channel LVDS or dual channel TMDS and HDTV encoders, and power management features within the budget of every notebook and slim form factor desktop consumer. Paired with either an AMD Opteron, Turion 64, Mobile Athlon 64, or Sempron CPU and an MCP51 media communications processor all the key features needed for computing, displaying, storing, and communicating information come together in notebooks and slim form factor desktops using the C51M.

Product Overview
The NVIDIA C51M includes the following features:

Integrated Programmable Shader model 3.0 DirectX 9 graphics processor Shader model 3.0 vertex processor Shader model 3.0 pixel processor CineFX 3.0 Intellisample AA Programmable NVIDIA PureVideo processor Integrated dual channel LVDS interface for notebook LCD panels or integrated dual channel TMDS interface for DVI monitors Integrated high definition TV encoder Integrated 300 MHz DAC for external desktop displays Primary HyperTransport link up to 800 MHz to the CPU x16 x1 x1 Secondary HyperTransport link up to 800 MHz PCI Express 16 lane link interface for external graphics processors Dual PCI Express single lane link interface with dedicated controller for ExpressCard and other peripherals Active power management Programmable clock synthesizer 25 mm 25 mm, 1.0 mm ball pitch PBGA

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NVIDIA C51M Data Sheet

Introduction

PROPRIETARY INFORMATION

Based on the award winning NVIDIA nForce4 and the GeForce 6 series of processors, the C51M represents the next level of integration by combining a graphics processor in a small, low power, space efficient package ideal for desktops and thin light notebooks.

System and Block Diagram

HyperTransport Link @ 800 MHz

HyperTransport Primary Port Interface

C51M
Dual Channel LVDS/ Dual Channel TMDS

3D iGPU HOST Display

External LCD Display/ DVI Monitor

TV/CRT DAC PureVideo

External HDTV or CRT

PCI Express x1 Root Port

x1

External PCI Express Device External PCI Express Device External PCI Express Device

PCI Express x1 Root Port

x1

PCI Express x16 Root Port

x16

HyperTransport Secondary Port Interface

Active Power Management

Integrated Clock Synthesizer

HyperTransport Link @ 800 MHz

Figure 1.
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System and Block Diagram

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NVIDIA C51M Data Sheet

Introduction

PROPRIETARY INFORMATION

Features and Functions

Primary HyperTransport Link (to CPU)

High-speed, differential, low voltage interface Communication with the AMD Opteron, Turion 64, Mobile Athlon 64, or Sempron CPUs 8 and 16 upstream and 8 and 16 downstream data paths Up to 800 MHz, for a total bandwidth of up to 6.4 GT/s Supports coherent and non-coherent data types Supports isochronous and non-isochronous data channels Supports real-time link reconnect/disconnect Clock spread spectrum capability

PCI Express Interface

Three separate PCI Express controllers with 18 total lanes, configured as one 16 and two 1 PCI Express lanes Each controller can support isochronous data WAKE# function is supported for power management 2.5 GHz support, for a total bandwidth of 2.5 Gb/s per direction per lane Clock spread spectrum capability

DirectX 9.0c Shader Model 3.0 Graphics Processing Unit

CineFX 3.0 Shading Architecture Vertex Shaders Supports Microsoft DirectX 9.0 Vertex Shader 3.0 Displacement mapping Geometry instancing Infinite length vertex programs Pixel Shaders Supports DirectX 9.0 Pixel Shader 3.0 Full pixel branching support Supports Multiple Render Targets (MRTs) Infinite length pixel programs GeForce6-Class Texture Engine Up to 16 textures per rendering pass Supports 16-bit floating point format and 32-bit floating point format Supports non-power of two textures Supports sRGB texture format for gamma textures DirectX and S3TC texture compression

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NVIDIA C51M Data Sheet

Introduction

PROPRIETARY INFORMATION

Full 128-bit studio-quality floating point precision through the entire rendering pipeline with native hardware support for 32bpp, 64bpp, and 128bpp rendering modes Intellisample 3.0 Technology2 Advanced 16 anisotropic filtering Blistering-fast antialiasing and compression performance New rotated-grid antialiasing removes jagged edges for incredible edge quality Supports advanced lossless compression algorithms for color, texture, and z-data, at even higher resolutions and frame rates Fast z-clear NVIDIA UltraShadow II technology; designed to enhance the performance of shadow-intensive games, like id Software Doom 3 Advanced thermal management and thermal monitoring

Programmable PureVideo Processor

Sixteen-way VLIW SIMD vector processor Separate scaling controller and coefficient generator Fifty new dedicated video instructions Up to 96 operations per clock MPEG video decode WMV9 decode acceleration Advanced adaptive de-interlacing High-quality video scaling and filtering Hardware accelerated MPEG-2 decoding Microsoft Video Mixing Renderer (VMR) supports multiple video windows with full video quality and features in each window

Display Controller
Full NVIDIA nView multi-display technology capability, with independent display controllers for the CRT/TV and LVDS/TMDS interfaces Each controller can drive same or different display contents to different resolutions and refresh rates

Video Mixing Rendered (VMR) Scaling Pipeline

Four-tap horizontal by five-tap vertical scaling Arbitrary number of video streams can be scaled simultaneously, each with its own scaling coefficients Scaled output can be directed to overlay, display, or FB for compositing

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NVIDIA C51M Data Sheet

Introduction

PROPRIETARY INFORMATION

Integrated Flat Panel Interface, Dual Channel LVDS Mode

Up to SXGA resolution single channel support (135 MHz @ 75 Hz) Four low voltage differential and high speed data channels One low voltage and differential clock channel Up to QXGA resolution dual channel support (266 MHz @ 60 Hz) Eight low voltage differential and high speed data channels Two low voltage and differential clock channels Support for 18-bit and 24-bit notebook LCD panels Clock spread spectrum capability

Integrated Flat Panel Interface, TMDS Mode

Up to UXGA resolution single channel support (165 MHz @ 60Hz) Three low voltage, differential data channels at up to 1.65 Gb/s One low voltage differential clock channel at up to 165 MHz Up to 330 MHz dual channel support Six low voltage differential data channels at up to 3.3 Gb/s Two low voltage differential clock channel at up to 330 MHz

Integrated DAC CRT Mode

300 MHz RAMDAC for display resolutions up to and including 1920 1440 at 75 Hz Individual RGB 10-bit DACs

Integrated DAC SD/HDTV Encoder Mode

Supports HD resolutions, 720p and 1080i RCA, S-video, component output support Support for Japanese D connector Requires 27.0 MHz crystal connected to C51M

Secondary HyperTransport Link

High-speed, differential, low voltage interface 8 and 16 upstream and 8 and 16 downstream data paths Up to 800 MHz operation Supports coherent and non-coherent data types Supports isochronous and non-isochronous data channels Supports real-time link reconnect/disconnect Clock spread spectrum capability

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NVIDIA C51M Data Sheet

Introduction

PROPRIETARY INFORMATION

Integrated Clock Synthesizer

Generates all necessary internal and external clock frequencies Based on a single 25 MHz reference clock input from the MCP51 Generates clocks for HyperTransport link, PCI Express, AMD Opteron, Turion 64, Mobile Athlon 64, or Sempron CPUs Spread spectrum capable on the following clocks: CPU + upstream HyperTransport link, PCI Express, and downstream HyperTransport link clocks Simplifies system design and motherboard layout

System and Power Management

Power Management

Supports instantly available PC (IAPC), ACPI 2.0, and PCI PM 1.1 PME message support on PCI Express links Active clock generator management Active clock tree gating and PLL power-down Integrated thermal sensor Thermal event detection (alarm) Power On Suspend (POS) or ACPI S1 support Suspend to RAM (STR) or ACPI S3 support Suspend to Disk (STD) or ACPI S4/S5 support Supports C0, C1, C2, and C3 states Supports HyperTransport link disconnect and STOP/REQ protocol Supports FID/VID cycles for CPU P-state transition and AMD CoolnQuiet

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Chapter 2. Signal Descriptions

This chapter contains the signal descriptions for the NVIDIA C51M. See Appendix A for signal listings by ball location and signal name and Appendix B for the ballout. This chapter contains the following information:

Conventions Primary HyperTransport Interface to the CPU Secondary HyperTransport Interface PCI Express Interface Integrated Dual Channel LVDS Transmitter Interface Integrated Dual Channel TMDS Transmitter Interface Video DAC Signals Power Supply Clocks TEST/JTAG Interface

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

Conventions
Following are the conventions used in describing the signals for the NVIDIA C51M: Signal Names Signal names use a mnemonic to represent the function of the signal. Active low single-ended signals are identified by a pound sign (#) after the signal name. Active high signals do not have the pound sign (#) after the signal names. Differential signals have _P (positive) or _N (complementary) suffixes to indicate the polarity within the pair. I/O Type The signal I/O type is represented as a code to indicate the operational characteristics of the signal. Table 1 lists the I/O codes used in the signal description tables.

Table 1.
Item
A DIFF I/O DIFF IN DIFF OUT I I/O O OC OD P

Signal Type Codes

Description
Analog Differential input/output Differential input Differential output Input Bidirectional input/output Output Open collector output Open drain output Power

Note:

Signals can be part of more than one interface.

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

Primary HyperTransport Interface to the CPU

Table 2.
Signal
HT_CPU_REQ#

Primary HyperTransport Interface Signals to the CPU

I/O
I

Definition
HyperTransport Link Request This asynchronous signal indicates that an external master wishes to send a transaction and the HyperTransport link should be reconnected. This signal should be an input tied to a motherboard pull-up. Please refer to the NVIDIA C51 and MCP51 Design Guide. HyperTransport Link Differential Receive Clocks These signals are the differential pairs used as the timing reference for HT_CPU_RXD[15:0] and HT_CPU_RXCTL. HT_CPU_RX_CLK1_P/HT_CPU_RX_CLK1_N is used for HT_CPU_RXD[15:8] and HT_CPU_RX_CLK0_P/HT_CPU_RX_CLK0_N is used for HT_CPU_RXD[7:0] and HT_CPU_RXCTL. When interfacing to a link width smaller than the full 16 bits, please refer to the NVIDIA C51 and MCP51 Design Guide for more details. HyperTransport Link Differential Receive Control Receive link control signal. HyperTransport Link Differential Receive Data These signals are the differential pairs used to receive the high-speed 16 bits of information from the upstream CPU. The C51M supports HyperTransport link widths of 8 and 16 bits. When interfacing to a link width smaller than the full 16-bits, please refer to the NVIDIA C51 and MCP51 Design Guide for more details. HyperTransport Link Disconnect This signal enables and disables the HyperTransport link during system state transitions. Please refer to the NVIDIA C51 and MCP51 Design Guide. HyperTransport Link Differential Transmit Clocks These signals are the differential pairs used as the timing reference for HT_CPU_TXD[15:0] and HT_CPU_TXCTL. HT_CPU_TX_CLK1_P/HT_CPU_TX_CLK1_N is used for HT_CPU_TXD[15:8] and HT_CPU_TX_CLK0_P/HT_CPU_TX_CLK0_N is used for HT_CPU_TXD[7:0] and HT_CPU_TXCTL. These clock pairs are spread spectrum capable for EMI reduction. When interfacing to a link width smaller than the full 16 bits, please refer to the NVIDIA C51 and MCP51 Design Guide for more details. HyperTransport Link Differential Transmit Control Transmit link control signal. HyperTransport Link Differential Transmit Data These signals are the differential pairs used to transmit the high-speed 16 bits of information to the upstream CPU. The C51M supports HyperTransport link widths of 8 and 16 bits. When interfacing to a link width smaller than the full 16-bits, please refer to the NVIDIA C51 and MCP51 Design Guide for more details.

HT_CPU_RX_CLK[1:0]_P HT_CPU_RX_CLK[1:0]_N

DIFF IN

HT_CPU_RXCTL_P HT_CPU_RXCTL_N HT_CPU_RXD[15:0]_P HT_CPU_RXD[15:0]_N

DIFF IN DIFF IN

HT_CPU_STOP#

OD

HT_CPU_TX_CLK[1:0]_P HT_CPU_TX_CLK[1:0]_N

DIFF OUT

HT_CPU_TXCTL_P HT_CPU_TXCTL_N HT_CPU_TXD[15:0]_P HT_CPU_TXD[15:0]_N

DIFF OUT DIFF OUT

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

Signal
HT_CPU_PWRGD

I/O
OD

Definition
CPU Power OK This signal is the Power Good/Cold Reset control for the upstream HyperTransport device. Typically this connects to an AMD Opteron, Turion 64, Mobile Athlon 64, or Sempron CPU. Please refer to the NVIDIA C51 and MCP51 Design Guide. CPU Reset This signal is the warm reset signal control for the upstream HyperTransport device. Typically this connects to an AMD Opteron, Turion 64, Mobile Athlon 64, or Sempron CPU. Please refer to the NVIDIA C51 and MCP51 Design Guide. HyperTransport Calibration Used for HyperTransport link interface pads calibration. Please refer to the NVIDIA C51 and MCP51 Design Guide. HyperTransport Calibration Used for HyperTransport link interface pads calibration. Please refer to the NVIDIA C51 and MCP51 Design Guide.

HT_CPU_RST#

OD

HT_CPU_CAL_1P2V

HT_CPU_CAL_GND

Secondary HyperTransport Interface

Table 3.
Signal
HT_MCP_REQ#

Secondary HyperTransport Interface Signals

I/O
OD

Definition
HyperTransport Link Request This asynchronous signal indicates that a master, internal to the C51M, wishes to send a transaction and the HyperTransport link should be reconnected. C51M asserts this signal when its Primary or Secondary links have a transaction pending irrespective of the current link state. Please refer to the NVIDIA C51 and MCP51 Design Guide. HyperTransport Link Differential Receive Clocks These signals are the differential pairs used as the timing reference for HT_MCP_RXD[15:0] and HT_MCP_RXCTL. HT_MCP_RX_CLK1_P/HT_MCP_RX_CLK1_N is used for HT_MCP_RXD[15:8] and HT_MCP_RX_CLK0_P/HT_MCP_RX_CLK0_N is used for HT_MCP_RXD[7:0] and HT_MCP_RXCTL. When interfacing to a link width smaller than the full 16 bits, please refer to the NVIDIA C51 and MCP51 Design Guide. HyperTransport Link Differential Receive Control Receive link control signal. HyperTransport Link Differential Receive Data These signals are the differential pairs used to receive the high-speed 16 bits of information from the downstream MCP51. The C51M supports HyperTransport link widths of 8 and 16 bits. When interfacing to a link width smaller than the full 16-bits, please refer to the NVIDIA C51 and MCP51 Design Guide.

HT_MCP_RX_CLK[1:0]_P HT_MCP_RX_CLK[1:0]_N

DIFF IN

HT_MCP_RXCTL_P HT_MCP_RXCTL_N HT_MCP_RXD[15:0]_P HT_MCP_RXD[15:0]_N

DIFF IN DIFF IN

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

Signal
HT_MCP_STOP#

I/O
I

Definition
HyperTransport Link Disconnect This signal enables and disables the HyperTransport link during system state transitions. Please refer to the NVIDIA C51 and MCP51 Design Guide. HyperTransport Link Differential Transmit Clocks These signals are the differential pairs used as the timing reference for HT_MCP_TXD[15:0] and HT_MCP_TXCTL. HT_MCP_TX_CLK1_P/HT_MCP_TX_CLK1_N is used for HT_MCP_TXD[15:8] and HT_MCP_TX_CLK0_P/HT_MCP_TX_CLK0_N is used for HT_MCP_TXD[7:0] and HT_MCP_TXCTL. These clock pairs are capable of tracking a spread spectrum input reference for EMI reduction. When interfacing to a link width smaller than the full 16 bits, please refer to the NVIDIA C51 and MCP51 Design Guide. HyperTransport Link Differential Transmit Control Transmit link control signal. HyperTransport Link Differential Transmit Data These signals are the differential pairs used to transmit the high-speed 16 bits of information to the downstream HyperTransport device. The C51M supports HyperTransport link widths of 8 and 16 bits. When interfacing to a link width smaller than the full 16-bits, please refer to the NVIDIA C51 and MCP51 Design Guide. MCP Power OK This signal is the Power Good/Cold Reset control for the upstream HyperTransport device. Typically this connects to the C51M. Please refer to the NVIDIA C51 and MCP51 Design Guide. MCP Reset This signal is the warm reset signal control for the upstream HyperTransport device. Typically this connects to the MCP51. Please refer to the NVIDIA C51 and MCP51 Design Guide. HyperTransport Calibration Used for HyperTransport Link interface pads calibration. Please refer to the NVIDIA C51 and MCP51 Design Guide. HyperTransport Calibration Used for HyperTransport Link interface pads calibration. Please refer to the NVIDIA C51 and MCP51 Design Guide.

HT_MCP_TX_CLK[1:0]_P HT_MCP_TX_CLK[1:0]_N

DIFF OUT

HT_MCP_TXCTL_P HT_MCP_TXCTL_N HT_MCP_TXD[15:0]_P HT_MCP_TXD[15:0]_N

DIFF OUT DIFF OUT

HT_MCP_PWRGD

HT_MCP_RESET#

HT_MCP_CAL_1P2V

HT_MCP_CAL_GND

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

PCI Express Interface

Table 4.
Signal
PE0_PRSNT#

PCI Express x16 Interface Signals

I/O
I

Definition
PCI Express x 16 Presence Detect This signal is the presence/hot plug presence detect of a device on the 16 PCI Express link. PCI Express x16 Reference Clock These signals are the 100 MHz differential reference clock pair for the 16 PCI Express link. PCI Express x16 Receive Data These signals are the 16 differential receive data pairs of the PCI Express link. PCI Express x16 Transmit Data These signals are the 16 differential transmit data pairs of the PCI Express link.

PE0_REFCLK_P PE0_REFCLK_N PE0_RX[15:0]_P PE0_RX[15:0]_N PE0_TX[15:0]_P PE0_TX[15:0]_N

DIFF OUT DIFF IN DIFF OUT

Table 5.
Signal
PE1_CLKREQ#

PCI Express1 x1 Interface Signals

I/O
I

Definition
PCI Express x1 Reference Clock Request This signal is used by a PCI Express device to indicate it needs the PE1_REFCLK_P and PE1_REFCLK_N to actively drive the 100 MHz reference clock. PCI Express x1 Presence Detect This signal is the hot plug presence detect of a device on a 1 PCI Express link. PCI Express x1 Reference Clock These signals are the 100 MHz differential reference clock pair for the first 1 PCI Express link. PCI Express x1 Receive Data These signals are the 1 differential receive data pair of the first 1 PCI Express link. PCI Express x1 Transmit Data These signals are the 1 differential transmit data pair of the first 1 PCI Express link.

PE1_PRSNT#

PE1_REFCLK_P PE1_REFCLK_N PE1_RX_P PE1_RX_N PE1_TX_P PE1_TX_N

DIFF OUT DIFF IN DIFF OUT

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

Table 6.
Signal
PE2_CLKREQ#

PCI Express2 x1 Interface Signals

I/O
I

Definition
PCI Express x1 Reference Clock Request This signal is used by a PCI Express device to indicate it needs the PE2_REFCLK_P and PE2_REFCLK_N to actively drive the 100 MHz reference clock. PCI Express x1 Presence Detect This signal is the hot plug presence detect of a device on a 1 PCI Express link. PCI Express x1 Reference Clock These signals are the 100 MHz differential reference clock pair for the second 1 PCI Express link. PCI Express x1 Receive Data These signals are the 1 differential receive data pair of the second 1 PCI Express link. PCI Express x1 Transmit Data These signals are the 1 differential transmit data pair of the second 1 PCI Express link.

PE2_PRSNT#

PE2_REFCLK_P PE2_REFCLK_N PE2_RX_P PE2_RX_N PE2_TX_P PE2_TX_N

DIFF OUT DIFF IN DIFF OUT

Table 7.
Signal
PE_RESET#

PCI Express Interface Signals

I/O
I A DIFF IN DIFF OUT

Definition
PCI Express Reset This signal is used Reset PCI Express links. PCI Express Termination Please refer to the NVIDIA C51 and MCP51 Design Guide. PCI Express Reference Clock Input These signals are the 100 MHz differential reference clock pair input for the PCI Express link. PCI Express Test Clock Output These signals are the differential test clock pair of the PCI Express link.

PE_CTERM_GND PE_REFCLKIN_N PE_REFCLKIN_P PE_TSTCLK_N PE_TXTCLK_P

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

Integrated Flat Panel Transmitter Dual Channel LVDS Mode

In LVDS mode, the +2.5V_IFPA and +2.5V_IFPB can be either +2.5V or +3.3V.

Table 8.
Signal
IFPAB_RSET

Integrated Dual Channel LVDS Transmitter Interface

I/O
A

Description
Reference Current Produces a reference current through an external resistor. Refer to the NVIDIA C51 and MCP51 Design Guide for the appropriate value and tolerance. LVDS Low-Voltage Differential Single Channel Data Low voltage differential and high speed single channel data outputs. LVDS Low-Voltage Differential Clock for IFPA_TXD[3:0] Low voltage differential single channel output clock used for IPFA_TXD[3:0]. LVDS Low-Voltage Differential Dual Channel Data Low voltage differential and high speed dual channel data outputs. LVDS Low-Voltage Differential Clock for IFPB_TXD[7:4] Low voltage differential dual channel output clock used for IFPB_TXD[7:4].

IFPA_TXD[3:0]_P IFPA_TXD[3:0]_N IFPA_TXC_P IFPA_TXC_N IFPB_TXD[7:4]_P IFPB_TXD[7:4]_N IFPB_TXC_P IFPB_TXC_N

DIFF OUT DIFF OUT DIFF OUT DIFF OUT

Note: The DDC and panel sequencing interface for the integrated GPU flat panel interface are connected to the MCP51 component.

The integrated LVDS channel supports LVDS/OpenLDI-compliant LCD panels. It supports 18-bit or 24-bit, single-pixel or dual-pixel mode panels, either balanced or unbalanced. Single channel panels use only IFPA signals while dual channel LVDS panels use both IFPA and IFPB signals Table 9 and Table 10 detail how the video data are mapped to the LVDS channel signals in unbalanced mode. Table 11 and Table 12 detail how the video data are mapped to the LVDS channel signals in balanced mode. For more details, refer to the OpenLDI Specification published by National Semiconductor.
Note:

Tables 9 through 12 assume Channel A is used to drive the LCD panel in single-pixel mode.

Table 9.

18-Bit Single-Pixel Mode, Unbalanced

Bit Bit Bit Bit Bit Bit Bit

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION
time0
IFPA_TXD0 IFPA_TXD1 IFPA_TXD2 IFPA_TXD3 G0 B1 DE

time1
R5 B0 VSYNC

time2
R4 G5 HSYNC

time3
R3 G4 B5

time4
R2 G3 B4

time5
R1 G2 B3

time6
R0 G1 B2

Table 10.

24-Bit Single-Pixel Mode, Unbalanced

Bit time0 Bit time1
R5 B0 VSYNC B7

Bit time2
R4 G5 HSYNC B6

Bit time3
R3 G4 B5 G7

Bit time4
R2 G3 B4 G6

Bit time5
R1 G2 B3 R7

Bit time6
R0 G1 B2 R6

IFPA_TXD0 IFPA_TXD1 IFPA_TXD2 IFPA_TXD3

G0 B1 DE Reserved

Table 11.

18-Bit Dual-Pixel Mode, Unbalanced

Bit time0 Bit time1
RU5 BU0 VSYNC RL5 BL0 CNTLE

Bit time2
RU4 GU5 HSYNC RL4 GL5 CNTLE

Bit time3
RU3 GU4 BU5 RL3 GL4 BL5

Bit time4
RU2 GU3 BU4 RL2 GL3 BL4

Bit time5
RU1 GU2 BU3 RL1 GL2 BL3

Bit time6
RU0 GU1 BU2 RL0 GL1 BL2

IFPA_TXD0 IFPA_TXD1 IFPA_TXD2 IFPA_TXD3 IFPB_TXD4 IFPB_TXD5 IFPB_TXD6 IFPB_TXD7

GU0 BU1 DE GL0 BL1 Reserved

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

Table 12.

24-Bit Dual-Pixel Mode, Unbalanced

Bit time0 Bit time1
RU5 BU0 VSYNC BU7 RL5 BL0 CNTLE BL7

Bit time2
RU4 GU5 HSYNC BU6 RL4 GL5 CNTLE BL6

Bit time3
RU3 GU4 BU5 GU7 RL3 GL4 BL5 GL7

Bit time4
RU2 GU3 BU4 GU6 RL2 GL3 BL4 GL6

Bit time5
RU1 GU2 BU3 BU7 RL1 GL2 BL3 RL7

Bit time6
RU0 GU1 BU2 BU6 RL0 GL1 BL2 RL6

IFPA_TXD0 IFPA_TXD1 IFPA_TXD2 IFPA_TXD3 IFPB_TXD4 IFPB_TXD5 IFPB_TXD6 IFPB_TXD7

GU0 BU1 DE Reserved GL0 BL1 Reserved Reserved

Integrated Flat Panel Interface TMDS Mode

In TMDS mode, the +2.5V_IFPA and +2.5V_IFPB must be +3.3V. If TMDS is not used, then it can be either +2.5V or +3.3V.

Table 13.
Signal
IFPAB_RSET

Integrated Dual Channel TMDS Interface

I/O
A

Description
TMDS Low Voltage Output Swing Current Reference This resistor sets the current reference for the output differential voltage swing level on the 6 data channels and 2 clock channel. Please refer to the NVIDIA C51G and MCP51 Design Guide for further information. Single Channel TMDS Output Data Channel [2:0] These signals are the 3 low voltage, differential, high speed output data signals for single channel TMDS or the first 3 channels in a dual channel TMDS configuration. Single channel TMDS Output Clock Channel This signal is the low voltage differential clock channel output signal for signal channel TMDS or the first clock channel in a dual channel TMDS configuration. Dual Channel TMDS Output Data Channel [2:0] These signals are the second 3 low voltage, differential, high speed output data signals in a dual channel TMDS configuration. Dual channel TMDS Output Clock Channel This signal is the second low voltage differential clock channel output signal in a dual channel TMDS configuration.

IFPA_TXD[2:0]_P IFPA_TXD[2:0]_N

DIFF OUT

IFPA_TXC_P IFPA_TXC_N

DIFF OUT

IFPB_TXD[6:4]_P IFPB_TXD[6:4]_N

DIFF OUT

IFPB_TXC_P IFPB_TXC_N

DIFF OUT

Note: The DDC and panel sequencing interface for the integrated GPU flat panel interface are connected to the MCP51 component.

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

Video DAC/TV Out Signals

Table 14.
Signal
DAC_RED DAC_GREEN DAC_BLUE

Video DAC/TV Out Signals

I/O
O

Description
Red, Green, and Blue Outputs These signals are the RGB display monitor outputs. Software configures these signals to drive either a doubly terminated or singly terminated 75-ohm load. TV Chrominance, Luminance, and Composite Outputs These signals are also the S-video analog chrominance and luminance outputs, as well as the standard composite output. HDTV Component Outputs These signals are also the HDTV component outputs. The above TV out signal mapping is the default but is fully programmable. The type of output is determined by an output load detect algorithm. Please refer to the NVIDIA C51 and MCP51 Design Guide for the specific application.

Chrominance (DAC_RED) Luminance (DAC_GREEN) Composite (DAC_BLUE) Pr (DAC_RED) Y (DAC_GREEN) Pb (DAC_BLUE)

DAC_IDUMP DAC_HSYNC DAC_RSET

P I/O A

DAC Ground Reference Local GND reference for the internal triple DACs. Horizontal Sync Horizontal sync supplied to the display monitor. Output level is 3.3V. DAC Reference Current Set A precision resistor placed between this pin and GND sets the full-scale video DAC current. Refer to the NVIDIA C51 and MCP51 Design Guide for the suggested value and tolerance of this resistor. DAC Reference Voltage A capacitor should be placed between this pin and GND. Refer to the NVIDIA C51 and MCP51 Design Guide for the suggested value and tolerance of this capacitor. Vertical Sync Vertical sync supplied to the display monitor. Output level is 3.3V. TV Encoder Reference Clock Input A 27.0 MHz series resonant crystal is connected between these two points to provide the reference clock for the TV Encoder. Alternately, an external LVTTL clock oscillator output may be driven in on signal XTAL_IN, leaving XTAL_OUT unconnected. If the internal TV Encoder is not used then XTAL_IN should be connected to GND leaving XTAL_OUT unconnected. Refer to the NVIDIA C51 and MCP51 Design Guide for crystal frequency and tolerance.

DAC_VREF

DAC_VSYNC XTAL_IN XTAL_OUT

I/O I/O

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

Power Supply
Table 15.
Signal
+1.2V_CORE

Power Supply Interface

I/O
P

Description
Core Power Rail This voltage powers the core logic of the C51M. It is derived from the main silver box PS_ON power supply rails. Isolated HyperTransport Power Rail Since the +1.2V_CORE power rail is enabled simultaneously with the +3.3V main power supply rail and before the CPU power is valid, the enable of this rail must be delayed to honor the AMD power sequence. Most NVIDIA MCP devices have timed digital sequencer outputs. These can be used to accurately control this sequence in accordance with AMD regulations and without using highly variable RC timing circuits. HyperTransport to MCP Power Rail This voltage powers the HyperTranport interface between the C51M and the MCP51. Refer to the NVIDIA C51 and MCP51 Design Guide. +1.2V PCI Express Analog Voltage This is a filtered version of the +1.2V_CORE power supply and is used to power the analog circuits of the PCI Express block. Refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design. +1.2V PCI Express Digital Voltage This is a filtered version of the +1.2V_CORE power supply and is used to power the digital circuits of the PCI Express block. Refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design. +1.2V PLL Voltage This is a filtered version of the +1.2V_CORE power supply and is used to power some of the internal PLLs. Refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design. +1.2V Core PLL Voltage This voltage powers the PLL of the core logic. It is a filtered version of the +1.2V_CORE voltage. Refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design. +1.2V CPU HT PLL Voltage This voltage powers the PLL of the HyperTransport interface to the CPU. It is a filtered version of the +1.2V_CORE voltage. Refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design. +1.2V MCP HT PLL Voltage This voltage powers the PLL of the HyperTransport interface to the MCP. It is a filtered version of the +1.2V_CORE voltage. Refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design.

+1.2V_HT

+1.2V_HTMCP

+1.2V_PEA

+1.2V_PED

+1.2V_PLL

+1.2V_PLLCORE

+1.2V_PLLHTCPU

+1.2V_PLLHTMCP

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

Signal
+1.2V_PLLIFP

I/O
P

Description
+1.2V IFP PLL Voltage This voltage powers the PLL of the integrated LVDS/TMDS block. It is a filtered version of the +1.2V_CORE voltage. Refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design. 2.5V Core Voltage This voltage is used to power the core logic of the C51M. It is derived from the main silver box PS_ON power supply rails. +2.5V Core PLL Voltage This voltage powers the core PLL. It is a filtered version of the +2.5V_CORE voltage. Refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design. +2.5V GPU PLL Voltage This voltage powers the PLL of the integrated GPU. It is a filtered version of the +2.5V_CORE voltage. Refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design. +2.5V CPU HT PLL Voltage This voltage powers the PLL of the HyperTransport interface to the CPU. It is a filtered version of the +2.5V_CORE voltage. Refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design. +2.5V IFP PLL Voltage This voltage powers the PLL of the integrated LVDS/TMDS block. It is a filtered version of the +2.5V_CORE voltage. Refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design. +3.3V Voltage This voltage is the +3.3V rail supplied by the main silver box power supply. It is used to power the +3.3V I/Os. +3.3V DAC Voltage This voltage power the video output DAC. It is a filtered version of the +3.3V power supply. Refer to the NVIDIA C51 and MCP51 Design Guide for details on the filter design. +2.5V Integrated Single Channel LVDS Voltage This voltage powers the integrated single channel LVDS block. It is a filtered version of the +2.5V_CORE voltage. +3.3V Integrated Single Channel TMDS Voltage This voltage powers the integrated single channel TMDS block. It is a filtered version of the +3.3V voltage. Please refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design. +3.3V Integrated Single Channel TMDS Voltage This voltage powers the integrated single channel TMDS block. It is a filtered version of the +3.3V voltage. Please refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design.

+2.5V_CORE

+2.5V_PLLCORE

+2.5V_PLLGPU

+2.5V_PLLHTCPU

+2.5V_PLLIFP

+3.3V

+3.3V_DAC

+2.5V_IFPA

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

Signal
+2.5V_IFPB

I/O
P

Description
+2.5V Integrated Dual Channel LVDS Voltage This voltage powers the integrated dual channel LVDS block. It is a filtered version of the +2.5V_CORE voltage. +3.3V Integrated Dual Channel TMDS Voltage This voltage powers the integrated dual channel TMDS block. It is a filtered version of the +3.3V voltage. Please refer to the NVIDIA C51 and MCP51 Design Guide for details of the filter design." Ground Ground

PE_GND GND

P P

Clocks
Table 16.
Signal
CLKIN_25MHZ

Clock Signals
I/O
I

Description
Non-Spread Reference Clock Input Typically, this clock is a buffered version of the 25 MHz crystal from the downstream MCP51. It is used as the reference for the iGPU, PCI Express, and upstream HyperTransport PLLs. Clock In 200 MHz This is the reference clock input for the PLL of the downstream HyperTransport link to the MCP51. It is spread spectrum capable. Clock Out 200 MHz These spread-spectrum capable differential clock outputs provide the HT reference inputs to the CPUs and other HT devices in the system. Please refer to the NVIDIA C51 and MCP51 Design Guide. Clock Out 200 MHz These signals are outputs and behave identically to the CLKOUT_PRI_200MHZ/CLKOUT_SEC_200MHZ signal pairs. 200 MHz Clock Out Termination Please refer to the NVIDIA C51 and MCP51 Design Guide.

CLKIN_200MHZ_P CLKIN_200MHZ_N CLKOUT_PRI_200MHZ_P CLKOUT_PRI_200MHZ_N CLKOUT_SEC_200MHZ_P CLKOUT_SEC_200MHZ_N SCLKIN_MCLKOUT_200MHZ_P SCLKIN_MCLKOUT_200MHZ_N CLKOUT_CTERM_GND

DIFF IN DIFF OUT

DIFF I/O A

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

TEST/JTAG Interface
Table 17.
Signal
IFPAB_VPROBE TEST_MODE_EN PKG_TEST JTAG_TCK

TEST Interface Signals

I/O
A I I I

Description
This should be left as a no connect. Please refer to the NVIDIA C51 and MCP51 Design Guide. This pin may be connected directly to GND. Please refer to the NVIDIA C51 and MCP51 Design Guide. This signal is pulled down to GND for normal operations. Please refer to the NVIDIA C51 and MCP51 Design Guide. JTAG Clock This signal must be pulled down to GND through a resistor for normal operation. Please refer to the NVIDIA C51 and MCP51 Design Guide. JTAG Serial Data Input This signal must be pulled up to +3.3 V through a resistor for normal operation. Please refer to the NVIDIA C51 and MCP51 Design Guide. JTAG Serial Data Output This signal must be left as a no-connect for normal operation. Please refer to the NVIDIA C51 and MCP51 Design Guide. JTAG Mode Select This signal must be pulled up to +3.3 V through a resistor for normal operation. Please refer to the NVIDIA C51 and MCP51 Design Guide. JTAG Reset This signal must be pulled down to GND through a resistor for normal operation. Please refer to the NVIDIA C51 and MCP51 Design Guide.

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST#

No Connect Interface
Table 18.
Signal
NC

No Connect Interface Signals

Description
These signals should be left as a no-connect for normal operation. Please refer to the NVIDIA C51 and MCP51 Design Guide.

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NVIDIA C51M Data Sheet

Signal Descriptions

PROPRIETARY INFORMATION

This page is blank.

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Chapter 3. Clock Domains

Clocking
Figure 2 shows the clocks that are used or generated by the NVIDIA C51M to and from the various peripherals. Table 19 lists the signals.

AMD Athlon64
200 MHz

HT
200 MHZ - 800 MHz

HT CPU
25 MHz

C51M Other PLLs

Optional 27.00 MHz TV XTAL

200 MHz

HT
200 MHz - 800 MHz

HT CPU
25.00 MHz XTAL

MCP51
Other PLLs

Figure 2.

Simple Clock Block Diagram

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NVIDIA C51G Data Sheet PROPRIETARY INFORMATION

Clock Domains

Table 19.
Clock Signal

Clock Signals
(in MHz unless noted)

Frequency
Variable 200 800

I/O
DIFF OUT

Description
HyperTransport Link Differential Transmit Clocks These clocks are used to synchronize the transmission of data to the upstream CPU. HyperTransport Link Differential Receive Clocks These clocks are used to synchronize the reception of data from the upstream CPU. HyperTransport Link Differential Transmit Clocks These clocks are used to synchronize the transmission of data to the downstream MCP. HyperTransport Link Differential Receive Clocks These clocks are used to synchronize the reception of data from the downstream MCP. PCI Express Reference Clocks These are the 100 MHz differential reference clock pairs for the x1 and 16 PCI Express links. Single Channel LVDS/TMFDS Interface Differential Clocks These are the Single Channel LVDS/TMDS interface low-voltage differential clocks that drive the flat panel. Dual Channel LVDS/TMFDS Interface Differential Clocks These are the Dual Channel LVDS/TMDS interface low-voltage differential clocks that drive the flat panel. TV Encoder Crystal This crystal oscillator generates the timing base for the optional TV encoder. 25 MHz Clock In This is the non-spread reference clock input. Typically this clock is a buffered version of the 25 MHz crystal from the downstream MCP51. It is used as the reference for the iGPU, PCI Express, and upstream HyperTransport PLLs. Clock In 200 MHz This is the spread-spectrum capable reference input clock for the PLL of the downstream HyperTransport link to the MCP. Clock Out 200 MHz These spread-spectrum capable differential clock outputs provide the HyperTransport reference inputs to the CPUs and other HyperTransport devices in the system.

HT_CPU_TX_CLK[1:0]

HT_CPU_RX_CLK[1:0]

Variable 200 - 800

DIFF IN

HT_MCP_TX_CLK[1:0]

Variable 200 800

DIFF OUT

HT_MCP_RX_CLK[1:0]

Variable 200 - 800

DIFF IN

PE[2:0]_REFCLK

100

DIFF OUT DIFF OUT

IFPA_TXC

Variable

IFPB_TXC

Variable

DIFF OUT

XTAL_IN XTAL_OUT CLKIN_25MHZ

27.0

I/O

25.0

CLKIN _200MHZ

200

DIFF IN

CLKOUT_PRI_200MHZ CLKOUT_SEC_200MHz

200

DIFF OUT

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NVIDIA C51G Data Sheet PROPRIETARY INFORMATION

Clock Domains

Clock Signal
SCLKIN_MCLKOUT_200MHZ

(in MHz unless noted)

Frequency
200

I/O
DIFF I/O

Description
Clock Out 200 MHz This becomes an output clock which behaves identically to the CLKOUT_PRI_200MHZ/CLKOUT_SEC_200M HZ signals. PCI Express Reference Clock Input These signals are the 100 MHz differential reference clock pair input for the PCI Express link. PCI Express Test Clock Output These signals are the differential test clock pair of the PCI Express link. JTAG Clock This signal must be pulled down to GND through a resistor for normal operation.

PE_REFCLKIN

100

DIFF IN

PE_TSTCLK

100

DIFF OUT

JTAG_TCK

Variable

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NVIDIA C51G Data Sheet PROPRIETARY INFORMATION

Clock Domains

This page is blank.

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Chapter 4. Power Sequencing and Reset

Power Sequencing and Reset Information

Please refer to the NVIDIA C51and MCP51 Design Guide as a lot of information pertaining to the Power Sequencing and RESET are dependent upon motherboard design implementations.

CPU VREG

VID

AMD K8
HT_CPU_STOP#

MEM VREG

HT_CPU_PWRGD

C51M
HT_MCP_PWRGD

HT VREG

HT_MCP_RESET#

CPUVDD_EN

HT_VLD

Power Supply

PWRGD SLP_S3# PWRGD_SB

MCP51

HTVDD_EN MEM_VLD SLP_S5#

Figure 3.

C51M Power Sequencing

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NVIDIA C51G Data Sheet PROPRIETARY INFORMATION

Power Sequencing and Reset

AMD K8
HT_CPU_STOP# CTL DATA CLK CTL DATA CLK

C51M
HT_MCP_STOP# CTL DATA CLK CTL DATA CLK HT_MCP_REQ#

MCP51

Figure 4.

HyperTransport Link Sequencing

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Chapter 5. Pin States

Signal Connections
Table 20 lists the signal connections and Table 21 list the signal states.

Table 20.
Signal
HT_CPU_REQ#

Signal Connections
OD = Open Drain I = Input O = Output OC = Open Collector

Notes: I/O = Bidirectional

I/O
I OD DIFF IN DIFF IN DIFF IN DIFF OUT DIFF OUT DIFF OUT OD OD OD I DIFF IN DIFF IN DIFF IN DIFF OUT DIFF OUT DIFF OUT I I I DIFF OUT DIFF IN

Voltage Tolerance Rail

+2.5V +2.5V +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +2.5V +2.5V +2.5V +3.3V +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +3.3V +3.3V +3.3V

Voltage Drive Rail

+2.5V +2.5V

HT_CPU_STOP# HT_CPU_RX_CLK[1:0] HT_CPU_RXCTL HT_CPU_RXD[15:0] HT_CPU_TX_CLK[1:0] HT_CPU_TXCTL HT_CPU_TXD[15:0] HT_CPU_PWRGD HT_CPU_RESET# HT_MCP_REQ# HT_MCP_STOP# HT_ MCP_RX_CLK[1:0] HT_ MCP_RX_CTL HT_ MCP_RXD[15:0] HT_ MCP_TX_CLK[1:0] HT_ MCP_TX_CTL HT_ MCP_TXD[15:0] HT_ MCP_PWRGD HT_ MCP_RESET# PE0_PRSNT# PE0_REFCLK PE0_RX[15:0]

+1.2V_HT +1.2V_HT +1.2V_HT +2.5V +2.5V +2.5V

+1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP

+1.2V +1.5V_PE_A

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NVIDIA C51G Data Sheet PROPRIETARY INFORMATION

Pin States

Notes: I/O = Bidirectional

OD = Open Drain

I = Input

O = Output

OC = Open Collector

Signal
PE0_TX[15:0] PE1_CLKREQ# PE1_PRSNT# PE1_REFCLK PE1_RX PE1_TX PE2_CLKREQ# PE2_PRSNT# PE2_REFCLK PE2_RX PE2_TX PE_REFCLKIN PE_RESET# IFPA_TXC IFPA_TXD[3:0] IFPB_TXC IFPB_TXD[7:4] DAC_RED DAC_GREEN DAC_BLUE DAC_HSYNC DAC_VSYNC XTAL_IN XTAL_OUT CLKIN_25MHZ CLKIN_200MHZ CLKOUT_PRI_200MHZ CLKOUT_SEC_200MHZ SCLKIN_MCLKOUT_ 200MHZ

I/O
DIFF OUT I I DIFF OUT DIFF IN DIFF OUT I I DIFF OUT DIFF IN DIFF OUT DIFF IN O DIFF OUT DIFF OUT DIFF OUT DIFF OUT O

Voltage Tolerance Rail

+1.5V_PE_A +3.3V +3.3V

Voltage Drive Rail

+1.5V_PE_A

+1.2V +1.5V_PE_A +1.5V_PE_A +3.3V +3.3V +3.3V +1.5V_PE_A +1.5V_PE_A +1.5V_PE_A +3.3V +2.5V/+3.0V +2.5V/+3.0V +2.5V/+3.0V +2.5V/+3.0V +3.3V +3.3V +3.3V +3.3V +3.3V +2.5V +2.5V +3.3V +3.3V +2.5V +2.5V +2.5V +2.5V +2.5V +2.5V +3.3V LVDS/TMDS Clock LVDS/TMDS Data LVDS/TMDS Clock LVDS/TMDS Data +3.3V +3.3V +3.3V +3.3V +3.3V +2.5V +2.5V +1.5V_PE_A +1.2V +1.5V_PE_A

I/O I/O I/O

I DIFF IN DIFF OUT DIFF OUT DIFF I/O

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NVIDIA C51G Data Sheet PROPRIETARY INFORMATION

Pin States

Signal States
Table 21.
Notes:

Signal States
I/O = Bidirectional L = Low I O I I I O Z Z L/H L H De-asserted at least 1 uS before HT_RESET O O O O O O I I I O I Z I I O I Z I I O I = Input H=High O = Output OC = Open Collector
S1 (POS)

Z = Tri-state U = Unpowered

OD = Open Drain
S4/S5 (SOFF)

Signal
HT_CPU_REQ# HT_CPU_STOP# HT_CPU_RX_CLK[1:0] HT_CPU_RXCTL HT_CPU_RXD[15:0] HT_CPU_TX_CLK[1:0] HT_CPU_TXCTL HT_CPU_TXD[15:0] HT_CPU_PWRGD HT_CPU_RESET# HT_MCP_REQ# HT_MCP_STOP#

During Reset

After RST (SO)

S3 (STR)

I O I I I O O O O H O O

I L I I I O O O O H O O

U U U U U U U U U U U U

U U U U U U U U U U U U

HT_ MCP_RX_CLK[1:0] HT_ MCP_RX_CTL HT_ MCP_RXD[15:0] HT_ MCP_TX_CLK[1:0] HT_ MCP_TX_CTL HT_ MCP_TXD[15:0] HT_ MCP_PWRGD HT_ MCP_RESET# PE0_PRSNT# PE0_REFCLK PE0_RX[15:0] PE0_TX[15:0] PE1_CLKREQ# PE1_PRSNT# PE1_REFCLK PE1_RX PE1_TX PE2_CLKREQ# PE2_PRSNT# PE2_REFCLK

O O O O O O I I I O I O I I O I O I I O

O O O O O O I I I O I O I I O I O I I O

U U U U U U U U U U U U U U U U U U U U

U U U U U U U U U U U U U U U U U U U U

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NVIDIA C51G Data Sheet PROPRIETARY INFORMATION

Pin States

Notes:

Z = Tri-state U = Unpowered

I/O = Bidirectional L = Low I Z I L O O O O O O O O O Z O I I O O Z

I = Input H=High

O = Output

OC = Open Collector
S1 (POS)

OD = Open Drain
S4/S5 (SOFF)

Signal
PE2_RX PE2_TX PE_REFCLKIN PE_RESET# IFPA_TXC IFPA_TXD[3:0] IFPB_TXC IFPB_TXD[7:4] DAC_RED DAC_GREEN DAC_BLUE DAC_HSYNC DAC_VSYNC XTAL_IN XTAL_OUT CLKIN_25MHZ CLKIN_200MHZ CLKOUT_PRI_200MHZ CLKOUT_SEC_200MHZ SCLKIN_MCLKOUT_ 200MHZ

During Reset

After RST (SO)

S3 (STR)

I O I O O O O O O O O O O Z O I I O O I/O

I O I O O O O O O O O O O Z O I I O O I/O

U U U U U U U U U U U U U U U U U U U U

U U U U U U U U U U U U U U U U U U U U

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Chapter 6. Mechanical Specifications

The C51M is a 25 25 package with 468 balls at a 1mm ball pitch. Table 22 lists the package dimensions and Figure 9 shows the package drawings.

Table 22.
Ref
A A1 A2 A5 D/E D1/E1 WxL WxR WyT WyB e b aaa ccc ddd eee fff

PBGA Package Dimensions

Dimensions in Millimeter Min
2.25 0.43 0.82 0.46 24.30

Dimensions in Inches Min

0.089 0.017 0.032 0.018 0.857

Nom
2.50 0.52 0.87 0.53 24.50 23.00 BASIC 3.1 BASIC 3.5 BASIC 3.1 BASIC 4.6 BASIC 1.00 BASIC

Max
2.65 0.60 0.95 0.58 24.70

Nom
0.098 0.020 0.034 0.021 0.985 0.906 BASIC 0.12 BASIC 0.14 BASIC 0.12 BASIC 0.18 BASIC 0.039 BASIC

Max
0.104 0.024 0.037 0.023 0.972

0.51

0.60 0.20 0.35 0.20 0.30 0.10

0.74

0.020

0.024 0.006 0.014 0.006 0.012 0.004

0.029

Total Number of Balls: 468 Package Size: 25 mm 25 mm

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NVIDIA C51G Data Sheet PROPRIETARY INFORMATION

Mechanical Specifications

Top view

Bottom view

Figure 5.

PBGA Package Drawing

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NVIDIA C51G Data Sheet PROPRIETARY INFORMATION

Mechanical Specifications

1. Controlling dimension: Millimeter 2. Primary datum C and seating plane are defined by the spherical

crowns of the solder balls.

3. Dimension b is measured at the maximum solder ball diameter,

parallel to primary datum C.

4. There must be a minimum clearance of 0.15 mm (0.060 in.) between

the edge of the solder ball and the body edge.

5. Die size approximately 6.7 x 8.3 mm (0.26 x 0.33 in.) 6. Die pattern of pin 1 fiducial is for reference only. 7. All passive locations shown. Some or all locations may not be

populated.
8. Drawing not to scale.

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NVIDIA C51G Data Sheet PROPRIETARY INFORMATION

Mechanical Specifications

This page is blank.

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Chapter 7. AC/DC Specifications

Absolute Ratings
The NVIDIA C51M should not be subjected to conditions exceeding the absolute maximum ratings listed in Table 23. Exceeding the conditions listed can damage the functionality and affect the long-term reliability of the part.

Table 23.
Parameter

Absolute Ratings
Min
0 C -50 C -0.5 V -0.5 V -0.5 V -0.5 V -0.5 V -0.5 V

Max
110 C 150 C 1.3 V 2.7 V 3.6 V 1.3 V 2.7 V 3.6 V

Case temperature under bias Storage temperature Voltage on any 1.2 V pin with respect to ground Voltage on any 2.5 V pin with respect to ground Voltage on any 3.3 V pin with respect to ground 1.2 V supply 2.5V supply 3.3 V supply

Table 24.
C51M

Maximum Power Dissipation

Maximum
7 W to 10 W

Power Dissipation
Note: These maximum power numbers are estimates.

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

Thermal Operations
The thermal operating temperature range is given in Table 25.

Table 25.
Characteristic

Thermal Operating Temperature

Range
0C to TBD

Thermal operating temperature (TCASE)

DC Voltage Characteristics
Table 26 lists the voltage characteristics for NVIDIA C51M.

Table 26.
Signal
+1.2V_CORE +1.2V_HT +1.2V_HTMCP +1.2V_PEA +1.2V_PED +1.2V_PLL

Voltage Characteristics
Min
1.14 V 1.14 V 1.14 V 1.14 V 1.14 V 1.14 V 1.14 V 1.14 V 1.14 V 2.3 V 2.3 V/+3.0V 2.3 V/+3.0V 2.3 V 2.3 V 2.3 V 2.3 V 3.0 V 3.0 V

Max
1.26 V 1.26 V 1.26 V 1.26 V 1.26 V 1.26 V 1.26 V 1.26 V 1.26 V 2.7 V 2.7 V/+3.3V 2.7 V/+3.3V 2.7 V 2.7 V 2.7 V 2.7 V 3.3 V 3.3 V

Range
0.06 V 0.06 V 0.06 V 0.06 V 0.06 V 0.06 V 0.06 V 0.06 V 0.06 V 0.20 V 0.20 V/0.3V 0.20 V/0.3V 0.20 V 0.20 V 0.20 V 0.20 V 0.3 V 0.3 V

+1.2V_PLLCORE +1.2V_PLLHTMCP +1.2V_PLLIFP +2.5V_CORE +2.5V_IFPA +2.5V_IFPB +2.5V_PLLCORE +2.5V_PLLGPU +2.5V_PLLHTCPU +2.5V_PLLIFP +3.3V +3.3V_DAC

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

AC Characteristics
This section contains the following AC specifications: Input clock characteristics Output clock characteristics Interface characteristics HyperTransport Interface PCI Express Interface

Input Clock Characteristics

Table 27 provides the input clock characteristics.

Table 27.
Clock

AC Input Clock Characteristics

Characteristic
Clock frequency Clock period Clock high time Clock low time Clock rise time Clock fall time 17 ns 17 ns 1 ns 1 ns 25 MHz 40 ns 18 ns 18 ns 1 ns 1 ns 200 MHz 5 ns 2.25 ns 2.25 ns 100 MHz 10 ns 4.5 ns 4.5 ns 200 MHz 5 ns 2.25 ns 2.25 ns 2.75 ns 2.75 ns 55/45 duty cycle 55/45 duty cycle 5.5 ns 5.5 ns 55/45 duty cycle 55/45 duty cycle 2.75 ns 2.75 ns 55/45 duty cycle 55/45 duty cycle 22 ns 22 ns 4 ns 4 ns 55/45 duty cycle 55/45 duty cycle

Min

Typical
27 MHz 37 ns

Max

Comments

27MHz Crystal (XTAL_IN/XTAL_OUT)

20 ns 20 ns 4 ns 4 ns

55/45 duty cycle 55/45 duty cycle

CLKIN_25MHZ

Clock frequency Clock period Clock high time Clock low time Clock rise time Clock fall time

CLKIN_200MHZ

Clock frequency Clock period Clock high time Clock low time

PE_REFCLKIN

Clock frequency Clock period Clock high time Clock low time

SCLKIN_MCLKOUT_ 200MHZ

Clock frequency Clock period Clock high time Clock low time

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

Output Clock Characteristics

Table 28 lists the AC output clock characteristics and Figure 8 shows clock timing.

Table 28.
Clock

AC Output Clock Characteristics

Characteristic
Clock frequency Clock period Clock high time Clock low time Clock rise time Clock fall time 2.25 ns 2.25 ns TBD TBD 100 MHz 10 ns 4.5 ns 4.5 ns 200 MHz 5 ns 2.25 ns 2.25 ns TBD TBD 2.75 ns 2.75 ns TBD TBD 55/45 duty cycle 55/45 duty cycle 5.5 ns 5.5 ns 55/45 duty cycle 55/45 duty cycle

Min

Typical
200 MHz 5 ns

Max

Comments

CLKOUT_PRI_200MHZ CLKOUT_SEC_200MHZ

2.75 ns 2.75 ns TBD TBD

55/45 duty cycle 55/45 duty cycle

PE[2:0]_REFCLK

Clock frequency Clock period Clock high time Clock low time

SCLKIN_MCLKOUT_ 200 MHZ

Clock frequency Clock period Clock high time Clock low time Clock rise time Clock fall time

CLK Period CLK High VHIGH CLK Rising Edge VLOW CLK Falling Edge CLK Low

Figure 6.

Clock Timing Diagram

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

Interface Characteristics
The AC interface characteristics are explained in the following tables and diagrams.

HyperTransport Interface
The HyperTransport interface is compliant with the HyperTransport I/O Link Specification published by the HyperTransport Technology Consortium. Refer to that document for full details of the interface timing. NVIDIA C51M meets the timing requirements for transmit and receive up to a link speed of 3200 MT/s.

TDIFF

Figure 7.

HyperTransport Bus TDIFF

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

TCADV_max

CLKOUT

CAD/CTLOUTLATE

CAD/CTLOUTEARLY

TCADV_min

Figure 8.

HyperTransport Bus TCAD

CLKIN

CAD/CTLOUT

TSU_max

THD_max

Figure 9.

HyperTransport Bus TSU and THD

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

Table 29.
TODIFF

HyperTransport Bus
Link Speed
800 MT/s 1200 MT/s 1600 MT/s 2000 MT/s 2400 MT/s 3200 MT/s 800 MT/s 1200 MT/s 1600 MT/s 2000 MT/s 2400 MT/s 3200 MT/s 800 MT/s 1200 MT/s 1600 MT/s 2000 MT/s 2400 MT/s 3200 MT/s 800 MT/s 1200 MT/s 1600 MT/s 2000 MT/s 2400 MT/s 3200 MT/s 800 MT/s 1200 MT/s 1600 MT/s 2000 MT/s 2400 MT/s 3200 MT/s 800 MT/s 1200 MT/s 1600 MT/s 2000 MT/s 2400 MT/s 3200 MT/s 800 MT/s 1200 MT/s 1600 MT/s 2000 MT/s 2400 MT/s 3200 MT/s 695 467 345 280 213 166 460 312 225 194 166 116 460 312 225 194 166 116 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps 250 ps 215 ps 175 ps 153 ps 138 ps 110 ps 250 215 175 153 138 110 ps ps ps ps ps ps

Symbol Characteristic
Output differential skew

Min

Max
70 70 70 60 60 60 90 90 90 65 65 65 ps ps ps ps ps ps ps ps ps ps ps ps

Comments

TIDIFF

Input differential skew

TCADV

Transmitter output CAD/CTLOUT valid relative to CLKOUT

1805 ps 1200 ps 905 ps 720 ps 620 ps 459 ps

TCADVRS

Receiver input CADIN valid time to CLKIN

TCADVRH

Receiver input CADIN valid time from CLKIN

TSU

Receiver input setup time

THD

Receiver input hold time

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

PCI Express Interface

The PCI Express interface is compliant with the PCI Express Base Specification published by the PCI SIG. Refer to that document for full details of the interface timing. The NVIDIA C51M meets the timing requirements for transmit and receive at a link speed of 2.5 Gb/s.

Table 30.
Symbol

Differential Transmitter (TX) Output Specifications

Parameter
Unit interval

Min
399.88

Nom
400

Max
400.12

Units
ps

Comments
Each UI is 400ps +/-300ppm. UI does not account for SSC (spread spectrum clock) dictated variations. See Note 1. VTX-DIFFp-p = 2*|VTX-D+ - VTX-D-|. See Note 2. This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. See Note 2. The maximum transmitter jitter can be derived as TTX-MAX
JITTER

UI

VTX-DIFFp-p VTX-DE-RATIO

Differential peak-to-peak output voltage De-emphasized differential output voltage (ratio)

0.800 -3.0 -3.5

1.2 -4.0

V dB

VTX-EYE

Minimum TX eye width

0.70

UI

= 1 TTX-EYE = 0.3 UI.

See Notes 2 and 3.

VTX-EYE-MEDIAN-TOMAX-JITTER

Maximum time between jitter median and maximum deviation from the median

0.15

UI

Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to an appropriate average TX UI. See Notes 2 and 3. See Notes 2 and 5.

VTX-RISE, VTX-FALL VTX-CM-ACp

D+/D- TX output rise/fall time AC peak common mode output voltage

0.125 20

UI mV

VTX-CM-ACp = |VTX-D+ + VTX-D-|/2 VTX-CM-DC VTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D-|/2 during L0. See Note 2.

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

Symbol

Parameter
Absolute delta of DC common mode voltage during L0 and electrical idle

Min
0

Nom

Max
100

Units
mV

Comments
DC[during Electrical Idle]

VTX-CM-DC-ACIVE-IDLEDELTA

|VTX-CM-DC [during L0] VTX-CM-IDLE| <= 100 mV

VTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D-|/2 [L0] VTX-CM-IDLE-DC = DC(avg) of |VTX-D+ + VTX-D-|/2 [Electrical Idle]. See Note 2.

VTX-CM-DC-LINE-DELTA

Absolute delta of DC common mode voltage between D+ and D-

25

mV

DC-D-[during L0]|

|VTX-CM-DC-D+ [during L0] VTX-CM-IDLE<= 25 mV

VTX-CM-DC-D+ = DC(avg) of |VTX-D+| [during L0] VTX-CM-DC-D- = DC(avg) of |VTXD-|

[during L0].

See Note 2. VTX-IDLE-DIFFp Electrical idle differential peak output voltage The amount of voltage change allowed during receiver detection 0 20 mV VTX-IDLE-DIFFp = |VTX-IDLE-D+ - VTX| <= 20 mV See Note 2.
IDLE-D-

VTX-RCV-DETECT

600

mV

The total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. See Figure 8. Minimum time a transmitter must be electrical idle. After sending an electrical idle ordered-set, the transmitter must meet all electrical idle specifications within this time. Maximum time spent in electrical idle before initiating a receiver detect sequence. See Figure 8. Measured over 50 MHz to 1.25 GHz. See Note 4. Measured over 50 MHz to 1.25 GHz. See Note 4. TX DC differential mode low impedance. TX DC high impedance.

VTX-IDLE-MIN VTX-IDLE-SET-TO-IDLE

Minimum time spec in electrical idle Maximum time to transition to a valid electrical idle after sending an electrical idle ordered set Maximum time spent in electrical idle before initiating a receiver detect sequence Differential return loss

50 20

UI UI

VTX-IDLE-RCVDETECT-MAX

100

ms

RLTX-DIFF

12

dB

RLTX-CM

Common mode return loss

dB

ZTX-DIFF-DC ZTX-COM-High-IMP-DC

DC differential TX impedance Transmitter common mode high impedance state (DC) Lane-to-lane skew

80 5

100

120 20

LTX-SKEW

500

ps

Between any two lanes within a single transmitter.

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

Symbol
CTX

Parameter
AC coupling capacitor

Min
75

Nom

Max
200

Units
pF

Comments
All transmitters shall be AC coupled. The AC coupling is required either within the media or within the transmitting component itself.

Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 4-31 of the PCI Express Base Specification Revision 1.0 and measured over any 250 consecutive TX UIs. (Also refer to the Transmitter Compliance Eye Diagram shown in Figure 4-30 of the PCI Express Base Specification Revision 1.0.) 3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX =0.30 UI for the transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-TO-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the average time value. 4. The transmitter output impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements is 50 ohms to ground for both the D+ and D- line (i.e., as measured by a Vector Network Analyzer with 50 ohm probes see Figure 4-31 of the PCI Express Base Specification Revision 1.0). Note that the series capacitor CTX is optional for the return loss measurement. 5. Measured between 20%-80% at transmitter package pins into a test load as shown in Figure 4-31 for both VTX-D+ and VTX-D-.

VTX-DIFF = 0 mV (D+ D- Crossing Point)

[Transition Bit] VTX-DIFFp-p-MIN = 800 mV

VTX-DIFF = 0 mV (D+ D- Crossing Point)

[De-emphasized Bit] 566 mV (3dB) >= VTX-DIFFp-p-MIN >= 505 mV (4dB)

[Transition Bit] VTX-DIFFp-p-MIN = 800 mV

0.7 UI = UI - 0.3 UI(JTX-TOTAL-MAX)

Figure 10.

Minimum TX Eye Timing and Voltage Compliance

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

Table 31.
Symbol

Differential Receiver (RX) Output Specifications

Parameter
Unit interval

Min
399.88

Nom
400

Max
400.12

Units
ps

Comments
Each UI is 400ps +/-300 ppm. UI does not account for SSC dictated variations. See Note 6. V RX-DIFFp-p = 2*|VRX-D+ - VRX-D-|. See Note 7. The maximum interconnect media and transmitter jitter can be tolerated by the receiver can be derived as T RX-MAX JITTER = 1 TRX-EYE = 0.6 UI. See Notes 7 and 8.

UI

VRX-DIFFp-p VRX-EYE

Differential input peak-topeak voltage Minimum RX eye width

0.175 0.40

1.2

V UI

VTX-EYE-MEDIAN-TOMAX-JITTER

Maximum time between the jitter median and maximum deviation from the median

0.3

UI

Jitter is defined as the measurement variation of the crossing points (V RX-DIFFp-p = 0 V) in relation to an appropriate average TX UI. See Notes 7 and 8. VRX-CM-ACp = |VRX-D+ + VRX-D-|/2 VRX-CM-DC VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D-|/2 during L0. See Note 7. Measured over 50 MHz to 1.25 GHz. See Note 9. Measured over 50 MHz to 1.25 GHz. See Note 9. RX DC differential mode low impedance. See Note 10. RX DC common mode impedance 50 ohms +/-20% tolerance. See Note 7 and 10. RX DC common mode impedance allowed when the receiver terminations are first powered on. See Note 11 RX DC common mode impedance when the receiver terminations are not powered (i.e., no power). See Note 12 VRX-IDLE-DET-DIFFp-p = 2*| VRXD+ - VRX-D-| Measured at the package pins of the receiver.

VRX-CM-ACp

AC peak common mode input voltage

150

mV

RL R

RX-DIFF

Differential return loss

15

dB

RX-CM

Common mode return loss

dB

ZRX-DIFF-DC ZRX-COM-DC

DC differential RX impedance DC input common mode input impedance

80

100

120

40

50

60

ZRX-COM-INITIAL-DC

Initial DC input common mode input impedance

50

60

ZRX-COM-HIGH-IMP-DC

Powered down DC input common mode input impedance

200

VRX-IDLE-DET-DIFFp-p

Electrical idle threshold

65

175

mV

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

Symbol

Parameter
Unexpected electrical idle enter detect threshold integration time

Min

Nom

Max
10

Units
ms

Comments
An unexpected electrical idle (VRX-DIFFp-p < VRX-IDLE-DETmust be recognized no longer than VRX-IDLE-DET-OFFENTERTIME to signal an unexpected idle condition.
DIFFp-p)

TRX-IDLE-DET-OFFENTERTIME

LTX-SKEW

Lane-to-lane skew

20

ns

Across all lanes on a port. This includes variation in the length of a skip ordered-set (e.g., COM and 1 to 5 SKP symbols) at the RX as well as any delay differences arising from the interconnect itself.

Notes: 6. No test load is necessarily associated with this value. 7. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 4-31 of the PCI Express Base Specification Revision 1.0 should be used as the RX device when taking measurements (Also refer to the Receiver Compliance Eye Diagram shown in Figure 4-32 of the PCI Express Base Specification Revision 1.0). If the clocks to the RX and TX are not derived from the same clock chip the TX UI must be used as a reference for the eye diagram. 8. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget of the TX and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-TO-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total 0.60 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the average time value. If the clocks to the RX and TX are not derived from the same clock chip, the appropriate average TX UI must be used as the reference for the eye diagram. 9. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements is 50 ohms to ground for both the D+ and D- line (i.e., as measured by a Vector Network Analyzer with 50 ohm probes see Figure 4-31 of the PCI Express Base Specification Revision 1.0). Note that the series capacitor CTX is optional for the return loss measurement. 10. Impedance during all operating conditions. 11. The RX DC common mode impedance that must be present when the receiver terminations are first enabled to ensure that the receiver-detect occurs properly. Compensation of this impedance can start immediately and the (ZRX-COM-DC) RX DC common mode impedance must be within the specified range by the time Detect is entered. 12. The RX DC common mode impedance that exists when the receiver terminations are disabled or when no power is present. This helps ensure that the receiver-detect circuit does not falsely assume a receiver is powered on when it is not.

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

VRX-DIFF = 0 mV (D+ D- Crossing Point)

VRX-DIFF = 0 mV (D+ D- Crossing Point)

VRX-DIFFp-p-MIN > 175 mV

0.4 UI = TRX-EYE-MIN

Figure 11.

Minimum RX Eye Timing and Voltage Compliance

Industry Standards
The following industry standard documents are referenced in this document. You should reference these as well as this document. HyperTransport I/O Link Specification Revision 1.03, HyperTransport Technology Consortium EIA/JEDEC Standard EIA/JESD8-5 October 1995

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NVIDIA C51G Data Sheet

AC/DC Specifications

PROPRIETARY INFORMATION

This page is blank.

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Appendix A. Ball Listings

Table 32 provides the ball listing by package ball and Table 33 provides the ball listing by the signal name.

Table 32.
Ball
A2 A3 A5 A6 A9 A10 A11 A14 A15 A16 A19 A20 A22 A23 B1 B2 B3 B4 B5 B6 B7 B9 B10

Ball Listing by Package Ball

Ball
B11 B12 B13 B14 B15 B16 B18 B19 B20 B21 B22 B23 B24 C1 C2 C3 C4 C5 C6 C7 C8 C9

Signal Name
+1.2V_PLL +1.2V_PEA DAC_RED DAC_BLUE +3.3V_DAC IFPB_TXC_P IFPB_TXD4_N IFPA_TXD2_P IFPA_TXD0_P IFPAB_VPROBE JTAG_TRST# SCLKIN_MCLKOUT_ 200MHZ_P CLKOUT_SEC_ 200MHZ_P GND GND +1.2V_PLL +1.2V_PEA +1.2V_PED +1.2V_CORE DAC_GREEN DAC_HSYNC XTAL_OUT IFPB_TXC_N

Signal Name
IFPB_TXD4_P IFPB_TXD7_P IFPA_TXC_N IFPA_TXD2_N IFPA_TXD0_N +2.5V_CORE JTAG_TMS JTAG_TDI SCLKIN_MCLKOUT_ 200MHZ_N CLKOUT_SEC__ 200MHZ_N CLKOUT_ CTERM_GND CLKOUT_PRI_ 200MHZ_N CLKOUT_PRI_ 200MHZ_P GND +1.2V_PLL +1.2V_PLL +1.2V_PEA +1.2V_PED +1.2V_CORE DAC_VSYNC DAC_IDUMP XTAL_IN

Ball
C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 D1 D2 D3 D4 D5 D6 D7 D8 D9 D11

Signal Name
+3.3V GND IFPB_TXD7_N IFPB_TXD6_N IFPA_TXC_P IFPA_TXD1_N +2.5V_CORE TEST_MODE_EN JTAG_TCK JTAG_TDO GND +1.2V_HT GND HT_CPU_TXD0_P HT_CPU_TXD0_N PE0_PRSNT# PE_CTERM_GND PE1_CLKREQ# +1.2V_PLL +1.2V_PEA +1.2V_PED +1.2V_CORE DAC_RSET DAC_VREF GND

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NVIDIA C51G Data Sheet

Ball Listings

PROPRIETARY INFORMATION

Ball
D13 D15 D17 D18 D19 D20 D21 D22 D23 D24 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 F1 F2 F3 F4 F6 F7 F8 F9 F10

Signal Name
IFPB_TXD6_P IFPA_TXD1_P PKG_TEST +3.3V GND HT_CPU_RESET# HT_CPU_TXD8_P HT_CPU_TXD8_N HT_CPU_TXD1_P HT_CPU_TXD1_N PE1_PRSNT# PE2_PRSNT# PE2_CLKREQ# +1.2V_PLL +1.2V_PEA +1.2V_PED +1.2V_CORE +1.2V_CORE +1.2V_CORE NC GND IFPB_TXD5_P IFPA_TXD3_N GND +2.5V_PLLIFP NC GND HT_CPU_PWRGD HT_CPU_TXD9_N HT_CPU_TXD10_N HT_CPU_TXD2_P HT_CPU_TXD2_N PE_TSTCLK_P PE_TSTCLK_N PE_GND PE_GND +1.2V_PLL +1.2V_PEA +1.2V_PEA +1.2V_PEA +1.2V_CORE

Ball
F11 F12 F13 F14 F15 F16 F17 F18 F19 F21 F22 F23 F24 G1 G2 G3 G4 G5 G6 G7 G8 G9 G11 G13 G15 G17 G18 G19 G20 G21 G22 G23 G24 H2 H3 H4 H6 H8 H9 H10 H11

Signal Name
+1.2V_CORE NC IFPB_TXD5_N IFPA_TXD3_P IFPAB_RSET GND NC HT_CPU_REQ# HT_CPU_TXD9_P HT_CPU_TXD10_P GND HT_CPU_TXD3_P HT_CPU_TXD3_N PE_RESET# PE1_REFCLK_P PE1_REFCLK_N PE1_TX_P PE1_TX_N PE1_RX_P +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_CORE GND +2.5V_IFPA NC HT_CPU_STOP# HT_CPU_TXD11_N HT_CPU_TXD11_P HT_CPU_TX_CLK1_N HT_CPU_TX_CLK1_P HT_CPU_TX_CLK0_P HT_CPU_TX_CLK0_N PE2_REFCLK_P PE2_REFCLK_N PE2_TX_P PE1_RX_N PE_GND PE_GND +1.2V_PLL +1.2V_CORE

Ball
H12 H13 H14 H15 H16 H17 H19 H21 H22 H23 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K6 K8 K9 K16 K17 K19 K21

Signal Name
+2.5V_PLLCORE +2.5V_PLLGPU GND +2.5V_IFPB +1.2V_PLLIFP +1.2V_HT GND GND HT_CPU_TXD4_P HT_CPU_TXD4_N PE2_TX_N PE2_RX_P PE0_RX1_N PE0_RX1_P PE0_RX0_N PE0_RX0_P PE0_RX2_N +1.2V_PLL +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE GND GND GND HT_CPU_TXD12_N HT_CPU_TXD12_P +1.2V_HT HT_CPU_TXD5_P HT_CPU_TXD5_N PE0_REFCLK_P PE0_REFCLK_N PE2_RX_N PE_GND PE_GND PE_GND PE0_RX2_P +1.2V_HT HT_CPU_TXD13_N HT_CPU_TXD14_N HT_CPU_TXD6_P

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Ball Listings

PROPRIETARY INFORMATION

Ball
K22 K23 K24 L1 L2 L3 L4 L5 L6 L7 L8 L9 L11 L12 L13 L14 L16 L17 L18 L19 L20 L21 L22 L23 L24 M2 M3 M4 M6 M8 M9 M11 M12 M13 M14 M16 M17 M19 M21 M22 M23

Signal Name
HT_CPU_TXD6_N HT_CPU_TXD7_P HT_CPU_TXD7_N PE0_TX0_P PE0_TX0_N PE0_TX1_P PE0_TX2_P PE0_RX3_N PE0_RX3_P PE0_RX4_P PE0_RX4_N PE_GND GND GND GND GND +2.5V_PLLHTCPU HT_CPU_TXD13_P HT_CPU_TXD15_P HT_CPU_TXD15_N HT_CPU_TXD14_P GND GND HT_CPU_TXCTL_P HT_CPU_TXCTL_N PE0_TX1_N PE0_TX2_N PE0_TX3_P PE_GND PE0_RX5_N PE0_RX5_P GND GND GND GND +1.2V_HT HT_CPU_RXD15_P GND +1.2V_HT HT_CPU_RXCTL_N HT_CPU_RXCTL_P

Ball
N3 N4 N5 N6 N7 N8 N9 N11 N12 N13 N14 N16 N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P6 P8 P9 P11 P12 P13 P14 P16 P17 P19 P21 P22 P23 P24 R1 R2 R3 R4 R5

Signal Name
PE0_TX3_N PE_GND PE0_RX7_N PE0_RX7_P PE0_RX6_N PE0_RX6_P PE_GND GND GND GND GND +1.2V_PLLHTCPU GND HT_CPU_RXD15_N HT_CPU_RXD14_N HT_CPU_RXD14_P HT_CPU_RXD7_N HT_CPU_RXD7_P PE0_TX4_P PE0_TX4_N PE0_RX9_P PE0_RX9_N PE_GND PE_GND +1.2V_PLLCORE GND GND GND GND HT_CPU_RXD13_P HT_CPU_RXD13_N GND HT_CPU_RXD6_N HT_CPU_RXD6_P HT_CPU_RXD5_N HT_CPU_RXD5_P PE0_TX5_P PE0_TX5_N PE0_TX6_P PE0_TX7_P PE0_RX8_N

Ball
R6 R7 R8 R9 R16 R17 R18 R19 R20 R21 R22 R23 R24 T2 T3 T4 T6 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T19 T21 T22 T23 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12

Signal Name
PE0_RX8_P PE0_RX10_N PE0_RX10_P +1.2V_PLLGPU +1.2V_HT GND HT_CPU_RXD12_P HT_CPU_RXD12_N HT_CPU_RX_CLK1_N HT_CPU_RX_CLK1_P GND HT_CPU_RXD4_N HT_CPU_RXD4_P PE0_TX6_N PE0_TX7_N PE_GND PE_GND PE0_RX12_P PE0_RX12_N HT_MCP_RX_CLK1_N +1.2V_PLLPE GND +1.2V_PLLHTMCP GND +1.2V_HTMCP +1.2V_HT GND GND HT_CPU_RXD11_P HT_CPU_RX_CLK0_N HT_CPU_RX_CLK0_P PE0_TX8_N PE0_TX8_P PE0_RX11_N PE0_RX11_P PE0_RX13_P PE0_RX13_N PE_GND HT_MCP_RX_CLK1_P +1.2V_HTMCP GND

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Ball Listings

PROPRIETARY INFORMATION

Ball
U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V6 V8 V9 V11 V13 V15 V17 V19 V21 V22 V23 V24 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15

Signal Name
+1.2V_HTMCP GND +1.2V_HTMCP +1.2V_HTMCP +1.2V_HT GND GND HT_CPU_RXD11_N HT_CPU_RXD3_N HT_CPU_RXD3_P PE0_TX9_P PE0_TX9_N PE0_RX14_N PE0_RX14_P PE_GND PE_GND HT_MCP_RXD11_P HT_MCP_RXD14_P HT_MCP_RXD15_N HT_MCP_TXD12_N HT_MCP_TXD11_N GND HT_CPU_RXD9_P GND HT_CPU_RXD2_N HT_CPU_RXD2_P PE0_TX10_P PE0_TX10_N PE0_TX11_P PE_GND CLKIN_200MHZ_N PE_GND HT_MCP_RXD9_P PE_GND HT_MCP_RXD11_N HT_MCP_RXD12_N HT_MCP_RXD14_N HT_MCP_RXD15_P HT_MCP_TXD15_P HT_MCP_TXD14_N HT_MCP_TXD12_P

Ball
W16 W17 W18 W19 W20 W21 W22 W23 W24 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA11

Signal Name
+1.2V_HTMCP HT_MCP_TX_CLK1_N HT_MCP_TXD11_P HT_CPU_CAL_1P2V HT_CPU_RXD9_N HT_CPU_RXD10_P HT_CPU_RXD10_N HT_CPU_RXD1_N HT_CPU_RXD1_P PE0_TX11_N PE0_RX15_P PE_GND CLKIN_200MHZ_P HT_MCP_RXD8_N HT_MCP_RXD9_N HT_MCP_RXD10_P +1.2V_HTMCP HT_MCP_RXD12_P GND HT_MCP_RXD13_N HT_MCP_TXD15_N HT_MCP_TXD14_P HT_MCP_TXD13_N GND HT_MCP_TX_CLK1_P GND HT_CPU_CAL_GND HT_CPU_RXD8_N HT_CPU_RXD8_P HT_CPU_RXD0_N HT_CPU_RXD0_P PE0_TX12_P PE0_TX12_N PE0_RX15_N GND HT_MCP_STOP# HT_MCP_RXD8_P HT_MCP_RXD10_N HT_MCP_RXD2_P HT_MCP_RXD3_P HT_MCP_RXD13_P

Ball
AA13 AA15 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AC1 AC2 AC3 AC4 AC5 AC6 AC7

Signal Name
GND HT_MCP_TXD13_P HT_MCP_TXD5_P +1.2V_HTMCP HT_MCP_TXD10_N HT_MCP_TXD9_N GND GND GND GND PE0_TX13_P PE0_TX13_N PE_REFCLKIN_N GND HT_MCP_REQ# GND HT_MCP_RXD1_N HT_MCP_RXD2_N HT_MCP_RXD3_N GND +1.2V_HTMCP HT_MCP_RXD6_N HT_MCP_RXD7_N GND HT_MCP_TXD6_N HT_MCP_TXD6_P HT_MCP_TXD5_N HT_MCP_TXD4_P HT_MCP_TXD10_P HT_MCP_TXD9_P HT_MCP_TXD8_P HT_MCP_TXD8_N HT_MCP_CAL_1P2V HT_MCP_CAL_GND PE0_TX14_P PE0_TX14_N PE_REFCLKIN_P CLKIN_25MHZ HT_MCP_RESET# HT_MCP_RXD0_N HT_MCP_RXD1_P

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Ball Listings

PROPRIETARY INFORMATION

Ball
AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC18 AC19

Signal Name
HT_MCP_RX_CLK0_N HT_MCP_RXD4_N HT_MCP_RXD5_N HT_MCP_RXD6_P HT_MCP_RXD7_P HT_MCP_RXCTL_N HT_MCP_TXCTL_P HT_MCP_TXD7_P HT_MCP_TXD4_N HT_MCP_TX_CLK0_P

Ball
AC20 AC21 AC22 AC23 AC24 AD2 AD3 AD5 AD6 AD9

Signal Name
HT_MCP_TXD3_P HT_MCP_TXD2_N HT_MCP_TXD2_P HT_MCP_TXD0_N HT_MCP_TXD0_P PE0_TX15_P PE0_TX15_N HT_MCP_PWRGD HT_MCP_RXD0_P HT_MCP_RX_CLK0_P

Ball
AD10 AD11 AD14 AD15 AD16 AD19 AD20 AD22 AD23

Signal Name
HT_MCP_RXD4_P HT_MCP_RXD5_P HT_MCP_RXCTL_P HT_MCP_TXCTL_N HT_MCP_TXD7_N HT_MCP_TX_CLK0_N HT_MCP_TXD3_n HT_MCP_TXD1_N HT_MCP_TXD11_P

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Ball Listings

PROPRIETARY INFORMATION

Table 33.
Signal Name +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_PEA +1.2V_PEA +1.2V_PEA +1.2V_PEA +1.2V_PEA +1.2V_PEA +1.2V_PEA

Ball Listing by Signal Name

Ball B5 C6 D7 E8 E9 E10 F10 F11 G11 H11 J11 J12 J13 J14 K16 M16 R16 M21 J20 T16 U17 C21 H17 Y9 U11 AB11 U13 T15 U15 U16 W16 AA18 A3 B3 C4 D5 E6 F7 F8 Signal Name +1.2V_PEA +1.2V_PED +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PED +1.2V_PED +1.2V_PED +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLLCORE +1.2V_PLLGPU +1.2V_PLLHTCPU +1.2V_PLLHTMCP +1.2V_PLLIFP +1.2V_PLLPE +2.5V_CORE +2.5V_CORE +2.5V_IFPA +2.5V_IFPB +2.5V_PLLCORE +2.5V_PLLGPU +2.5V_PLLHTCPU +2.5V_PLLIFP +3.3V +3.3V +3.3V_DAC CLKIN_25MHZ CLKOUT_CTERM_GND CLKOUT_PRI_ 200MHZ_N Ball F9 B4 B2 C2 C3 D4 E5 F6 G7 G8 C5 D6 E7 A2 G9 H10 J10 P9 R9 N16 T13 H16 T11 C16 B16 G15 H15 H12 H13 L16 E16 C10 D18 A9 AC4 B22 B23 Signal Name CLKOUT_PRI_ 200MHZ_P CLKOUT_SEC_ 200MHZ_N CLKOUT_SEC_ 200MHZ_P DAC_BLUE DAC_GREEN DAC_HSYNC DAC_IDUMP DAC_RED DAC_RSET DAC_VREF DAC_VSYNC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball B24 B21 A22 A6 B6 B7 C8 A5 D8 D9 C7 C1 AA21 AA13 U14 H14 C11 AB4 AA4 J15 E12 AB10 Y18 E18 U18 E15 Y11 U19 N17 F16 J17 L13 B1 T17 D11 T12

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NVIDIA C51G Data Sheet

Ball Listings

PROPRIETARY INFORMATION

Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Ball J16 D19 H19 L21 M19 P19 T19 V19 T14 C20 R17 AB14 U12 G13 Y16 H21 C22 AB6 F22 L22 R22 V22 AA22 A23 AA23 AA24 L11 M11 N11 P11 M12 N12 P12 M13 N13 P13 M14 N14 P14 L14 L12

Signal Name HT_CPU_CAL_1P2V HT_CPU_CAL_GND HT_CPU_PWRGD HT_CPU_REQ# HT_CPU_RESET# HT_CPU_RX_CLK0_N HT_CPU_RX_CLK0_P HT_CPU_RX_CLK1_N HT_CPU_RX_CLK1_P HT_CPU_RXCTL_N HT_CPU_RXCTL_P HT_CPU_RXD0_N HT_CPU_RXD0_P HT_CPU_RXD1_N HT_CPU_RXD1_P HT_CPU_RXD2_N HT_CPU_RXD2_P HT_CPU_RXD3_N HT_CPU_RXD3_P HT_CPU_RXD4_N HT_CPU_RXD4_P HT_CPU_RXD5_N HT_CPU_RXD5_P HT_CPU_RXD6_N HT_CPU_RXD6_P HT_CPU_RXD7_N HT_CPU_RXD7_P HT_CPU_RXD8_N HT_CPU_RXD8_P HT_CPU_RXD9_N HT_CPU_RXD9_P HT_CPU_RXD10_N HT_CPU_RXD10_P HT_CPU_RXD11_N HT_CPU_RXD11_P HT_CPU_RXD12_N HT_CPU_RXD12_P HT_CPU_RXD13_N HT_CPU_RXD13_P HT_CPU_RXD14_N HT_CPU_RXD14_P

Ball W19 Y19 E19 F18 D20 T22 T23 R20 R21 M22 M23 Y22 Y23 W23 W24 V23 V24 U21 U22 R23 R24 P23 P24 P21 P22 N21 N22 Y20 Y21 W20 V21 W22 W21 U20 T21 R19 R18 P17 P16 N19 N20

Signal Name HT_CPU_RXD15_N HT_CPU_RXD15_P HT_CPU_STOP# HT_CPU_TX_CLK0_N HT_CPU_TX_CLK0_P HT_CPU_TX_CLK1_N HT_CPU_TX_CLK1_P HT_CPU_TXCTL_N HT_CPU_TXCTL_P HT_CPU_TXD0_N HT_CPU_TXD0_P HT_CPU_TXD1_N HT_CPU_TXD1_P HT_CPU_TXD2_N HT_CPU_TXD2_P HT_CPU_TXD3_N HT_CPU_TXD3_P HT_CPU_TXD4_N HT_CPU_TXD4_P HT_CPU_TXD5_N HT_CPU_TXD5_P HT_CPU_TXD6_N HT_CPU_TXD6_P HT_CPU_TXD7_N HT_CPU_TXD7_P HT_CPU_TXD8_N HT_CPU_TXD8_P HT_CPU_TXD9_N HT_CPU_TXD9_P HT_CPU_TXD10_N HT_CPU_TXD10_P HT_CPU_TXD11_N HT_CPU_TXD11_P HT_CPU_TXD12_N HT_CPU_TXD12_P HT_CPU_TXD13_N HT_CPU_TXD13_P HT_CPU_TXD14_N HT_CPU_TXD14_P HT_CPU_TXD15_N HT_CPU_TXD15_P

Ball N18 M17 G18 G24 G23 G21 G22 L24 L23 C24 C23 D24 D23 E23 E22 F24 F23 H23 H22 J22 J21 K22 K21 K24 K23 D22 D21 E20 F19 E21 F21 G19 G20 J18 J19 K17 L17 K19 L20 L19 L18

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NVIDIA C51G Data Sheet

Ball Listings

PROPRIETARY INFORMATION

Signal Name HT_MCP_CAL_1P2V HT_MCP_CAL_GND HT_MCP_PWRGD HT_MCP_REQ# HT_MCP_RESET# HT_MCP_RX_CLK0_N HT_MCP_RX_CLK0_P HT_MCP_RX_CLK1_N HT_MCP_RX_CLK1_P HT_MCP_RXCTL_N HT_MCP_RXCTL_P HT_MCP_RXD0_N HT_MCP_RXD0_P HT_MCP_RXD1_N HT_MCP_RXD1_P HT_MCP_RXD2_N HT_MCP_RXD2_P HT_MCP_RXD3_N HT_MCP_RXD3_P HT_MCP_RXD4_N HT_MCP_RXD4_P HT_MCP_RXD5_N HT_MCP_RXD5_P HT_MCP_RXD6_N HT_MCP_RXD6_P HT_MCP_RXD7_N HT_MCP_RXD7_P HT_MCP_RXD8_N HT_MCP_RXD8_P HT_MCP_RXD9_N HT_MCP_RXD9_P HT_MCP_RXD10_N HT_MCP_RXD10_P HT_MCP_RXD11_N HT_MCP_RXD11_P HT_MCP_RXD12_N HT_MCP_RXD12_P HT_MCP_RXD13_N HT_MCP_RXD13_P HT_MCP_RXD14_N HT_MCP_RXD14_P

Ball AB23 AB24 AD5 AB5 AC5 AC9 AD9 T10 U10 AC14 AD14 AC6 AD6 AB7 AC7 AB8 AA8 AB9 AA9 AC10 AD10 AC11 AD11 AB12 AC12 AB13 AC13 Y6 AA6 Y7 W7 AA7 Y8 W9 V9 W10 Y10 Y12 AA11 W11 V11

Signal Name HT_MCP_RXD15_N HT_MCP_RXD15_P HT_MCP_STOP# HT_MCP_TX_CLK0_N HT_MCP_TX_CLK0_P HT_MCP_TX_CLK1_N HT_MCP_TX_CLK1_P HT_MCP_TXCTL_N HT_MCP_TXCTL_P HT_MCP_TXD0_N HT_MCP_TXD0_P HT_MCP_TXD1_N HT_MCP_TXD1_P HT_MCP_TXD2_N HT_MCP_TXD2_P HT_MCP_TXD3_N HT_MCP_TXD3_P HT_MCP_TXD4_N HT_MCP_TXD4_P HT_MCP_TXD5_N HT_MCP_TXD5_P HT_MCP_TXD6_N HT_MCP_TXD6_P HT_MCP_TXD7_N HT_MCP_TXD7_P HT_MCP_TXD8_N HT_MCP_TXD8_P HT_MCP_TXD9_N HT_MCP_TXD9_P HT_MCP_TXD10_N HT_MCP_TXD10_P HT_MCP_TXD11_N HT_MCP_TXD11_P HT_MCP_TXD12_N HT_MCP_TXD12_P HT_MCP_TXD13_N HT_MCP_TXD13_P HT_MCP_TXD14_N HT_MCP_TXD14_P HT_MCP_TXD15_N HT_MCP_TXD15_P

Ball V13 W12 AA5 AD19 AC19 W17 Y17 AD15 AC15 AC23 AC24 AD22 AD23 AC21 AC22 AD20 AC20 AC18 AB18 AB17 AA17 AB15 AB16 AD16 AC16 AB22 AB21 AA20 AB20 AA19 AB19 V17 W18 V15 W15 Y15 AA15 W14 Y14 Y13 W13

Signal Name IFPA_TXC_N IFPA_TXC_P IFPA_TXD0_N IFPA_TXD0_P IFPA_TXD1_N IFPA_TXD1_P IFPA_TXD2_N IFPA_TXD2_P IFPA_TXD3_N IFPA_TXD3_P IFPAB_RSET IFPAB_VPROBE IFPB_TXC_N IFPB_TXC_P IFPB_TXD4_N IFPB_TXD4_P IFPB_TXD5_N IFPB_TXD5_P IFPB_TXD6_N IFPB_TXD6_P IFPB_TXD7_N IFPB_TXD7_P JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST# NC NC NC NC NC PE_CTERM_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND

Ball B13 C14 B15 A15 C15 D15 B14 A14 E14 F14 F15 A16 B10 A10 A11 B11 F13 E13 C13 D13 C12 B12 C18 B19 C19 B18 A19 F12 E11 E17 F17 G17 D2 F3 L9 P8 N9 K4 N4 T4 W4

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NVIDIA C51G Data Sheet

Ball Listings

PROPRIETARY INFORMATION

Signal Name PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_REFCLKIN_N PE_REFCLKIN_P PE_RESET# PE_TSTCLK_N PE_TSTCLK_P PE0_PRSNT# PE0_REFCLK_N PE0_REFCLK_P PE0_RX0_N PE0_RX0_P PE0_RX1_N PE0_RX1_P PE0_RX2_N PE0_RX2_P PE0_RX3_N PE0_RX3_P PE0_RX4_N PE0_RX4_P PE0_RX5_N PE0_RX5_P PE0_RX6_N PE0_RX6_P PE0_RX7_N PE0_RX7_P PE0_RX8_N PE0_RX8_P PE0_RX9_N

Ball Y4 U9 V8 K6 M6 P6 T6 W6 W8 H8 K8 V6 F4 H9 AB3 AC3 G1 F2 F1 D1 K2 K1 J7 J8 J5 J6 J9 K9 L5 L6 L8 L7 M8 M9 N7 N8 N5 N6 R5 R6 P4

Signal Name PE0_RX9_P PE0_RX10_N PE0_RX10_P PE0_RX11_N PE0_RX11_P PE0_RX12_N PE0_RX12_P PE0_RX13_N PE0_RX13_P PE0_RX14_N PE0_RX14_P PE0_RX15_N PE0_RX15_P PE0_TX0_N PE0_TX0_P PE0_TX1_N PE0_TX1_P PE0_TX2_N PE0_TX2_P PE0_TX3_N PE0_TX3_P PE0_TX4_N PE0_TX4_P PE0_TX5_N PE0_TX5_P PE0_TX6_N PE0_TX6_P PE0_TX7_N PE0_TX7_P PE0_TX8_N PE0_TX8_P PE0_TX9_N PE0_TX9_P PE0_TX10_N PE0_TX10_P PE0_TX11_N PE0_TX11_P PE0_TX12_N PE0_TX12_P PE0_TX13_N PE0_TX13_P

Ball P3 R7 R8 U5 U6 T9 T8 U8 U7 V3 V4 AA3 Y3 L2 L1 M2 L3 M3 L4 N3 M4 P2 P1 R2 R1 T2 R3 T3 R4 U3 U4 V2 V1 W2 W1 Y2 W3 AA2 AA1 AB2 AB1

Signal Name PE0_TX14_N PE0_TX14_P PE0_TX15_N PE0_TX15_P PE1_CLKREQ# PE1_PRSNT# PE1_REFCLK_N PE1_REFCLK_P PE1_RX_N PE1_RX_P PE1_TX_N PE1_TX_P PE2_CLKREQ# PE2_PRSNT# PE2_REFCLK_N PE2_REFCLK_P PE2_RX_N PE2_RX_P PE2_TX_N PE2_TX_P PKG_TEST SCLKIN_MCLKOUT_ 200MHZ_N SCLKIN_MCLKOUT_ 200MHZ_P TEST_MODE_EN XTAL_IN XTAL_OUT

Ball AC2 AC1 AD3 AD2 D3 E2 G3 G2 H6 G6 G5 G4 E4 E3 H3 H2 K3 J4 J3 H4 D17 B20 A20 C17 C9 B9

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NVIDIA C51G Data Sheet

Ball Listings

PROPRIETARY INFORMATION

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Appendix B. Ballout

This appendix contains the ballout for the NVIDIA C51M.

Ball Locations Ballout (Top Left View) Ballout (Top Right View)

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NVIDIA C51G Data Sheet

Ballout

PROPRIETARY INFORMATION

Ballout (Top Left View)

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD 1 PE0_TX12_P PE0_TX13_P PE0_TX14_P PE0_TX9_P PE0_TX10_P PE0_TX9_N PE0_TX10_N PE0_TX11_N PE0_TX12_N PE0_TX13_N PE0_TX14_N PE0_TX15_P 2 PE0_TX4_P PE0_TX5_P PE0_TX4_N PE0_TX5_N PE0_TX6_N PE0_ REFCLK_P PE0_ TX0_P PE0_ REFCLK_N PE0_TX0_N PE0_ TX1_N PE_ TSTCLK_P PE_ RESET# GND GND PE0_PRSNT# 2 +1.2V_PLL +1.2V_PLL +1.2V_PLL PE_CTERM_ GND PE1_PRSNT # PE_ TSTCLK_N PE1_ REFCLK_P PE2_ REFCLK_P 3 +1.2V_PEA +1.2V_PEA +1.2V_PLL PE1_CLKREQ# PE2_PRSNT# PE_GND PE1_REFCLK_N PE2_REFCLK_N PE2_TX_N PE2_RX_N PE0_TX1_P PE0_TX2_N PE0_TX3_N PE0_RX9_P PE0_TX6_P PE0_TX7_N PE0_TX8_N PE0_RX14_N PE0_TX11_P PE0_RX15_P PE0_RX15_N PE_ REFCLKIN_N PE_ REFCLKIN_P PE0_TX15_N 3 4 +1.2V_PED +1.2V_PEA +1.2V_PLL PE2_ CLKREQ# PE_GND PE1_TX_P PE2_TX_P PE2_RX_P PE_GND PE0_TX2_P PE0_TX3_P PE_GND PE0_RX9_N PE0_TX7_P PE_GND PE0_TX8_P PE0_RX14_P PE_GND PE_GND GND GND CLKIN_ 25MHZ 4 5

Pin Define

6 DAC_BLUE DAC_ GREEN

9 +3.3V_DAC

10

11

12

DAC_RED +1.2V_ CORE +1.2V_PED +1.2V_PEA +1.2V_PLL

IFPB_TXC_P IFPB_TXD4_N IFPB_TXC_N IFPB_TXD4_P +3.3V GND GND NC +1.2V_CORE +1.2V_CORE +1.2V_PLL +1.2V_PLL +1.2V_CORE +1.2V_CORE +2.5V_ PLLCORE +1.2V_CORE GND NC IFPB_ TXD7_P IFPB_ TXD7_N

DAC_HSYNC DAC_ IDUMP DAC_RSET

XTAL_OUT XTAL_IN DAC_VREF

+1.2V_CORE DAC_VSYNC +1.2V_PED +1.2V_PEA +1.2V_PLL +1.2V_CORE +1.2V_PED +1.2V_PEA +1.2V_PLL

+1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_PEA +1.2V_PLL PE_GND +1.2V_PEA +1.2V_PLL PE_GND PE0_RX2_N PE0_RX2_P PE_GND PE0_RX5_P PE_GND +1.2V_ PLLCORE +1.2V_ PLLGPU PE0_ RX12_N PE_GND HT_MCP_ RXD11_P HT_MCP_ RXD11_N +1.2V_ HTMCP HT_MCP_ RXD3_P HT_MCP_ RXD3_N HT_MCP_RX _CLK0_N HT_MCP_ RX_CLK0_P GND HT_MCP_ RXD4_N HT_MCP_ RXD4_P 10 HT_MCP_ RXD12_N HT_MCP_ RXD12_P HT_MCP_ RX_CLK1_N HT_MCP_ RX_CLK1_P +1.2V_CORE

PE1_TX_N

PE1_RX_P PE1_RX_N

PE0_RX1_N

PE0_RX1_P PE_GND

PE0_RX0_N

PE0_RX0_P PE_GND

PE0_RX3_N

PE0_RX3_P PE_GND

PE0_RX4_P

PE0_RX4_N PE0_RX5_N

GND GND GND GND

GND GND GND GND

PE0_RX7_N

PE0_RX7_P PE_GND

PE0_RX6_N

PE0_RX6_P PE_GND

PE0_RX8_N

PE0_RX8_P PE_GND

PE0_ RX10_N

PE0_RX10_P PE0_RX12_P PE0_ RX13_N PE_GND

+1.2V_PLLPE +1.2V_ HTMCP HT_MCP_ RXD14_P HT_MCP_ RXD14_N GND HT_MCP_ RXD13_P +1.2V_ HTMCP HT_MCP_ RXD5_N HT_MCP_ RXD5_P 11

GND GND

PE0_ RX11_N

PE0_RX11_P PE0_RX13_P PE_GND

CLKIN_ 200MHZ_N CLKIN_ 200MHZ_P HT_MCP_ STOP# HT_MCP_ REQ# HT_MCP_ RESET# HT_MCP_ PWRGD 5

PE_GND HT_MCP_ RXD8_N HT_MCP_ RXD8_P GND HT_MCP_ RXD0_N HT_MCP_ RXD0_P 6

HT_MCP_ RXD9_P HT_MCP_ RXD9_N HT_MCP_ RXD10_N HT_MCP_ RXD1_N HT_MCP_ RXD1_P

PE_GND HT_MCP_ RXD10_P HT_MCP_ RXD2_P HT_MCP_ RXD2_N

HT_MCP_ RXD15_P HT_MCP_ RXD13_N

HT_MCP_ RXD6_N HT_MCP_ RXD6_P

12

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Ballout

PROPRIETARY INFORMATION

Ballout (Top Right View)

13 14 IFPA_ TXD2_P IFPA_TXC_N IFPB_ TXD6_N IFPB_ TXD6_P IFPB_ TXD5_P IFPB_ TXD5_N GND +2.5V_ PLLGPU GND IFPA_ TXD3_N IFPA_ TXD3_P IFPA_ TXD2_N IFPA_TXC_P 15 IFPA_ TXD0_P IFPA_ TXD0_N IFPA_ TXD1_N IFPA_ TXD1_P GND IFPAB_RSET +2.5V_IFPA +2.5V_IFPB GND +1.2V_ PLLIFP GND +1.2V_HT GND GND GND GND GND GND GND GND +2.5V_ PLLHTCPU +1.2V_HT +1.2V_ PLLHTCPU HT_CPU_ RXD13_P +1.2V_HT +1.2V_ PLLHTMCP +1.2V_ HTMCP HT_MCP_ RXD15_N HT_MCP_ TXD15_P HT_MCP_ TXD15_N GND HT_MCP_ RXD7_N HT_MCP_ RXD7_P GND HT_MCP_ RXCTL_N HT_MCP_ RXCTL_P 13 14 HT_MCP_ TXD14_N HT_MCP_ TXD14_P GND GND +1.2V_ HTMCP +1.2V_ HTMCP HT_MCP_ TXD12_N HT_MCP_ TXD12_P HT_MCP_ TXD13_N HT_MCP_ TXD13_P HT_MCP_ TXD6_N HT_MCP_ TXCTL_P HT_MCP_ TXCTL_N 15 HT_MCP_ TXD6_P HT_MCP_ TXD7_P HT_MCP_ TXD7_N 16 17 18 +1.2V_ HTMCP GND +1.2V_HT +1.2V_ HTMCP +2.5V_ PLLIFP GND 16 IFPAB_ VPROBE +2.5V_ CORE +2.5V_ CORE TEST_ MODE_EN PKG_TEST NC NC NC +1.2V_HT GND HT_CPU_ TXD13_N HT_CPU_ TXD13_P HT_CPU_ RXD15_P GND HT_CPU_ RXD13_N GND GND +1.2V_HT HT_MCP_ TXD11_N HT_MCP_ TX_CLK1_N HT_MCP_ TX_CLK1_P HT_MCP_ TXD5_P HT_MCP_ TXD5_N HT_MCP_ TXD11_P GND +1.2V_ HTMCP HT_MCP_ TXD4_P HT_MCP_ TXD4_N GND HT_CPU_ RXD12_P HT_CPU_ RXD15_N HT_CPU_ TXD15_P HT_CPU_ TXD12_N JTAG_TMS JTAG_TCK +3.3V GND HT_CPU_ REQ# HT_CPU_ STOP# 17 18 19 JTAG_ TRST# JTAG_TDI JTAG_TDO GND HT_CPU_ PWRGD HT_CPU_ TXD9_P HT_CPU_ TXD11_N GND HT_CPU_ TXD12_P HT_CPU_ TXD14_N HT_CPU_ TXD15_N GND HT_CPU_ RXD14_N GND HT_CPU_ RXD12_N GND GND GND HT_CPU_ CAL_1P2V HT_CPU_ CAL_GND HT_MCP_ TXD10_N HT_MCP_ TXD10_P HT_MCP_ TX_CLK0_P HT_MCP_ TX_CLK0_N 19 HT_CPU_ RXD9_N HT_CPU_ RXD8_N HT_MCP_ TXD9_N HT_MCP_ TXD9_P HT_MCP_ TXD3_P HT_MCP_ TXD3_N 20 21 HT_CPU_ RXD11_N HT_CPU_ RX_CLK1_N HT_CPU_ RXD14_P HT_CPU_ TXD14_P +1.2V_HT HT_CPU_ TXD11_P 20 SCLKIN_ MCLKOUT_ 200MHZ_P SCLKIN_ MCLKOUT_ 200MHZ_N GND HT_CPU_ RESET# HT_CPU_ TXD9_N CLKOUT_SEC_ 200MHZ_N +1.2V_HT HT_CPU_ TXD8_P HT_CPU_ TXD10_N HT_CPU_ TXD10_P HT_CPU_TX_ CLK1_N GND HT_CPU_ TXD5_P HT_CPU_ TXD6_P GND +1.2V_HT HT_CPU_ RXD7_N HT_CPU_ RXD6_N HT_CPU_ RX_CLK1_P HT_CPU_ RXD11_P HT_CPU_ RXD3_N HT_CPU_ RXD9_P HT_CPU_ RXD10_P HT_CPU_ RXD8_P GND HT_MCP_ TXD8_P HT_MCP_ TXD2_N 21 22 CLKOUT_ SEC_ 200MHZ_P CLKOUT_ CTERM_ GND GND HT_CPU_ TXD8_N HT_CPU_ TXD2_P GND HT_CPU_ TX_CLK1_P HT_CPU_ TXD4_P HT_CPU_ TXD5_N HT_CPU_ TXD6_N GND HT_CPU_ RXCTL_N HT_CPU_ RXD7_P HT_CPU_ RXD6_P GND HT_CPU_ RX_CLK0_N HT_CPU_ RXD3_P GND HT_CPU_ RXD10_N HT_CPU_ RXD0_N GND HT_MCP_ TXD8_N HT_MCP_ TXD2_P HT_MCP_ TXD1_N 22 HT_CPU_ RXD2_N HT_CPU_ RXD1_N HT_CPU_ RXD0_P GND HT_MCP_ CAL_1P2V HT_MCP_ TXD0_N HT_MCP_ TXD1_P 23 24 GND HT_MCP_ CAL_GND HT_MCP_ TXD0_P HT_CPU_ RXD2_P HT_CPU_ RXD1_P HT_CPU_ RXD5_N HT_CPU_ RXD4_N HT_CPU_ RX_CLK0_P HT_CPU_ RXD5_P HT_CPU_ RXD4_P HT_CPU_ TXD7_P HT_CPU_ TXCTL_P HT_CPU_ RXCTL_P HT_CPU_ TXD7_N HT_CPU_ TXCTL_N 23 GND CLKOUT_PRI_ CLKOUT_PRI_ 200MHZ_N 200MHZ_P HT_CPU_ TXD0_P HT_CPU_ TXD1_P HT_CPU_ TXD2_N HT_CPU_ TXD3_P HT_CPU_ TX_CLK0_P HT_CPU_ TXD4_N HT_CPU_ TXD3_N HT_CPU_ TX_CLK0_N HT_CPU_ TXD0_N HT_CPU_ TXD1_N 24 A

B C D E F G H J K L M N P R T U V W Y AA AB AC AD

+1.2V_CORE +1.2V_CORE

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NVIDIA C51G Data Sheet

Ballout

PROPRIETARY INFORMATION

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Notice ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS, AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY, MATERIALS) ARE BEING PROVIDED AS IS. NVIDIA MAKES NO WARRANTIES (EXPRESSED, IMPLIED, STATUTORY, OR OTHERWISE) WITH RESPECT TO THE MATERIALS AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE.

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