ARM

Architecture, Programming and Development Tools

Lesson 3 ARM CPU32 bit ARM and 16-bit Thumb Instruction Sets

"Microcontrollers....", Raj Kamal, from Pearson Education, 2005

Outline
Basic Features 32-bit Instruction Set Thumb 16-bit Instruction Set Inter-working with ARM/Thumb sets

"Microcontrollers....", Raj Kamal, from Pearson Education, 2005

ARM code size small than other RISCs 32-bit un-segmented memory

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Basic Programming FeaturesProcessor can operate on the words as per initialization. A word alignment can in big endian [least significant byte stored as higher bits (address 3) of a word] or little endian [least significant byte stored as lower bits (address 0) of a word].
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Data Types support 8-bit byte, 16-bit half-word data types half-words are aligned on 2byte boundaries 32-bit data types- words are aligned on 4-byte boundaries
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Little Endian Mode

Address

Half word

Word Byte3 (MSB) byte2 byte1 Byte0 (LSB)

Byte Address0 Address1 Address2 Address3

Address0 Byte0 (LSB) Address1 byte1 (MSB)

Address0- even address; Address1- odd address

Three DataType options

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Big Endian Mode

Address

Half word

Word Byte3 (MSB) byte2 byte1 byte0 (LSB)

Byte Address0 Address1 Address2 Address3

Address0 byte1 (MSB) Address1 Byte0 (LSB)

Address0- even address; Address1- odd address

Three DataType options

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Programming Model 16 general-purpose registers with program counter as one of the register (R15).

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- Registers
R0 R1 R2 R3 R4 R5 R6 R7 Lo registers R8 R9 R10 R11 R12 Hi registers

SP (R13) Stack Pointer LR (R14) Link Register PC (Rr15) Program Counter CPSR SPSR

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CPSR and SPSR

CPSR (Conditions and Processor Status Register) SPSR ( Saved Program Status Register) Saves Program Status Register from CPSR on branch and link (routine call) and SPSR can be stacked for each processor mode
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Outline
Basic Features 32-bit Instruction Set Thumb 16-bit Instruction Set Inter-working with ARM/Thumb sets

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Load Instructions
LDM: Load multiple registers LDR: Load a register (32 bit) LDRB: Load a byte (8 bit) into register

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Load Instructions (in certain variants

e.g. ARM7500, StrongARM)

LFM: Load multiple floating point values - ARM7500 LDRSB: Load a signed byte (8 bit) into register Load a half-word (16 bit) into register (in certain variants e.g. StrongARM)
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Store Instructions
STM: Store multiple registers STR: Store a register (32 bit) STRB: Store a byte (8 bit) from a register

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Store Instructions (in certain variants

e.g. ARM7500, StrongARM)

SFM: Store Multiple Floating point values- ARM7500 STRSB: Store a signed byte from a register- StrongARM STRSH: Store a signed half-word from a register- StrongARM
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Load-store architecture Features LDM/STM with multiple options of addressing modes (like immediate) LDM/STM loads into a subset of registers in a list or save from the list to the memory addresses
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Data Transfer Instructions MOV: Move value/register into a register MRC: Co-processor register transfer (co-processor to ARM) MVN: Move after negation

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ARM Arithmetic Instructions

MAC unit Support

ADD

ADC

BIC

SBC and

MUL 32x32 and MULL

MLA and MLAL

A select Add with Carry bit clear Subtract with carry SUB: Subtract multiply long (32 x 32 64)

SUB

multiply (32 x 32 32) with add instruction

(32 x 32 64) multiply

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long 19 and add instruction.

Arithmetic Instructions ADC: Add with Carry, ADD:Add SBC: Subtract with carry , SUB: Subtract RSC: Reverse Subtract with carry , RSB: Reverse Subtract BIC: A select bit Clear
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MUL and DIV Instructions..

UMULL: Unsigned Long (64 bit) Multiply- StrongARM

DVF: Divide floating PointARM7500

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MAC unit Support

MLA and MLAL implement DSP instructions UMLAL: Unsigned Long (64 bit) Multiply with Accumulate-Strong ARM
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ARM Logic Instructions

AND

ORR

TST Test bits

CMN

TEQ

EOR Exclusive OR

Hypothetical AND Compare negated values (Hypothetical SUB)

CMP

Test Equivalence (Hypothetical EOR)

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Logical Instructions.. Logical AND, ORR, EOR TST: Test bits (Hypothetical AND) TEQ: Test Equivalence (Hypothetical EOR) CMP: Compare values (Hypothetical SUB), CMN: Compare negated values
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Program Flow Control B: Branch BL: Branch with Link

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Interrupt Control Instruction

SWI<suffix> <number> SWI: cond SWI (8 msbs) remaining 24 bit lsbs are irrelevant as far as execution of the instruction is concerned. Interrupt handler can use the 24-bits for the suffix parameter (s) and number to reflect the interrupting foreground program (source of SWI).
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Lets the OS including Device Drivers, have a modular structure The code required to create a complete operating system spliced into a number of small parts (modules) and a module handler specifies by <number> The handler executes after passing any data through use of <suffix>
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SWI <suffix> <number>

ARM32-bit Instruction Set Features Data processing, data transfer and control flow execute with several settable options Implementation of many instructions by just a few instructions at the set CPU instruction decoder decodes instruction as per chosen options
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ARM32-bit Instruction Option fields Conditional or no-condition 4-bit field inmost instructions - facilitates implementation of many conditional instructions After cond option, there are option fields like addressing mode, shift or rotate option, flag change fields
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32-bit Instruction Format

Cond Opcode X- Opcode S- Rn Rd 44-bits major Bit Minor Bit 4-bits 4-bits Bits 4-bits 2-bits flag change field Source operand 2 8-bits

Destination Option Field Refer Next Slide

Refer Next Slide

Bits 31-0
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Instruction Format
cond 00 X opcode S Rn Rd operand 2 S specifies CPSR flags change or no change by the operation
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If X =1 then b11-b8 specifies rotate right instruction and b7-b0 immediate operand. b11-b8 = 0000 means no rotation, b11-b8 = 0001 means rotate right 2 times, b11-b8 = 1111 means ROR 30 times. Immediate operand is32-bit with 24 msbs = 0s
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Second source operand can also be shifted or rotated before using the source in the operations. Flags (N, Z, C and V)can be changed or unchanged as per S bit in the instruction. Move can be conditional or unconditional as per cond 4-bit field in the instruction
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Outline
Basic Features 32-bit Instruction Set Thumb 16-bit Instruction Set Inter-working with ARM/Thumb sets

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- Thumb16 bit subset Better code density than 32-bit architecture instruction set

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Programming Model 8 general-purpose Lower set of registers permit 3-bit in the instruction for a register Program counter register (R15) Link Register (R14) Stack Pointer (R13)
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16-bit Thumb Instruction Set Features Code size small than 32-bit instruction Most instructions - data processing, data transfer and control flow execute with nocondition field 3-bit for Lower set register facilitates implementation with 16-bit instruction
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Instructions ExamplesLDMIA:Thumb: Store multiple registers LDR: Load register (32 bits?) LDRB:Load byte (8 bit) into register LDRH: Load half-word (!)into register
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Contd

LDRSB: oad signed byte (sign + 7 bit) into registe LDRSH: Load signed half-word (sign + 15 bit) into register

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Contd

STMIA:Thumb: Store multiple registers STR: Store register (32 bit?) STRB:Store byte (8 bit) STRH: Store half-word (16 bit)
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Data Transfer Instructions MOV: Move value/register into a register MVN: Move after negation PUSH: registers to stack POP: registers from stack

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Thumb Arithmetic Instructions

ADD

ADC

BIC

SBC and

MUL

NEG

A select Add with Carry bit clear Subtract with carry SUB: Subtract

SUB

multiply By -1 multiply long (32 x 32 64)

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Thumb Logic Instructions

AND

OR

TST Test bits

CMN

CMP

EOR Exclusive OR

Hypothetical AND Compare negated values

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(Hypothetical SUB)

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Program Flow Control NOP: No operation, B: Branch, BX: Branch and Exchange BL: Long Branch with Link (LR and PC exchange), BLX:Branch with Link and Exchange BKPT: Breakpoint
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Interrupt Control Instruction

SWI: cond SWI (8 msbs) remaining 8 bit lsbs are irrelevant as far as execution of the instruction is concerned. However, the handler can use the 4-bits for the suffix parameter and a number of 4-bits to reflect the interrupting foreground program (source of SWI).
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16-bit Thumb Instruction Format

Opcode X- Opcode Rd operand major Bit Minor 3-bits 8-bits 2-bits 2-bits Immediate Operand if X=1 Rn Rd or other options For Index Bits 15-0
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Destination cum Source Register or Rm

Instruction Example

ADD r4, #data8 16-bit instruction in memory decompressed at run time into 32-bit format will be 1110 (condition code) 011 01001 (minor opcode) 0 (S bit) 01000 (S bit) 0100 0000 (rotation) 1000 0000.
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Outline
Basic Features 32-bit Instruction Set Thumb 16-bit Instruction Set Inter-working with ARM/Thumb sets

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ARM/THUMB Inter-working
T-bit at CPSR support for interworking with 16-bit Thumb set and 32-bit ARM. T-bit in CPSR can always switch from ARM to Thumb and vice versa using assembly instruction code16 and code32, respectively.
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When working with 16-bit Thumb set execute the instruction code16, T bit set in CPSR. When switching to 32-bit Arm set execute the instruction code32, reset T bit in CPSR.
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ARM and Thumb code each execute in their own processor state as ARM PC increments by 4 and Thumb by 2

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Popular References at Web

http://www.cs.umd.edu/class/fall2001/cmsc41 1/proj01/arm/home.html http://www.e-lab.de/ARM7/ARMinstructionset.pdf. http://www.cvsi.fau.edu/shankar/Presenta tions/Lecture7_Ch2_ARM.pdf.
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http://www.cs.umd.edu/class/fall2001/ cmsc411/proj01/arm/thumb.html http://www.cs.man.ac.uk/Study_subwe b/Ugrad/coursenotes/cs1031/Lec20Thumb.pdf.

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Summary

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We learnt Programmability as little endian and big endian ARM 7 - Princeton architecture, ARM 9 Harvard architecture
8-bit byte, 16-bit half-word and 32-bit data types
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We learnt Conditional data processing, data transfer and control flow Execution and addressing modes facilitate by the few instructions only

Options for shift or rotate an operand in many instructions

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We learnt LDM/STM with many more addressing modes(like immediate) MAC Support
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We learnt Thumb16 bit

subset
Better code density than 32-bit architecture instruction set and switching in-between ARM 32-bit set and Thumb 16-bit set supported

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End of Lesson 3 on ARM 32-bit and Thumb16-bit Instruction Sets

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THANK YOU

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