DESIGNING CMOS CIRCUITS

FOR LOW POWER

Based on selected partner contributions
of the European Low Power Initiative for
Electronic System Design of the European
Community ESPRIT4 programme and other

Edited by

DIMITRIOS SOUDRIS
Democritus University of Thrace, Xanthi, Greece

CHRISTIAN PIGUET
CSEM, Neuchtel, Switzerland

COSTAS GOUTIS
University of Patras, Patras, Greece

Series Editors:

RENE VAN LEUKEN

ALEXANDER DE GRAAF
REINDER NOUTA
TUDelft/DIMES, Delft, Netherlands

Kluwer Academic Publishers

Boston/Dordrecht/London

Contents

List of Figures

vii

List of Tables

ix

Contributing Authors

xi

Foreword

xvii

Introduction

xxv

Part I

LOW POWER DESIGN METHODS

1
Motivation, Context and Objectives
Dimitrios Soudris, Christian Piguet and Costas Goutis

2
Sources of power dissipation in CMOS circuits
Dimitrios Soudris and Antonios Thanailakis
2.1
Introduction
2.2
The components of power dissipation in CMOS circuits
2.2.1 Dynamic Power dissipation
2.2.2 Short-circuit power dissipation
2.2.3 Leakage Power Dissipation
2.2.4 Static Power dissipation
2.3
Low Power Design with Multiple
and

9
10
10
12
15
18
19

References

20

3
Logic level Power Optimization
George Theodoridis and Dimitrios Soudris
3.1
Introduction
3.2
Problem Formulation
3.3
Combinational Circuits Technology-Independent Optimization

23
23
24
26

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DESIGNING CMOS CIRCUITS FOR LOW POWER

3.4
3.5

3.6

3.3.1 Two-Level Logic Circuits

3.3.2 Multi-Level Circuits
Sequential Circuits Technology-Independent Optimization
3.4.1 State Assignment
3.4.2 Logic Optimizations
Technology-Dependent Optimization
3.5.1 Path Balancing
3.5.2 Technology Decomposition
3.5.3 Technology Mapping
3.5.4 Post mapping Optimization
Conclusions

References

26
28
31
31
33
35
35
36
37
38
40
41

4
Circuit-Level Low-Power Design
Spiridon Nikolaidis and Alexander Chatzigeorgiou
4.1
Introduction
4.2
Logic Style
4.2.1 Static Logic
4.2.2 Dynamic Logic
4.2.3 Pass-Transistor Logic
4.2.4 Single-Rail Pass-Transistor Logic
4.2.5 Other Logic Styles
4.2.6 Logic Styles: Discussion
4.3
Latches and Flip-Flops
4.3.1 Latches
4.3.2 Flip - Flops
4.4
Transistor Sizing and Ordering
4.4.1 Transistor ordering
4.4.2 Transistor sizing
4.5
Drivers for large loads
4.6
Conclusions

45
46
46
48
50
52
54
57
58
58
61
63
63
64
64
66

References

67

5
Circuit Techniques for
Reducing Power Consumption
in Adders and Multipliers
Labros Bisdounis, Dimitrios Gouvetas and Odysseas Koufopavlou
5.1
Introduction
5.2
Power and Delay in CMOS Circuits
5.3
CMOS Circuit Design Styles
5.3.1 Conventional Static CMOS Logic - CSL
5.3.2 Complementary Pass-Transistor Logic - CPL
5.3.3 Double Pass-Transistor Logic - DPL
5.3.4 Static Differential Cascode Voltage Switch Logic - SDCVSL
5.3.5 Static Differential Split-level Logic - SDSL
5.3.6 Dual-Rail Domino Logic - DRDL

45

71

72
73
74
74
75
76
76
77
78

vii

Contents
5.3.7
5.4
5.5
5.6
5.7

Dynamic Differential Cascode Voltage Switch Logic DDCVSL

5.3.8 Enable/disabled CMOS Differential Logic- ECDL
Power, Delay and Area Comparisons of a 4-Bit Ripple Carry Adder
Adders
Multipliers
5.6.1 SPICE-like Power Measurements of Multipliers
5.6.2 High-Level Power Characterization of Multipliers
Conclusions

References

79
80
81
87
88
89
89
93
94

6
Computer Arithmetic Techniques for Low-Power Systems
Vassilis Paliouras and Thanos Stouraitis
6.1
Introduction
6.2
Conventional Arithmetic and Low-power design
6.2.1 Basic Arithmetic Operations
6.2.2 Number Representations
6.3
The Logarithmic Number System
6.3.1 LNS Basics
6.3.2 LNS and Power Dissipation
6.4
The Residue Number System
6.4.1 RNS Basics
6.4.2 RNS and Power Dissipation
6.4.3 RNS Signal Activity for Gaussian Input
6.4.4 Algebraic extensions: The Quadratic RNS
6.5
Conclusions

97
99
99
100
100
101
105
106
106
108
108
109
115

References

115

97

7
Reducing Power Consumption in Memories
Alexander Chatzigeorgiou and Spiridon Nikolaidis
7.1
Introduction
7.2
Static Random Access Memories
7.2.1 Sources of power dissipation in SRAMs
7.2.2 Low-Power SRAM Circuit Techniques
7.3
Dynamic Random Access Memories
7.3.1 Sources of power dissipation in DRAMs
7.3.2 Low-Power DRAM Circuit Techniques
7.4
Conclusions

117
118
119
121
128
131
133
138

References

139

8
Low-Power Clock, Interconnect and Layout Designs
Christian Piguet
8.1
Introduction
8.2
Low-Power Clock Design

117

141
141
142

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DESIGNING CMOS CIRCUITS FOR LOW POWER

8.2.1 Clock Skew
8.2.2 Latch-based Clocking Scheme
8.2.3 Gated Clock with Latch-based Designs
8.2.4 Results
8.2.5 Asynchronous Design
Interconnect Delays
8.3.1 The increased delays of wires
8.3.2 New Materials for wires and dielectric
8.3.3 Design methods taking into account interconnection delays
8.3.4 Crosstalk
Low-Power Optimization for Layout Design
8.4.1 Masks and Layout
8.4.2 Industrial Layout Rules
8.4.3 Layout Optimization for Low-Power
8.4.4 Low-power Standard Cell Libraries
8.4.5 Automatic Layout Synthesis
8.4.6 Transistor Sizing
8.4.7 Layout in Deep Submicron Technologies

8.3

8.4

References

142
145
146
148
148
149
150
152
153
154
156
157
157
158
160
163
163
164
165

9
Logic Level Power Estimation
George Theodoridis and Costas Goutis
9.1
Introduction
9.2
Problem Formulation
9.2.1 Sources of Power Dissipation
9.2.2 Problem Statement
9.3
Background
9.3.1 Signal Correlations
9.3.2 Structural Dependencies
9.3.3 Sequential Correlations
9.3.4 Gate Delay Model
9.4
Classication of Power Estimation Methodologies
9.5
Simulation-based Power Estimation
9.5.1 Monte-Carlo Power Estimation
9.5.2 Advanced Sampling Techniques
9.5.3 Vector Compaction
9.6
Probabilistic methods
9.6.1 Combinational Circuits
9.6.2 Real-Delay Gate Power Estimation
9.6.3 Sequential Circuits
9.7
Conclusions

169
170
170
170
172
172
174
175
176
176
178
178
180
182
186
187
193
196
198

References

199

Part II

169

LOW POWER DESIGN STORIES

10
Low-Power Design for Safety-Critical Applications

205

Contents

ix

Athanassios Kakarountas, Kyriakos Papadomanolakis and Costas Goutis

10.1 Introduction
10.2 Basic background on testing
10.2.1 Safety properties
10.2.2 Safe operation constraints vs. low-power techniques
10.3 Unsuitable design techniques for safety-critical applications
10.3.1 Unsuitable design strategies
10.3.2 Unsuitable low-power techniques
10.4 Low-power and safely-operating circuits
10.4.1 Appropriate low-power techniques for safe operation
10.4.2 Safe-operating circuits
10.4.3 Transforming circuits into TSC circuits
10.4.4 Evaluating the presented design techniques
10.5 Conclusions

205
206
207
212
213
214
216
218
218
219
221
231
232

References

233

11
Design of a Low Power Ultrasound Beamformer ASIC
Robert Schwann, Thomas Heselhaus, Oliver Weiss and Tobias G. Noll
11.1 Introduction
11.2 The Key to Physically Oriented Design: Automated Datapath Generation
11.3 Beamformers System Overview and Requirements
11.4 Optimization and Benchmarks of Basic Building Blocks
11.4.1 Coarse Delay Unit: Optimization of Customized Memories
11.4.2 Delay Generator
11.4.3 Fine Delay Interpolation Filter
11.4.4 Apodization Multiplier
11.4.5 Accumulation Chain
11.5 Conclusion

239
242
243
243
249
254
261
263
265

References

266

12
Epilogue
Christian Piguet

271

235
236

Contributing Authors

Labros Bisdounis was born in Agrinio, Greece, in 1970. He received the

Diploma and the Ph.D. degrees in Electrical Engineering from the Department
of Electrical and Computer Engineering, University of Patras, Greece, in 1993
and 1999, respectively. His Ph.D. thesis is in the area of timing and power
modeling of submicrometer CMOS circuits. During his collaboration with
the above department he participated as a researcher in several EU projects
related to VLSI design. Since 2000, he is with the Development Programmes
Department of INTRACOM S.A., Athens, Greece, working on the design and
development of VLSI circuits and systems. His main research interests is on
various aspects of VLSI circuits and systems design such as: circuit timing
analysis, power dissipation modeling, design and analysis of submicrometer
CMOS circuits, low-power and high-speed CMOS digital circuits and systems
design and System-on-Chip design for telecom applications. Dr. Bisdounis has
published 20 papers in international journals and conferences on these areas,
and he has received more than 70 references. He is a member of the Technical
Chamber of Greece.
Alexander Chatzigeorgiou received the Diploma in Electrical Engineering and
the Ph.D. degree in Computer Science, from the Aristotle University of Thessaloniki, Thessaloniki, Greece, in 1996 and 2000, respectively. From 1997 to
1999 he was with Intracom S.A., Greece, as a telecommunications software
designer. Since May 2002 he has been with the Department of Applied Informatics at the University of Macedonia, Thessaloniki, Greece, as a Lecturer
in Software Engineering and Object-Oriented Design. His research interests
include low-power hardware and software design, embedded systems architecture and timing and power modeling of digital CMOS circuits. He is a member
of the IEEE and the Technical Chamber of Greece.
Costas Goutis was a Lecturer at the School of Physics and Mathematics at the
University of Athens, Greece, from 1970 to 1972. In 1973, he was the Technical
Manager in the Greek P.T.T., responsible for the installation and maintenance of

xx

DESIGNING CMOS CIRCUITS FOR LOW POWER

the telephone exchanges in a large provincial region. He was Research Assistant

and Research Fellow in the Department of Electrical and Electronic Engineering at the University of Strathclyde, U.K., from 1976 to 1979, and Lecturer in
the Department of Electrical and Electronic Engineering at the University of
Newcastle upon Tyne, U.K., from 1979 to 1985. Since 1985 he has been Associate Professor and Full Professor in the Department of Electrical and Computer
Engineering, University of Patras, Greece. His recent research interests focus
on VLSI Circuit Design, Low Power VLSI Design, Systems Design, Analysis
and Design of Systems for Signal Processing and Telecommunications. He has
published more than 160 papers in international journals and conferences. He
has been awarded a large number of Research Contracts from ESPRIT, RACE,
IST and National Programs. Prof. Goutis has close collaboration with the industry. His group has recently won an international low power design contest
sponsored by Intel and IBM.
Dimitrios Gouvetas received the Diploma degree in Electrical Engineering
from the Department of Electrical and Computer Engineering, University of
Patras, Greece in 1997. His Diploma thesis is in the area of CMOS Technology
for Low Power and High Speed Circuits. He is a member of the Technical
Chamber of Greece.
Thomas Heselhaus received the Dipl.-Ing. degree in 1998 from Aachen University of Technology. Since 1998 he has been working as a research assistant at
the Chair of Electrical Engineering and Computer Systems, Aachen University
of Technology. His main topic are memory architectures and the modelling and
optimization of basic cells.
Athanassios Kakarountas is a postgraduate student at the VLSI Laboratory
of the University of Patras. He received his Diploma in Electrical and Electronics Engineering at the University of Patras. The research eld his Ph. D.
thesis is based on is in the area of Fault detection and fault tolerance in VLSI
designing. He has the working experience of two ESPRIT European projects :
i) LPGD : Contribution in the formation of a low power methodology/ ow and
its application to the implementation of DCS1800 - GSM/DECT Modulator
Demodulator for a DECT/GSM (DCS1800) dual mode mobile phone and ii)
CoSafe : Design of a Low Power safety-critical pump for in-vein infusion in
collaboration with Micrel Medical Devices Ltd.
Odysseas Koufopavlou received his Diploma and the Ph.D. degrees in Electrical Engineering in 1983 and 1990, both from University of Patras, Greece. From

Contributing Authors

xxi

1990 to 1994 he was at the IBM Thomas J. Watson Research Center, Yorktown
Heights, NY, USA. He is currently an Associate Professor with the Department
of Electrical and Computer Engineering, University of Patras. His research interests include VLSI, low power design, and high performance communication
subsystems architecture and implementation. He served as conference General Chair of the 1999 International Conference on Electronics, Circuits and
Systems, and on organizing committees and technical program committees of
many major conferences. He leads several projects, the Greek government, and
major companies. Dr. Koufopavlou has published 83 journal and conference
papers and received patents and inventions. He is a member of IEEE, IFIP 10.5
WG and the Technical Chamber of Greece.
Spiridon Nikolaidis was born in Eleochori of Kavala, Greece in 1965. He
received the Diploma and Ph.D. degrees in Electrical Engineering from Patras
University, Greece, in 1988 and 1994, respectively. Since September 1996
he has been with the Department of Physics of the Aristotle University of
Thessaloniki, Thessaloniki, Geece. He is now an assistant professor at this
Department in the eld of digital design. His research interests include CMOS
gate propagation delay and power-consumption modeling, high speed and low
power CMOS circuit design techniques, power estimation of DSP architectures,
and design of high speed and low power DSP architectures. He is author and coauthor in more than 60 papers and articles in conferences. He also participates
in many European (ESPRIT, IST) and Greek government projects.
Tobias G. Noll received the Ing. (grad.) degree in Electrical Engineering
from the Fachhochschule Koblenz in 1974, the Dipl.-Ing. degree in Electrical
Engineering from the Technical University of Munich in 1982, and the Dr.-Ing.
degree from the Ruhr-University of Bochum in 1989. From 1974 to 1976, he
was with the Max-Planck-Institute of Radio Astronomy, Bonn. Since 1976 he
was with the Corporate Research and Development Department of Siemens and
since 1987 he headed a group of laboratories concerned with CMOS circuits for
digital signal processing. In 1992, he joined the RWTH Aachen University of
Technology where he is a Professor holding the Chair of Electrical Engineering
and Computer Systems. His activities focus on low power deep submicron
CMOS architectures, circuits and design methodologies, as well as digital signal
processing for communications and medicine electronics.
Vassilis Paliouras received the Diploma in electrical engineering in 1992 and
the Ph.D. degree in electrical engineering in 1999, from the Electrical and
Computer Engineering Department, University of Patras, Greece. He works
as a researcher at the VLSI Design Laboratory, ECE Dept., while teaching

xxii

DESIGNING CMOS CIRCUITS FOR LOW POWER

microprocessor-based system design at the Computer Engineering and Informatics Dept., both at the University of Patras, Greece. His research interests
include computer arithmetic algorithms and circuits, microprocessor architecture, and VLSI signal processing, areas where he has published more than 30
conference and journal articles. Dr. Paliouras received the MEDCHIP VLSI
Design Award in 1997. He is also the recipient of the 2000 IEEE Circuits and
Systems Society Guillemin-Cauer best paper Award. He is a Member of ACM,
SIAM, and the Technical Chamber of Greece.
Kyriakos Papadomanolakis is a postgraduate student at the VLSI Laboratory
of the University of Patras. He received his Diploma in Electrical and Electronics Engineering at the University of Patras. He is currently working on his
Ph. D. thesis in the area of Hardware safety in VLSI designing at the VLSI
Laboratory of the University of Patras, at Rion. He has the working experience
of two ESPRIT European projects: i) ASPIS: Contribution in the designing of
a DECT/GSM (DCS1800) dual mode mobile phone, in INTRACOM S.A. at
the department of R&D and ii) CoSafe: Design of a Low Power safety-critical
pump for in-vein infusion in collaboration with Micrel Medical Devices Ltd.
Christian Piguet received the M. S. and Ph. D. degrees in electrical engineering from the EPFL, respectively in 1974 and 1981. He joined the Centre
Electronique Horloger S.A., Neuchtel, Switzerland, in 1974. He is now Head
of the Ultra Low Power Circuits section at the CSEM S.A. He is presently
involved in the design of low-power low-voltage integrated circuits. He is Professor at EPFL and also lectures at the University of Neuchtel, Switzerland.
He is author or co-author of more than 100 scientic papers and has contributed
to numerous advanced engineering courses.
Robert Schwann received the Dipl.-Ing. degree in 1997 from Aachen University of Technology. Since 1998 he has been working as a research assistant at
the Chair of Electrical Engineering and Computer Systems, Aachen University
of Technology. His eld of research are the signal processing and image quality
of medical ultrasound systems.
Dimitrios Soudris received his Diploma in Electrical Engineering from the
University of Patras, Greece, in 1987. He received the Ph.D. Degree from in
Electrical Engineering, from the University of Patras in 1992. He is currently
working as Ass. Professor in Dept. of Electrical and Computer Engineering,
Democritus University of Thrace, Greece. His research interests include low
power design, parallel architectures, embedded systems design, and VLSI sig-

Contributing Authors

xxiii

nal processing. He has published more than 80 papers in international journals

and conferences. He was leader and principal investigator in numerous research
projects funded from the Greek Government and Industry as well as the European Commission (ESPRIT II-III-IV and 5th IST). He has served as General
Chair and Program Chair for the International Workshop on Power and Timing
Modelling, Optimisation, and Simulation (PATMOS). Recently, received an
award from INTEL and IBM for the project results of LPGD #25256 (ESPRIT
IV). He is a member of the IEEE, the VLSI Systems and Applications Technical
Committee of IEEE CAS and the ACM.
Thanos Stouraitis received a B.S. in Physics and an M.S. in Electronic Automation from the University of Athens, Greece, in 1979 and 1981, respectively,
an M.S. in Electrical Engineering from the University of Cincinnati in 1983 and
the Ph.D. degree from the Univ. of Florida in 1986. He was awarded the Outstanding Ph.D. Dissertation award of the University of Florida and a Certicate
of Appreciation by the IEEE Society of Circuits and Systems in 1997. He is
a Professor of Electrical and Computer Engineering at the University of Patras, Greece. He has served on the faculty of the University of Florida and
the Ohio State University. He has published 2 books, several book chapters,
about 30 journal and 70 conference papers in the areas of computer architecture,
computer arithmetic, VLSI signal and image processing, and low-power processing. He is currently the chair of the IEEE Circuits and Systems Societys
technical committee on VLSI Systems and Applications, while he serves on
the digital signal processing and the multimedia systems committees. He has
served as the General Chair of the IEEE 3rd Int. Conference on Electronics,
Circuits, and Systems (ICECS 96), co-Program chair for EUSIPCO 98, and
regularly serves on the Program Committee of various circuits-and-systems and
signal-processing conferences.
Antonios Thanailakis was born in Greece on August 5, 1940. He received
B.Sc. degrees in physics and electrical engineering from the University of
Thessaloniki, Greece, 1964 and 1968, respectively, and the MSc . and Ph.D.
Degrees in electrical engineering and electronics from UMIST, Manchester,
U.K. in 1968 and 1971, respectively. He has been a Professor of Microelectronics in Dept. of Electrical and Computer Eng., Democritus Univ. of Thrace,
Xanthi, Greece, since 1977. He has been active in electronic device and VLSI
system design research since 1968. His current research activities include microelectronic devices and VLSI systems design. He has published a great number of scientic and technical papers, as well as ve textbooks. He was leader
for carrying out research and development projects funded by Greece, EU, or

xxiv

DESIGNING CMOS CIRCUITS FOR LOW POWER

other organizations on various topics of Microelectronics and VLSI Systems

Design (e.g. NATO, ESPRIT, ACTS, STRIDE).
George Theodoridis received the Diploma in Electrical Engineering for the
University of Patras in 1994, and the Ph.D. Degree in Electrical and Computer
Eng. from the same institution in 2001. He is currently working as researcher
at the VLSI Design laboratory of Electrical and Computer Eng. Department of
Patras University. His working interests include several aspects of development
of methodologies and techniques for power estimation and optimization, recongurable computing, parallel architectures and embedded DSP systems. He has
published more than 20 papers in international journals and conferences. He
also has participated in numerous research projects funding from the European
Union and Greek Government and Industry.
Oliver Weiss received the Dipl.-Ing. degree in 1995 from Aachen University
of Technology. Since 1995 he has been working as a research assistant at
the Chair of Electrical Engineering and Computer Systems, Aachen University
of Technology. His main research interest is the development of a datapath
generator for the physically oriented design of optimized CMOS macros for
digital signal processing.

Foreword

This book is the fourth in a series on novel low power design architectures,
methods and design practices. It results from of a large European project started
in 1997, whose goal is to promote the further development and the faster and
wider industrial use of advanced design methods for reducing the power consumption of electronic systems.
Low power design became crucial with the wide spread of portable information and communication terminals, where a small battery has to last for a
long period. High performance electronics, in addition, suffers from a permanent increase of the dissipated power per square millimeter of silicon, due
to the increasing clock-rates, which causes cooling and reliability problems or
otherwise limits the performance.
The European Unions Information Technologies Programme Esprit did
therefore launch a Pilot action for Low Power Design, which eventually grew
to 19 R&D projects and one coordination project, with an overall budget of 14
million EURO. It is meanwhile known as European Low Power Initiative for
Electronic System Design (ESD-LPD) and will be completed in the year 2002.
It involves to develop or demonstrate new design methods for power reduction,
while the coordination project takes care that the methods, experiences and
results are properly documented and publicised.
The initiative addresses low power design at various levels. This includes
system and algorithmic level, instruction set processor level, custom processor
level, RT-level, gate level, circuit level and layout level. It covers data dominated
and control dominated as well as asynchronous architectures. 10 projects deal
mainly with digital, 7 with analog and mixed-signal, and 2 with software related
aspects. The principal application areas are communication, medical equipment
and e-commerce devices.

xxvi

DESIGNING CMOS CIRCUITS FOR LOW POWER

The following list describes the objectives of the 20 projects. It is sorted by

decreasing funding budget.
CRAFT CMOS Radio Frequency Circuit Design for Wireless Application
Advanced CMOS RF circuit design including blocks such as LNA,
down converter mixers & phase shifters, oscillator and frequency
synthesiser, integrated lters delta sigma conversion, power amplier
Development of novel models for active and passive devices as well
as ne-tuning and validation based on rst silicon fabricates
Analysis and specication of sophisticated architectures to meet in
particular low power single chip implementation
PAPRICA Power and Part Count Reduction Innovative Communication Architecture
Feasibility assessment of DQIF, through physical design and characterisation of the core blocks
Low-power RF design techniques in standard CMOS digital process
RF design tools and framework; PAPRICA Design Kit.
Demonstration of a practical implementation of a specic application
MELOPAS Methodology for Low Power Asic design
To develop a methodology to evaluate the power consumption of a
complex ASIC early on in the design ow
To develop a hardware/software co-simulation tool
To quickly achieve a drastic reduction on the power consumption
of electronic equipment
TARDIS Technical Coordination and Dissemination
To organise the communication between design experiments and to
exploit their potential synergy
To guide the capturing of methods and experiences gained in the
design experiments
To organise and promote the wider dissemination and use of the
gathered design know-how and experience

xxvii
LUCS Low Power Ultrasound Chip Set.
Design methodology on low power ADC, memory and circuit design
Prototype demonstration of a handheld medical ultrasound scanner
ALPINS Analog Low Power Design for Communications Systems
Low-voltage voice band smoothing lters and analog-to-digital and
digital-to-analog converters for an analog front-end circuit of a
DECT system
High linear transconductor-capacitor (gm-C) lter for GSM Analog
Interface Circuit operating at supply voltages as low as 2.5V
Formal verication tools, which will be implemented in the industrial partners design environment. These tools support the complete
design process from system level down to transistor level
SALOMON System-level analog-digital trade-off analysis for low power
A general top-down design ow for mixed-signal telecom ASICs
High-level models of analog and digital blocks and power estimators
for these blocks
A prototype implementation of the design ow with particular software tools to demonstrate the general design ow
DESCALE Design Experiment on a Smart Card Application for Low Energy
The application of highly innovative handshake technology
Aiming at some 3 to 5 times less power and some 10 times smaller
peak currents compared to synchronously operated solutions
SUPREGE A low power SUPerREGEnerative transceiver for wireless data
transmission at short distances
Design trade-offs and optimisation of the micro power receiver /
transmitter as a function of various parameters (power consumption,
area, bandwidth, sensitivity, etc)
Modulation / demodulation and interface with data transmission
systems
Realisation of the integrated micro power receiver / transmitter
based on the super-regeneration principle

xxviii

DESIGNING CMOS CIRCUITS FOR LOW POWER

PREST Power REduction for System Technologies

Survey of contemporary Low Power Design techniques and commercial power analysis software tools
Investigation of architectural and algorithmic design techniques
with a power consumption comparison
Investigation of Asynchronous design techniques and Arithmetic
styles
Set-up and assessment of a low power design ow
Fabrication and characterisation of a Viterbi demonstrator to assess
the most promising power reduction techniques
DABLP Low Power Exploration for Mapping DAB Applications to MultiProcessors
A DAB channel decoder architecture with reduced power consumption
Rened and extended ATOMIUM methodology and supporting
tools
COSAFE Low Power Hardware-Software Co-Design for Safety-Critical Applications
The development of strategies for power efcient assignment of
safety critical mechanisms to hardware or software
The design and implementation of a low-power, safety-critical ASIP,
which realises the control unit of a portable infusion, pump system
AMIED Asynchronous Low-Power Methodology and Implementation of an
Encryption/Decryption System
Implementation of the IDEA encryption/decryption method with
drastically reduced power consumption
Advanced low power design ow with emphasis on algorithm and
architecture optimisations
Industrial demonstration of the asynchronous design methodology
based on commercial tools

xxix
LPGD A Low-Power Design Methodology/Flow and its Application to the
Implementation of a DCS1800-GSM/DECT Modulator/Demodulator
To complete the development of a top-down, low power design
methodology/ow for DSP applications
To demonstrate the methods at the example of an integrated
GFSK/GMSK Modulator-Demodulator (MODEM)
for DCS1800-GSM/DECT applications
SOFLOPO Low Power Software Development for Embedded Applications
Develop techniques and guidelines for mapping a specic algorithm
code onto appropriate instruction subsets
Integrate these techniques into software for the power-conscious
ARM-RISC and DSP code optimisation
I-MODE Low Power RF to Base band Interface for Multi-Mode Portable
Phone
To raise the level of integration in a DECT/DCS1800 transceiver, by
implementing the necessary analog base band low-pass lters and
data converters in CMOS technology using low power techniques
COOL-LOGOS Power Reduction through the Use of Local dont Care Conditions and Global Gate Resizing Techniques: An Experimental Evaluation.
To apply the developed low power design techniques to the existing
24-bit DSP, which is already fabricated
To assess the merit of the new techniques using experimental silicon
through comparisons of the projected power reduction (in simulation) and actually measured reduction of new DSP; assessment of
the commercial impact
LOVO Low Output VOltage DC/DC converters for low power applications
Development of technical solutions for the power supplies of advanced low power systems, comprising the following topics
New methods for synchronous rectication for very low output voltage power converters

xxx

DESIGNING CMOS CIRCUITS FOR LOW POWER

PCBIT Low Power ISDN Interface for Portable PCs

Design of a PC-Card board that implements the PCBIT interface
Integrate levels 1 and 2 of the communication protocol in a single
ASIC
Incorporate power management techniques in the ASIC design:
system level: shutdown of idle modules in the circuit
gate level: precomputation, gated-clock FSMs
COLOPODS Design of a Cochlear Hearing Aid Low-Power DSP System
Selection of a future oriented low-power technology enabling future
power reduction through integration of analog modules
Design of a speech processor IC yielding a power reduction of 90%
compared to the 3.3 Volt implementation

xxxi
The low power design projects have achieved the following results:
Projects, who have designed a prototype chip, can demonstrate a power
reduction of 10 to 30 percent.
New low power design libraries have been developed.
New proven low power RF architectures are now available.
New smaller and lighter mobile equipment is developed.
Instead of running a number of Esprit projects at the same time independently of each other, during this pilot action the projects have collaborated
strongly. This is achieved mostly by the novelty of this action, which is the
presence and role of the coordinator: DIMES - the Delft Institute of Microelectronics and Submicron-technology, located in Delft, the Netherlands
(http://www.dimes.tudelft.nl). The task of the coordinator is to co-ordinate,
facilitate, and organize:
The information exchange between projects.
The systematic documentation of methods and experiences.
The publication and the wider dissemination to the public.
The most important achievements, credited to the presence of the coordinator
are:
New personnel contacts have been made, and as a consequence the resulting synergy between partners resulted in better and faster developments.
The organization of low power design workshops, special sessions at
conferences, and a low power design web site,
http://www.esdlpd.dimes.tudelft.nl. At this site all public reports of the
projects can be found and all kind of information about the initiative
itself.
The used design methodology, design methods and/or design experience
are disclosed, are well documented and available.
Based on the work of the projects, in cooperation with the projects, the
publication of a low power design book series is planned. Written by
members of the projects this series of books on low power design will
disseminate novel design methodologies and design experiences, which
were obtained during the runtime of the European Low Power Initiative
for Electronic System Design, to the general public.

xxxii

DESIGNING CMOS CIRCUITS FOR LOW POWER

In conclusion, the major contribution of this project cluster is that, except the
already mentioned technical achievements, the introduction of novel knowledge
on low power design methods into the mainstream development processes is
accelerated.
We would like to thank all project partners from all the different companies
and organizations who make the Low Power Initiative a success.
Rene van Leuken, Reinder Nouta, Alexander de Graaf, Delft, May 2002

Introduction

Modern electronic systems have reached a signicant turning point in the last
decade, from low performance products such as wristwatches and calculators
to high performance products such as laptops and personal digital assistants.
The introduction of these devices to the consumer market raised to the surface
a characteristic that had been previously omitted. This was low power dissipation. Gradually, engineers invented novel techniques, which may be included
in efcient design methodologies, for designing and implementing efcient circuits not only in terms of area and performance, as they were used to, but in the
term of low power consumption.
The material in this book is based on the background and the innovative results of the different partners involved in the AMIED, LPGD, PREST, COSAFE,
and LUCS projects of the European Low Power Initiative for Electronic System Design under the successful coordination of DIMES, Delft. The partners
have been studying for many years low-power design eld introducing novel
concepts and efcient techniques. Due to close collaboration of academic and
industrial research groups the presented material have been inuenced by the
plethora of disseminations e.g. public deliverables, technical meetings, workshops, during the projects execution.
The book consists of two parts: The rst part includes the low power design techniques for power optimization and estimation, while the second one
provides the results from the projects COSAFE and LUCS. Starting from the
description of the power consumption sources, low power optimization and estimation techniques for logic design level, circuit/transistor design level, and
layout design level are provided in eight chapters (i.e. Chapters 2-9). The
next two chapters describe the novel low power techniques, which were used
during the implementation of the safety-critical Application Specic Instruction Processor designed in COSAFE project, and the implementation of the
low power 16-channel ultrasound beamformer application specic integrated
circuit (ASIC) designed for LUCS project.

xxxiv

DESIGNING CMOS CIRCUITS FOR LOW POWER

A top-down approach with respect to the design level is adopted in the presentation of the low power design techniques . However,it was not possible to
present in detail manner all the low power optimization and estimation techniques from the logic level to the layout level. Only the most important research
contributions presented in a tutorial manner, are included. The book can also
be used as a textbook for undergraduate and graduate students, VLSI design
engineers,and professionals, who have had a basic knowledge of VLSI digital
design.
The authors of the chapters of this book together with the editors would
like to use this opportunity to thank the many people, i.e. colleagues and Ph.D.
students, whose dedication and industry during the projects execution lead to the
introduction of novel scientic results and realization of innovative integrated
systems.
The authors of Chapter 3 and 9 would like to thank Dr. S. Theoharis for his
contribution in the software development of logic optimization and estimation
tools, which were necessary for making power measurements.
The authors of Chapter 6 wish to acknowledge the discussions with Dr.
Karagianni, who signicantly inuenced the particular chapter. Also the authors appreciate the nancial support from the "C. Caratheodorys" fund for the
University of Patras.
The authors of Chapter 10 would like to thank V. Spiliotopoulos for his
support in the designing and realization of the COSAFE ASIP. Also, many
thanks to V. Kokkinos for his contribution in the implementation of the many
fault-secure multiplier designs.
All authors of this book together with the editors would like to thank DIMES,
Delft, for their continuous support during the running of the low power projects
for the dissemination of the scientic results. This book is one of the activities
of this dissemination task.
The authors of Chapter 4 would like to thank the people, who contributed
to PREST, whose public deliverable reports used as an inspiration source for
chapters preparation.
Last but not least, D. Soudris would like to thank his parents for being a
constant source of moral support and for rmly imbibing into him from a very
young age that perseverantia omnia vincit - it is this perseverance that kept him
going. This book is dedicated to them.
Dimitrios Soudris, Christian Piguet, Costas Goutis, May 2002

Chapter 5
CIRCUIT TECHNIQUES FOR
REDUCING POWER CONSUMPTION
IN ADDERS AND MULTIPLIERS
Labros Bisdounis
INTRACOM S.A., Athens, Greece
[email protected]

Dimitrios Gouvetas
Odysseas Koufopavlou
University of Patras, Rio, Greece
[email protected]

Abstract

An important issue in the design of VLSI Circuits is the choice of the basic circuit
approach and topology for implementing various logic and arithmetic functions
such as adders and multipliers. In this chapter, several static and dynamic CMOS
circuit design styles are evaluated in terms of area, propagation delay and power
dissipation. The different design styles are compared by performing detailed
transistor-level simulations on a benchmark circuit (ripple carry adder) using
HSPICE, and analyzing the results in a statistical way. After the comparison
between the different design styles, a number of well known types of adders
(ripple carry, carry skip, carry lookahead, carry select etc.) are compared in terms
of propagation delay, number of gates and logic transitions average number.
Furthermore, power measurements and comparisons for a number of well-known
multipliers are provided. Based on the results of the provided analysis some of
the tradeoffs that are possible during the design phase in order to improve the
circuit power-delay product are identied.

Keywords:

circuit design techniques, circuit macroblocks, adders, circuit styles

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DESIGNING CMOS CIRCUITS FOR LOW POWER

5.1

Introduction

Much of the research efforts of the past years in the area of digital electronics
has been directed towards increasing the speed of digital systems. Recently,
the requirement of portability and the moderate improvement in battery performance indicate that the power dissipation is one of the most critical design
parameters [1]. The three most widely accepted metrics to measure the quality of a circuit or to compare various circuit styles are area, delay and power
dissipation. Portability imposes a strict limitation on power dissipation while
still demands high computational speeds. Hence, in recent VLSI systems the
power-delay product becomes the most essential metric of performance.
The reduction of the power dissipation and the improvement of the speed
require optimizations at all levels of the design procedure. In this chapter,
the proper circuit style and methodology is considered. Since, most digital
circuitry is composed of simple and/or complex gates, we study the best way
to implement adders in order to achieve low power dissipation and high speed.
Several circuit design techniques are compared in order to nd their efciency
in terms of speed and power dissipation. A review of the existing CMOS
circuit design styles is given, describing their advantages and their limitations.
Furthermore, a four-bit ripple carry adder for use as a benchmark circuit was
designed in a full-custom manner by using the different design styles, and
detailed transistor-level simulations using HSPICE [2] were performed. Also,
various designs and implementations of four multipliers are analysed in the
terms of delay and power consumption. Two ways of power measurements are
used.
Conventional static CMOS has been a technique of choice in most processor
design. Alternatively, static pass transistor circuits have also been suggested for
low-power applications [3]. Dynamic circuits, when clocked carefully, can also
be used in low-power, high speed systems [4]. However, several other design
techniques need to be applied and evaluated along with these circuit styles in
order to improve the speed and reduce the power dissipation of VLSI systems.
In this chapter we study eight different CMOS logic styles:
Conventional Static CMOS - CSL,
Complementary Pass-transistor - CPL [5],
Double Pass-transistor - DPL [6],
Static and Dynamic Differential Cascode Voltage Switch - DCVSL [7,8],
Static Differential Split-level - SDSL [9],
Dual-Rail Domino - DRDL [10,11], and
Enable/disabled CMOS Differential - ECDL [12].

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73

The rest of the chapter is structured as follows. In the next section a brief
introduction of the power dissipation and the delay in CMOS circuits is given. In
section 3, the CMOS adder logic styles and their characteristics are described
in details. The different adder logic styles are compared in terms of speed,
power dissipation and silicon area, in section 4. Also, the power-delay product
of the designs is considered, due to the importance of this metric in modern
VLSI applications. Comparison results among different realizations of a 16-bit
adder in terms of area, delay, and power are presented in Section 6. The next
section provides results for four implementations of multipliers. Finally, the
main points are summarized in Section 7 of conclusions.

5.2

Power and Delay in CMOS Circuits

Since the objective is to investigate the tradeoffs that are possible at the circuit
level in order to reduce power dissipation while maintaining the overall system
throughput, we must rst study the parameters that affect the power dissipation
and the speed of a circuit. It is well known that one of the major advantage
of CMOS circuits over single polarity MOS circuits, is that the static power
dissipation is very small and limited to leakage. However, in some cases such as
bias circuitry and pseudo-nMOS logic, static power is dissipated. Considering
that in CMOS circuits the leakage current between the diffusion regions and
the substrate is negligible, the two major sources of power dissipation are the
switching and the short-circuit power dissipation [1],
(5.1)

qq i

h
g
u s r pq i h g e c b
y q q i x w vtCq @4fd6a

e
fc

where
is the node transition activity factor,
is the load capacitance,
is the supply voltage, is the switching frequency.
is the current which
arises when a direct path from power supply to ground is caused, for a short
period of time during low to high or high to low node transitions [13]. The
switching component of power arises when energy is drawn from the power
supply to charge parasitic capacitors. It is the dominant power component in a
well designed circuit and it can be lowered by reducing one or more of ,
,
and , while retaining the required speed and functionality.
Even though the exact analysis of circuit delay is quite complex, a simple
rst-order derivation can be used [14,15] in order to show its dependency of the
circuit parameters

xwu

h e
g fc

(5.2)

y " iq q Sq q i 
i h
Ug

qq i

6q

"i

where depends on the transistors aspect ratio ( / and other device parameters,
is the transistor threshold voltage, and is the velocity saturation
index which varies between 1 and 2 ( is equal to 1.4 for the 1.5 m process

July 12, 2002, 2:00pm

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DESIGNING CMOS CIRCUITS FOR LOW POWER

technology which is used in the experiments of the next section). Since a

quadratic improvement in power dissipation may be obtained by lowering the
supply voltage (equation (5.1)), many researchers have investigated the effects
of lowering the supply voltage in VLSI circuits. Unfortunately, reducing the
supply voltage reduces power, but the delay increases (equation (5.2)) with the
effect being more drastic at voltages close to the threshold voltage [16]. Equations (5.1) and (5.2) indicate that by reducing the node parasitic capacitance
in a CMOS circuit, the power dissipation is reduced and the circuit speed is
increased.

5.3

CMOS Circuit Design Styles

In the following, the circuit design styles are described using the full adder
circuit, which is the most commonly used cell in arithmetic units. Also, their
characteristics in terms of power dissipation and delay are investigated.

5.3.1

Conventional Static CMOS Logic - CSL

Conventional Static CMOS logic is used in most chip designs in the recent
VLSI applications. The schematic diagram of a conventional static CMOS
full adder cell is illustrated in Figure 5.1. The signals noted with - are the
complementary signals. The pMOSFET network of each stage is the dual
network of the nMOSFET one. In order to obtain a reasonable conducting
current to drive capacitive loads the width of the transistors must be increased.
This results in increased input capacitance and therefore high power dissipation
and propagation delay.

A A

-A

-B

-B

-C

-B

-A

B -B

-A

-A

-C

-C

CARRY

-A
-C

-A
-B

-B

SUM

D R A F T

B -B

-A

Figure 5.1.

-B

A A

-A

Conventional static CMOS full adder

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Circuit Techniques forReducing Power Consumptionin Adders and Multipliers

5.3.2

75

Complementary Pass-Transistor Logic - CPL

The main concept behind CPL [5] is the use of only an nMOSFET network
for the implementation of logic functions. This results in low input capacitance
and high speed operation. The schematic diagram of the CPL full adder circuit
is shown in Figure 5.2. Because the high voltage level of the pass-transistor
outputs is lower than the supply voltage level by the threshold voltage of the
pass transistors, the signals have to be amplied by using CMOS inverters at
the outputs. CPL circuits consume less power than conventional static circuits
because the logic swing of the pass transistor outputs is smaller than the supply
voltage level. The switching power dissipated from charging or discharging the
pass transistor outputs is given by

r q
p h o l Gm l j fGh geG
n k i f hf d

(5.3)

l u "f Sh h g4m l j ff
t s f d k i

where
. In the case of conventional static CMOS circuits
the voltage swing at the output nodes is equal to the supply voltage, resulting in
higher power dissipation. To minimize the static current due to the incomplete
turn-off of the pMOSFET in the output inverters, a weak pMOSFET feedback
device can also be added in the CPL circuits of Figure 5.2, in order to pull the
pass-transistor outputs to full supply voltage level. However, this will increase
the output node capacitance, leading to higher switching power dissipation and
higher propagation delay.
B

-B

-A

-A

-C

-B
-C

SUM

-A

CARRY

Figure 5.2. Complementary pass-transistor full adder

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DESIGNING CMOS CIRCUITS FOR LOW POWER

5.3.3

Double Pass-Transistor Logic - DPL

DPL [6] is a modied version of CPL. The circuit diagram of the DPL full
adder is given in Figure 5.3. In DPL circuits full-swing operation is achieved by
simply adding pMOSFET transistors in parallel with the nMOSFET transistors.
Hence, the problems of noise margin and speed degradation at reduced supply
voltages which are caused in CPL circuits due to the reduced high voltage level,
are avoided. However, the addition of pMOSFETs results in increased input
capacitances.

-C

-A
B

SUM

-B

-B

-C

B
-A

Figure 5.3.

5.3.4

CARRY

Double pass-transistor full adder

Static Differential Cascode Voltage Switch Logic SDCVSL

Static DCVSL [7], is a differential style of logic requiring both true and complementary signals to be routed to gates. Figure 5.4 shows the circuit diagram of
the static DCVSL full adder. Two complementary nMOSFET switching trees
are constructed to a pair of cross-coupled pMOSFET transistors. Depending on

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Circuit Techniques forReducing Power Consumptionin Adders and Multipliers

the differential inputs one of the outputs is pulled down by the corresponding
nMOSFET network. The differential output is then latched by the cross-coupled
pMOSFET transistors. Since the inputs drive only the nMOSFET transistors of
the switching trees, the input capacitance is typically two or three times smaller
than that of the conventional static CMOS logic.

SUM

-SUM

CARRY

-A

-A

-C

-B

-B

-C

Figure 5.4.

5.3.5

-B
B

-CARRY

-C

Static differential cascode voltage switch full adder

Static Differential Split-level Logic - SDSL

A variation of the differential logic described above is the Static DSL [9].
The SDSL full adder circuit diagram is illustrated in Figure 5.5. Two nMOSFET transistors with their gates connected to a reference voltage (
,
: nMOSFET threshold voltage) are added to reduce the
logic swing at the output nodes. The output nodes are clamped at the half of the
supply voltage level. Thus, the circuit operation becomes faster than standard
DCVSL circuits. However, due to the incomplete turn-off of the cross-coupled
pMOSFET transistors, SDSL circuits dissipate high static power dissipation.
Also, the addition of two extra nMOSFET transistors per gate results in area
overhead.

| y
}{ z "x

x

"x "  fx

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DESIGNING CMOS CIRCUITS FOR LOW POWER

-SUM

SUM

Vref
- CARRY

CARRY

Vref
-A

-A

-B
-B

B
B

-C

-B

5.3.6

-C
C

Figure 5.5.

-C

Static differential split-level full adder

Dual-Rail Domino Logic - DRDL

Dual-Rail Domino Logic [10,11] is a precharged circuit technique which

is used to improve the speed of CMOS circuits. Figure 5.6 shows a DualRail Domino full adder cell. A domino gate consists of a dynamic CMOS
circuit followed by a static CMOS buffer. The dynamic circuit consists of a
pMOSFET precharge transistor and an nMOSFET evaluation transistor with
the clock signal (CLK) applied to their gate nodes, and an nMOSFET logic
block which implements the required logic function. During the precharge
phase (CLK = 0) the output node of the dynamic circuit is charged through
the precharged pMOSFET transistor to the supply voltage level. The output of
the static buffer is discharged to ground. During the evaluation phase (CLK
= 1) the evaluation nMOSFET transistor is ON, and depending on the logic
performed by the nMOSFET logic block, the output of the dynamic circuit
is either discharged or it will stay precharged. Since in dynamic logic every
output node must be precharged every clock cycle, some nodes are precharged
only to be immediately discharged again as the node is evaluated, leading to
higher switching power dissipation [1]. One major advantage of the dynamic,
precharged design styles over the static styles is that they eliminate the spurious
transitions and the corresponding power dissipation. Also, dynamic logic does
not suffers from short-circuit currents which ow in static circuits when a direct

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Circuit Techniques forReducing Power Consumptionin Adders and Multipliers

79

path from power supply to ground is caused. However, in dynamic circuits,

additional power is dissipated by the distribution network and the drivers of the
clock signal.

CLK
SUM

CLK

CARRY
C

-C

A
B

-A

CLK

-B
A

CLK

Figure 5.6.

5.3.7

-B B

Dual-rail domino full adder

Dynamic Differential Cascode Voltage Switch Logic

- DDCVSL

Dynamic DCVSL [8], is a combination between the domino logic and the
static DCVSL. The circuit diagram of the dynamic DCVSL full adder is given
in Figure 5.7. The advantage of this style over domino logic is the ability to
generate any logic function. Domino logic can only generate noninverted forms
of logic. For example, in the design of a ripple carry adder, two cells must be
designed for the carry propagation, one for the true carry signal and another
for the complementary one (in Figure 5.6, the cell for the true carry signal is
only shown, but the one for the complementary signal is also required). Using
DCVSL to design dynamic circuits will eliminate p-logic gates because of the
inherent availability of complementary signals. The p-logic gates usually cause
long delay times and consumes large areas.

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DESIGNING CMOS CIRCUITS FOR LOW POWER

SUM

-CARRY

CLK

-A

-A

-B

-C

-B

CARRY

-SUM

CLK

-B

-C

CLK

-C

CLK

Figure 5.7.

5.3.8

Dynamic differential cascode voltage switch full adder

Enable/disabled CMOS Differential Logic- ECDL

ECDL [12] is a self-timed differential logic which is used in the case of

implementing logic functions using iterative networks. It uses extra signals to
indicate the beginning and ending of a function evaluation, in order to improve
the circuit speed. The structure of the ECDL full adder is illustrated in Figure
5.8. The signals Done i 1 and Donei are the input and output self-timing control
signals. During the disabled state, Donei 1 has a value of logic one, which
discharges both the true and the complementary outputs to logic zero. During
the enabled state, Donei 1 changes to logic zero and the topmost pMOSFET
transistor (Figure 5.8) is ON to provide power to the inverters below. Then,
depending on the logic of the differential nMOSFET network, a path exists from
one of the output nodes to ground, holding that node to ground while leaving the
other output node to be driven to logic one. One major advantage of the ECDL
circuits is that there is no minimum clocking frequency requirement. However,
ECDL circuits suffer from extra power dissipation due to the inverters which
are needed to change the polarity of the output nodes. Also, their complex
pull-up circuitry leads in extra silicon area.

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Circuit Techniques forReducing Power Consumptionin Adders and Multipliers

Done i-1
Done i

Done i-1

Done i-1
-CARRY

-SUM

SUM
M

Done i-1

CARRY
Done i-1

-A

-C

-B

-B

-A

-B

-C
C

-C

Figure 5.8. Enable/Disable CMOS differential full adder

5.4

Power, Delay and Area Comparisons of a 4-Bit Ripple

Carry Adder

The experimental results described in this section were obtained using a fourbit ripple carry adder. A general block diagram of the adder is illustrated in
Figure 5.9.

C1

S0

D R A F T

B1

FA 1

S1
Figure 5.9.

FA 0

A1

B0

C2

A2

B2

FA 2

A3

C3

S2

C in

A0

B3

FA 3

C out

S3

Block diagram of the four-bit ripple carry adder

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DESIGNING CMOS CIRCUITS FOR LOW POWER

The circuit was designed in a full custom manner for all the design styles
described in the previous section, using a 1.5 m CMOS process technology.
The channel width of the transistors was 4.8 m for the nMOSFETs, and 9.6 m
for the pMOSFETs. The design was based on the full adder cells presented in
Figures 5.1 to 5.8.
Figure 5.10 shows the layout of the conventional static four-bit ripple carry
adder, as an example of the designed circuits.

Figure 5.10. Layout of the conventional static four-bit ripple carry adder

In Table 5.1 the adder silicon area and the number of the transistors for each
design style are given. Although no extensive attempts were made to minimize
area, the numbers presented are a good indication of the relative areas of the
eight adder implementations, which account not only for the transistors, but for
the interconnections as well. For example, even though DPL adder has fewer
transistors than the CSL one, it has longer interconnections, which is reected
by its large area. Dynamic design styles and styles which uses control signals
(such as ECDL) occupy extra area for the routing of the clock and the control
signals. The smallest area is occupied by the CPL circuit, which has fewer
transistors and shorter interconnections than the other adder implementations.
After the design of the layouts, circuit equivalents were extracted for a
detailed circuit simulation using HSPICE [2] to obtain the power and delay
measurements. In our experiments, a supply voltage of 5Volts is used. All
measurements were obtained with each input supplied through a driver consisting of two minimum-sized inverters in series, and each output node driving a
minimum-sized inverter load.
The estimation of power dissipation is a difcult problem because of its data
dependency, and has received a lot of attention [17]. Some direct simulative
power estimation methods have been proposed [18,19], which are expensive in

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Circuit Techniques forReducing Power Consumptionin Adders and Multipliers

Area and number of transistors of the four-bit ripple carry adder implementations

Adder Area ( 10

CSL
CPL
DPL
SDCVSL
SDSL
DRDL
DDCVSL
ECDL

5.42
4.46
6.52
5.19
6.39
6.48
7.22
7.65

Design Style

m )

Table 5.1.

No. of Transistors
144
88
136
114
130
146
154
166

terms of time. Also, several power estimation methods have been proposed,
where possibilities are used to solve the pattern-dependence problem. However,
in order to achieve good accuracy, the spatial and temporal correlations between
internal nodes should be modeled [20,21]. An alternative way is the use of
statistical methods [22,23,17], that combines the accuracy of simulation-based
techniques with the speed of probabilistic approaches.
In this chapter, the statistical approach proposed by Burch et al. [22] is used
in order to estimate the power dissipation of our designs. Using the powermeter
sub-circuit proposed by Kang [18], HSPICE can measure the average power
consumed by a circuit given a set of input transitions and a time interval. In
the method, the inputs are randomly generated and statistical mean estimation
techniques are used to determine the nal result. In our case for each adder
design we use 200 independent, pseudorandom input transition samples, and
the power consumed for each sample is monitored by HSPICE. All
simulations were carried out at 27C, with an input frequency of 50MHz in
order to accommodate the slowest adder. The power dissipation measures do
not include the power consumed by the drivers and the loads. In Figure 5.11, the
probability distributions of the power dissipation per addition derived from the
measurements, for the eight adder implementations, are shown. Since the data
inputs are independent, power can be approximated to be normally distributed
[22]. This conclusion can also be extracted from the curves of Figure 5.11.
Hence, the mean power dissipation is given by
(5.4)

where is the sample average, is the standard deviation, is the number of

samples, and
is obtained from the distribution for a (1- )% condence

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DESIGNING CMOS CIRCUITS FOR LOW POWER

interval [24]. The mean power dissipation of the eight adder implementations
using the simulation results and the equation (4) is given in Table 5.2.
The number of the required samples is extracted using the stopping criterion
[22] of the above method

$ d

(5.5)

where is the desired percentage error in the power estimate. The error in our
statistical power analysis for = 200 and 95% condence interval (
= 1.96)
is less than 7%. In Table 5.2, the percentage error for each adder design is also
given. For the four last designs the error is quite small because of the high
normality of their distributions which leads to small standard deviation.

D R A F T

Figure 5.11.

Power dissipation histograms

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85

The delay of each design was measured directly from the output waveforms
generated by simulating the adder using HSPICE for the worst case inputs, that
is, inputs which cause the carry to ripple from the least signicant bit position to
most signicant bit position. The worst case delays of the eight adder designs
are listed in the fourth column of Table 5.2. As mentioned in Section 5.1,
the most essential metric of performance in modern VLSI applications is the
power-delay product. By multiplying each power measurement with the worst
case delay, we can found the mean power-delay product of the designs using a
method similar to that used for the mean power dissipation. Hence, the mean
power-delay product is given by

g
Figure 5.12.

(5.6)

Power-delay product histograms

where
is the sample average power-delay product. The mean powerdelay product values of the eight adder designs are listed in Table 5.2, and the
probability distributions of the power-delay product are shown in Figure 5.12.

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DESIGNING CMOS CIRCUITS FOR LOW POWER

Table 5.2. Power dissipation, delay and power-delay product of the four- bit ripple carry adder
implementations

Adder
Design
Style

Mean Power
Dissipation per
addition (mW)

Statist. Worst Case

Error Delay (nsec)
(%)

Mean
PowerDelay Product per
addition (pJ)

CSL
CPL
DPL
SDCVSL
SDSL
DRDL
DDCVSL
ECDL

0.422
0.238
0.305
0.432
2.383
0.641
0.957
1.721

6.1
4.8
6.9
6.5
0.6
1.4
0.8
0.6

2.585
0.962
1.020
3.450
10.976
1.865
3.304
4.977

6.125
4.042
3.345
7.986
4.606
2.909
3.453
2.892

0.0302
0.0208
0.0263
0.0362
0.0129
0.0091
0.0074
0.0096

0.1850
0.0841
0.0879
0.2891
0.0594
0.0265
0.0255
0.0278

As we can see in the probability distributions of Figure 5.12, the curves of

the dynamic designs (DRDL and DDCVSL) are shifted to the right, because
of the power dissipated due to the precharge cycles. The same phenomenon
occurs in the ECDL adder due to the power dissipation of its disabled state. The
shifting to the right of the SDSL adder curve is caused because of the high static
power which is dissipated due to the incomplete turn-off of the cross-coupled
pMOSFET transistors. The other static design styles are more power efcient
compared to the dynamic circuits.
The static DCVSL circuit consumes more power than the conventional static
circuit due to the difference of the charging and discharging times of its output
nodes. The asymmetry in the rise and fall times of the potential at these output nodes will prolong the period of current ow through the latch during the
transient state, thus increasing the power dissipation.
It can be obtained from the results of Table 5.2, that the dynamic circuits
exhibit an increase in speed compared to the conventional static circuit. Comparing the dynamic logic styles, Domino logic has better power-delay product
characteristics (Figure 5.12). The circuit operation in the SDSL circuit becomes
faster than the standard SDCVSL circuit, due to the reduced logic swing at the
output nodes, but in the cost of high static power dissipation. ECDL circuit is
the faster one, but consumes high switching power due to the inverters which
are needed to change the polarity of the outputs.
The design styles which use pass-transistor logic (CPL and DPL) are the best
in terms of power dissipation. CPL circuit consumes lower power than the DPL
one, because of its lower parasitic capacitance. On the contrary, DPL circuit is

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87

faster than the CPL, because the addition of pMOSFET transistors in parallel
with the nMOSFET transistors results in higher circuit drivability. Also, DPL
avoids the problems of noise margin and speed degradation at reduced supply
voltages which are caused in CPL circuits. As shown in Figure 5.12 and in
Table 5.2, the two styles exhibit similar power-delay product characteristics,
and they are the most efcient for low-power and high-speed applications.
The mean power dissipation and the propagation delay values of the eight
adder implementations are summarized in Figure 5.13. The fast adder circuits
lie to the left of the gure , and those with low power consumption lie toward
the bottom of the gure .

Power D issipation (mW)

2.5

SDSL

ECDL
1.5

DDCVSL

DRDL
0.5

CSL
DPL

SDCVSL

CPL

0
2

Delay (ns)
Figure 5.13. Power dissipation versus delay of the adder implementations

5.5

Adders

In static CMOS the dynamic power dissipation of a circuit depends primary

on the number of transitions per unit area. As a result, the average number of
logic transitions per addition can serve as the basis of comparing the efciency
of a variety of adder designs. If two adders require roughly the same amount
of time and roughly the same number of gates, the circuit which requires fewer

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DESIGNING CMOS CIRCUITS FOR LOW POWER

logic transitions is more desirable as it will require less dynamic power. This is
only a rst order approximation as the power also depends on switching speed,
gate size, fan-out, output loading e.t.c.
The following types of adders were simulated: Ripple Carry, Constant Block
Width Single-level Carry Skip, Variable Block Width Multi-level Carry skip,
Carry Lookahead, Carry Select, and Conditional Sum. Table 5.3 presents the
worst case number of gate delays, the number of gates, and the average number
of logic transitions for the six 16-bit adder types. All the gates are assumed to
have the same delay, regardless of the fan-in or fan-out.
Table 5.3. Worst Case Delay, Number of Gates, and Average Number of Logic Transitions for
a 16-bit Adder

Adder Type

Worst Case
Delay
(in
gates units)

Number of
Gates

Average Number
of logic Transitions

Ripple Carry
Constant
Block
Width Single-level
Carry Skip
Variable
Block
Width Multi-level
Carry skip
Carry Lookahead
Carry Select
Conditional Sum

36
23

144
156

90
102

17

170

108

10
14
12

200
284
368

100
161
218

5.6

Multipliers

The majority of the real life applications, such as microprocessors and digital processing implementations, require the computation of the multiplication
operation. Specically, speed, area and power efcient implementation of a
multiplier is a very challenging problem. Here, four well-known multipliers: i)
the Array Multiplier [25], ii) the Split Array Multiplier [26], iii) Wallace Tree
Multiplier [27] and iv) the Radix-4 Modied Booth Recoded Wallace Tree
Multipliers [28], are studied in terms of power consumption.
Two kinds of measurements and comparisons in the terms of different design
parameters are performed providing to the designer a plethora of alternative implementations. Particularly, we provide SPICE-like measurements with respect
to the average logic transitions as well as the power consumption. The second

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89

kind of measurements are performed following a typical high-level analysis

ow and is based on a state-of-the-art CAD framework.

5.6.1

SPICE-like Power Measurements of Multipliers

The multipliers were described using only AND, OR, and INVERT gates.
The simulation was made using a program called CazM [29], which is similar
to SPICE. Each multiplier was fed with 1.000 pseudorandom inputs. For the
sake of completeness, the carry save array multiplier and the Wallace tree is
presented in the following section, in order to briey describe the architectures
of the most common multipliers. The former is a representative paradigm of
array multipliers, while the Wallace tree is an efcient way to add multiple
partial products together.
A gate level simulation with 10.000 pseudorandom inputs, enabled the gathering of average number of gate-output transitions for each multiplier. During
each input, the number of gates that switch output states is recorded, and an
average number of gate-output transitions per multiplication are computed at
the end of the simulation. Table 5.4 presents the results.
Table 5.4.

Average Number of Gate-Output Transistions

Average Number of Gate-Output Transitions

Multiplier Type
Array
Split array
Wallace
Modied booth

8-bit
570
569
549
964

16-bit
7224
4874
3793
3993

32-bit
99906
52221
20055
19542

The average power dissipation per multiplication is shown in Table 5.5.

These results were obtained by simulating the multiplication of 1000 pseudorandom inputs with a clock period of 100 ns. The results vary signicantly.
The Wallace multiplier, which presents the lower power dissipation, is neither
the smallest nor the slowest one.

5.6.2

High-Level Power Characterization of Multipliers

The second power estimation procedure is illustrated in Figure 5.14.The rst

step is the logic synthesis of the parameterized and structural VHDL description
of the arithmetic modules. Here, a 0.6-micron process, AMS standard-cell
library has been used. For power characterization, only the dynamic power
dissipation, which forms the dominant component of the total power, is taken

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DESIGNING CMOS CIRCUITS FOR LOW POWER

Table 5.5.

Avarage Power Dissipation from CAzM

Multiplier Type

Power (mW)

Logic Transitions

Array
Split array
Wallace
Modied booth

43.5
38.0
32.0
41.3

7224
4874
3793
3993

into account [30]. Specically, the activity per node, resulting via logic-level
simulation that takes place in a second step, is combined with the capacitance
per node, to compute the power for a certain input vector, according to

(5.7)

UC  GG

U @

where
is the capacitance at node ,
is the power supply voltage , is
the frequency and is the activity factor at node . The term f E of Eq. 5.7
is actually the number of transitions from logic 1 to logic 0 per time unit for
the node , which is equal to the ratio of number of node transitions from logic
1 to logic 0, divided by the total number of input vectors:

@

@ C @ 4

(5.8)

From Eq. 5.7 and 5.8, the power is:

(5.9)

@ C @

C

@


U @

Following this procedure, the power estimation errors are in the range of
10-25% [31], compared with SPICE transistor-level simulator. However, the
accuracy of the estimates sufces for the purpose of comparing alternative
module architectures, since its relative evaluation is of importance and not the
absolute accuracy. The 8-bit wide input modules were simulated with 50.000
random vectors, the 16-bit modules with 100.000 vectors, the 32-bit modules
with 150.000 random vectors, and the 64-bit modules with 200.000 vectors. It
should be stressed here, that the energy gures, given later in the characterization
sections of the arithmetic components, correspond to the average energy per
operation. The difference of the two characterization procedures in the number
of test vectors is signicant.In this section, power measures for the synthesized
multipliers, namely the carry save array, the Booth encoded Wallace tree and

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Synthesis

Parameters
Set

Parametrical
VHDL
Description

91

Target
Technology

Logic Level
Description

Delay
Estimation

Area
Estimation

Logic Level
Simulation

Capacitance
per Node

Target
Technology

Switching
Activity per node

Power
Estimation

Figure 5.14. High level Characterization Flow

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DESIGNING CMOS CIRCUITS FOR LOW POWER

the non-Booth encoded Wallace tree, will be presented, while analysis of results
and comparisons with previous work are made.
Table 5.6 presents the power estimation of the synthesized multipliers. The
measurements of power are normalized by frequency, reecting the fact of
simulation, with different operating frequencies. In this way, a representative
power measure is given, for every kind of multiplier and for every bit width. As
it is shown in Table 5.6, the most power-efcient multiplier for small bit-widths
(less than 32 bits) is the carry save array, but with a small difference, compared
to the Wallace tree with non-Booth encoding. In the 64-bit implementations,
the Wallace tree with non-Booth encoding multiplier is the most power efcient
choice. This fact is explained by the glitches arising from the ripple of carries of
the array multiplier for large bit-widths. Finally, for all bit-widths, the Wallace
tree with Booth encoding multiplier has the worst power dissipation.

Table 5.6.

Power dissipation estimates

Power (mW)
Multiplier Type/
Multiplier Width
Carry Save Array
Wallace Tree
(Booth Encoded)
Wallace Tree
(Non Booth Encoded)

8-bit

16-bit

32-bit

64-bit

0.3084
0.7868

2.2484
3.1204

3.057023
5.384

20.96759
23.7164

0.5488

2.5992

4.2212

18.8588

For comparison purposes, Table 5.7 shows the results presented in [29], considering 16-bit implementations of array and Wallace tree multipliers. These
designs were described only by AND, OR, and INVERT gates. The implementation technology was a 2-level metal 2- m process. It can be seen that the
array multiplier consumes more energy than the Wallace tree multiplier, which
is contradictory to corresponding values shown in Table 5.6. Only in the 64-bit
case, the array multiplier consumes more energy than the Wallace tree multiplier. The reason for this is the spurious transitions that occur by the rippling
of carries for the array multiplier of the 64-bit implementation, which cannot
compensate the interconnect area/capacitance switched by the array multiplier.
For the remaining cases, the factors of the greater interconnect and cell area for
the Wallace multiplier dominate the power performance of these two kinds of
multipliers.

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Table 5.7.

93

16-bit Multiplier Average Power Dissipation [29]

Multiplier

Power (mW)

Logic transitions

43.5
32

7224
3793

Carry Save Array

Wallace Tree

The Wallace multiplier with Booth encoding dissipates the most power, while
it is not the largest. It is the fastest multiplier for bit-widths larger than 16 bits
and can be assumed that Booth encoding is a rather power-hungry operation.
Finally, Table 5.8 depicts the Power Delay product of the multipliers at
1MHz frequency. More specically, the carry save array multiplier exhibits
the worst product for all bit-widths, except the 8-bit, due to the large delay
and the substantial power consumption Although the non-Booth Wallace tree
multiplier is the largest, it shows the best Power Delay product for every
bit-width. Where speed is of great interest, especially if large bit widths are
required, and chip area is not a problem, the non-Booth encoded Wallace tree
multiplier is the best candidate for selection.

Table 5.8.

Power-Delay product of Multipliers at 1MHz

Power*Delay (mW*ns)
8-bit
16-bit
32-bit

Multiplier Type/
Multiplier Width
Carry Save Array
Wallace Tree
(Booth Encoded)
Wallace Tree
(Non Booth Encoded)

5.7

64-bit

4,13256
4,980444

53,51192
25,96173

141,9987
58,09336

2090,049
312,345

3,172064

19,8059

44,95578

251,9536

Conclusions

In this chapter, the most common kinds of adders and multipliers have been
characterized in terms of power, using either a traditional low-level design ow
paradigm, which is rather tedious and incompatible with modern design ows,
but provides the most accurate results, or a high-level design ow paradigm,
which is commonly used.

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DESIGNING CMOS CIRCUITS FOR LOW POWER

A four-bit ripple carry adder was used, as the benchmark circuit. All the circuits have been designed in a full-custom manner, and simulated using HSPICE.
A statistical approach was used in order to analyze the simulation results. It
has been shown that the circuits which use pass-transistor logic (CPL and DPL)
exhibit better power and the power-delay product characteristics compared to
other design styles.
The array multiplier is power-efcient for small bit widths. Its power consumption grows in proportion to the cube of the word size. The Wallace multiplier is less regular, but is more power efcient, while its power dissipation
grows with the square of the word size.
The speed of the synthesized optimized carry look-ahead is traded-off for
the worst energy power consumption among all the investigated adders, which
have been synthesized. As opposed to the speed optimized architecture of the
carry look-ahead adder, a non-optimized architecture is power-efcient, though
much slower. Power-efcient is the ripple carry adder, too.

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