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Assignment 1

1. CPU time is reduced when using parallelization compared to no parallelization. With two cores, CPU time is reduced by 40%. 2. Power consumption is also reduced with parallelization. With two cores, power is reduced by 43.2% compared to no parallelization. 3. Additional transistors in chips over time are used to increase performance through wider data paths, multi-core designs, and dedicated hardware modules rather than just higher clock speeds due to power and heat limitations.

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58 views3 pages

Assignment 1

1. CPU time is reduced when using parallelization compared to no parallelization. With two cores, CPU time is reduced by 40%. 2. Power consumption is also reduced with parallelization. With two cores, power is reduced by 43.2% compared to no parallelization. 3. Additional transistors in chips over time are used to increase performance through wider data paths, multi-core designs, and dedicated hardware modules rather than just higher clock speeds due to power and heat limitations.

Uploaded by

chintu_89
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment 1 1.

7 a) CPU timewithout parallezation = CI x CPI x Clock Time = CI x CPI / f1 CPU timewih parallel =
0.8
2

+0.2 2

= 0.6 x CPI/ f2

CPU timewithout parallel = CPU timewith parallel f2 = 0.6f1 b) Assuming voltage decreases linearly with frequency V2 = 0.6V1 P 1 = x C x V 1 2x f 1 P2 = x C x (0.6V1)2 x 0.6f1 x 2 (Multiplied by 2 since dual core) P2 = x C x V12 x f1 x 0.432 P2 = 0.432P1 1.8 a) Transistor Density increases by 35% every year. So every year the transistor count increases by 1.35 times the previous year. Therefore for N years it increases by 1.35N For 2005 to 2015 i.e., 10 years the transistors increase by 1.3510 =20.106 times d) As Power = C V f Increasing the frequency (clock rate) increases the Power. And we finally reached to the limit, where further more increase in heat no longer be cooled by traditional cooling ways. Due to this limitation, modern architects are working in ways other than just increasing the clock rate to increase performance using the additional transistors. As example Increasing the manipulation from 4bit to 64 bit computers. Building Multi-core chips Building dedicated hardware modules which increase the performance using the extra transistors like Floating point arithmetic units, Video and audio rendering modules.

1.10 b) PInitial = 0.9 Pmax

P60% barely alive = 0.6 x 0.2 x Pmax + 0.4 x 0.9 x Pmax P60% barely alive = 0.48 Pmax Psaved = PInitial - P60% barely alive Psaved = 0.42 Pmax % saved = 0.42/0.9 x 100 = 46.6% C) P1 max = x C x V2 x f Power consumed = 0.9 Pmax Reducing Voltage by 20% and frequency by 40% P2 max = x C x (0.8V)2 x (0.6)f = x C x V2 x f x 0.384 = 0.384 P1max Power consumed = 0.9 P2max Power saved = 0.9(P1 max P2 max) = 0.554 P1 max %saved = 0.554/0.9 x 100 = 61.5 % 1.18) a) From Amdahls law Speed up =

1 (1 )+ 1 (10.8)+
0.8 8

= 1/0.3 =3.33 b) SpeedUp =

+ 0.0058

=
8

=1
8

1 + 0.04

= 6.06 C) The communication overhead is added only when processors are doubled. That is thrice for 8 core processor 1->2->4->8 SpeedUp = 1
8

+0.0053

=7.14

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