Spartan-3A/3AN FPGA Starter Kit Board User Guide

UG334 (v1.1) June 19, 2008

Xilinx is disclosing this Document and Intellectual Property (hereinafter the Design) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED AS IS WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (High-Risk Applications). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. 2007-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PCI Express is a registered trademark of PCI-SIG. All other trademarks are the property of their respective owners.

Revision History
The following table shows the revision history for this document.
Date 05/28/07 06/19/08 Version 1.0 1.1 Initial Xilinx release. Revision

Added note that PS/2 port I/Os should always be set to LVCMOS33 with the PULLUP attribute set true when used. Updated UCF examples to match reference designs. Added recommendation for 1 MHz BPI configuration. Updated links.

Spartan-3A/3AN FPGA Starter Kit Board User Guide www.xilinx.com

UG334 (v1.1) June 19, 2008

Table of Contents
Preface: About This Guide
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 1: Introduction and Overview

Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating the Default Demonstration Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VGA Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rotary Knob/Push-Button Menu System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Select MultiBoot Configuration Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scroll or Rotate Graphic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scroll or Scale Graphic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restart AutoPilot, Speaker Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Screen Control Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Saving Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RS-232 Serial Port Control Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 17 17 17 18 18 19

Key Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Design Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Configuration Methods Galore! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Voltages for all Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Spartan-3A/3AN FPGA Starter Kit Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . 21 Choose a Spartan-3 Generation Starter Kit Board for your Needs . . . . . . . . . . . . . 22
Spartan-3A/3AN FPGA Features and Embedded Processing Functions . . . . . . . . . . 22 Other Spartan-3 Generation Development Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Spartan-3A and Spartan-3AN FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Chapter 2: Switches, Buttons, and Rotary Knob

Slide Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SUSPEND Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROG_B Push-Button Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 28 28

Rotary Push-Button Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Push-Button Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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Rotary Shaft Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Discrete LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Optional Discrete LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

AWAKE LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 INIT_B LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Chapter 3: Clock Sources

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MHz On-Board Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Clock Oscillator Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMA Clock Input or Output Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33 34 34 34 34

34 Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Clock Period Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Chapter 4: FPGA Configuration Options

Configuration Mode Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Platform Flash Configuration PROM(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROG Push-Button Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DONE Pin LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the FPGA or Platform Flash PROM via USB . . . . . . . . . . . . . . . . . . .
39 40 40 41

41 Connecting the USB Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Platform Flash Programming Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Chapter 5: Character LCD Screen

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Character LCD Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DD RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CG ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CG RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Return Cursor Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entry Mode Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Display On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 44 44 44 45 45 45 46 47 48 49 49 49 49 50

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Cursor and Display Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set CG RAM Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set DD RAM Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Busy Flag and Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Data to CG RAM or DD RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Data from CG RAM or DD RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

50 51 51 51 51 51 52 52 53 53 54 54 54 55

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Four-Bit Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transferring Eight-Bit Data over the Four-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . Initializing the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writing Data to the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disabling the Unused LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Chapter 6: VGA Display Port

Signal Timing for a 60 Hz, 640x480 VGA Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGA Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58 60 61 61

Chapter 7: RS-232 Serial Ports

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Chapter 8: PS/2 Mouse/Keyboard Port

Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding a Second PS/2 Port Using a Y-Splitter Cable . . . . . . . . . . . . . . . . . . . . . . . . . UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66 68 69 69 70 70

Chapter 9: Analog Capture Circuit

Digital Outputs from Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Programmable Pre-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 73 74 75

Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Connecting Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Chapter 10: Digital-to-Analog Converter (DAC)

SPI Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI Communication Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Specifying the DAC Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Chapter 11: Parallel NOR Flash PROM

Flash Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Shared SPI Flash and Platform Flash Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Setting the FPGA Mode Select Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Creating and Programming Configuration Images for Parallel Flash . . . . . . . . . 89 Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Chapter 12: SPI Serial Flash

SPI Flash PROM Select Jumpers (J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Shared SPI Flash and Platform Flash Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Jumper Settings to Configure FPGA from Selected SPI Flash PROM . . . . . . . . . . . . . 94

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Creating and Programming Configuration Images for SPI Serial Flash . . . . . . . 95
SPI Flash PROM Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Direct Programming Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Using Embedded USB JTAG Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Using a Separate JTAG Parallel Programming Cable (Optional) . . . . . . . . . . . . . . . . . . 97 Direct SPI Flash Programming Using iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Indirect Programming Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Indirect SPI Flash Programming Using iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Chapter 13: DDR2 SDRAM

DDR2 SDRAM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserve FPGA VREF Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 111 111 112

Special Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

www.xilinx.com Spartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008

Chapter 14: 10/100 Ethernet Physical Layer Interface

Ethernet PHY Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MicroBlaze Ethernet IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
116 117 118 118

Chapter 15: Expansion Connectors

Hirose 100-Pin FX2 Edge Connector (J17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Expansion Connector Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Supplies to the Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connector Pinout and FPGA Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FX2-Connector Compatible Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mating Receptacle Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Differential Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Trace Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-Conductor Cable Assemblies (2x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J18 Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J19 Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J20 Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digilent Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 120 121 122 122 123 125 126 126 128 128 129 129 130 130 131

Differential I/O Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Six-Pin Accessory Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Connectorless Debugging Port Landing Pads (J34) . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Chapter 16: Miniature Stereo Audio Jack

Supported Audio Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 FPGA Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Chapter 17: Voltage Supplies

Measuring Power Across Voltage Supply Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . 137 I2C Voltage Adjustment Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Possible Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Restoring Default Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

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www.xilinx.com Spartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008

Preface

About This Guide

This user guide provides basic information on the Spartan-3A/3AN Starter Kit board capabilities, functions, and design. It includes general information on how to use the various peripheral functions included on the board. For detailed reference designs, including VHDL or Verilog source code, please visit the following web link. Spartan-3A/3AN FPGA Starter Kit Board Web Page http://www.xilinx.com/s3astarter and http://www.xilinx.com/s3anstarter

There are multiple versions of the Spartan-3A/3AN FPGA Starter Kit. This document describes the three kits that include the Revision D Spartan-3A/3AN FPGA Starter Kit Board, which is an updated version of the Revision C Spartan-3A FPGA Starter Kit Board. The following table describes the different kits.
Feature Part Number Device Board Revision DDR2 Memory User Guide Web Page Spartan-3AN Starter Kit HW-SPAR3AN-SK-UNI-G XC3S700AN Revision D Spartan-3A DDR2 SDRAM Spartan-3A Starter Spartan-3A Starter Kit, Interface Development Kit Kit, Revision D Revision C HW-SPAR3ADDR2-DKUNI-G HW-SPAR3A-SK-UNI-G XC3S700A Revision C Requires board modification for improved performance UG330 www.xilinx.com/s3astarter

Supported with 133 MHz crystal oscillator in auxiliary socket

UG334 (this document) www.xilinx.com/s3anstarter www.xilinx.com/s3addr2

Almost all functionality is identical between the Revision C and Revision D boards, although the silkscreen changes make the two boards look different. The pictures used in this document are from the Revision D board. If you are using the original Revision C version of the board, refer to UG330 for pictures and documentation. The following figure highlights where to find the board revision code on a Revision C board.

Spartan-3A/3AN FPGA Starter Kit Board User Guide www.xilinx.com UG334 (v1.1) June 19, 2008

Preface: About This Guide

Board Revision Code REV C

UG334_01_052707

Acknowledgments
Xilinx wishes to thank the following companies for their support of the Spartan-3A/3AN Starter Kit board: STMicroelectronics for the 32 Mbit parallel NOR Flash and 16 Mbit SPI serial Flash memories Atmel for the 16 Mbit SPI serial DataFlash memory Linear Technology for the SPI-compatible A/D and D/A converters and the programmable pre-amplifier SMSC for the 10/100 Ethernet PHY National Semiconductor for the four-rail voltage regulators that power the FPGA and and all peripheral components Xilinx, Inc. Configuration Solutions for the XCF04S Platform Flash PROM and support for the embedded USB programmer

Guide Contents
This manual contains the following chapters: Chapter 1, Introduction and Overview, provides an overview of the key features of the Spartan-3A/3AN Starter Kit board. Chapter 2, Switches, Buttons, and Rotary Knob, defines the switches, buttons, and knobs present on the Spartan-3A/3AN Starter Kit board. Chapter 3, Clock Sources, describes the various clock sources available on the Spartan-3A/3AN Starter Kit board. Chapter 4, FPGA Configuration Options, describes the configuration options for the FPGA on the Spartan-3A/3AN Starter Kit board. Chapter 5, Character LCD Screen, describes the functionality of the character LCD screen. Chapter 6, VGA Display Port, describes the functionality of the VGA port. Chapter 7, RS-232 Serial Ports, describes the functionality of the RS-232 serial ports. Chapter 8, PS/2 Mouse/Keyboard Port, describes the functionality of the PS/2 mouse and keyboard port. Chapter 10, Digital-to-Analog Converter (DAC), describes the functionality of the D/A converter.

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Additional Resources

Chapter 9, Analog Capture Circuit, describes the functionality of the A/D converter with a programmable gain pre-amplifier. Chapter 11, Parallel NOR Flash PROM, describes the functionality of the STMicroelectronics parallel NOR PROM. Chapter 12, SPI Serial Flash, describes the functionality of the SPI Serial Flash memory interface. Chapter 13, DDR2 SDRAM, describes the functionality of the DDR2 SDRAM memory interface. Chapter 14, 10/100 Ethernet Physical Layer Interface, describes the functionality of the 10/100Base-T Ethernet physical layer interface. Chapter 15, Expansion Connectors, describes the various connectors available on the Spartan-3A/3AN Starter Kit board. Chapter 16, Miniature Stereo Audio Jack, describes the audio interface. Chapter 17, Voltage Supplies, describes the boards power distribution system.

Additional Resources
To find additional documentation, see the Xilinx website at: http://www.xilinx.com/support/documentation/index.htm To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support.

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Preface: About This Guide

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Chapter 1

Introduction and Overview

Thank you for purchasing the Xilinx Spartan-3A/3AN FPGA Starter Kit. The board is invaluable to develop a Spartan-3A or Spartan-3AN FPGA application.

Getting Started
The Spartan-3A/3AN Starter Kit board is ready for use, right out of the box. The design stored in external Flash exercises the various I/O devices, such as the VGA display and serial ports. In addition it demonstrates new FPGA features, such as selectable MultiBoot and the power-saving Suspend mode. To start using the board, follow the simple steps outlined in Figure 1-1.

1 CHECK JUMPER SETTINGS! 5 Connect AC wall adapter. 6 Turn on power switch.

2 Optional: Connect VGA display. 3 Optional: Connect headphones

PS/2 RS-232 or amplified speakers

10 4
Set SUSPEND switch to RUN position.

8 7
See messages and instructions on LCD character display. Control operation using rotary / push-button switch.
UG334_c1_01_052407

Figure 1-1: 1. 2. 3. 4. 5.

Powering Up the Starter Kit Board

Double-check the position of the board jumpers, as shown in Figure 1-2, page 14. These settings are required for the demonstration design to configure correctly. Optionally connect a VGA display device. The display device can be a CRT, a flatpanel, or even a projector. Optionally connect headphones or amplified speakers to the audio jack. Set the SUSPEND switch to the RUN position. Connect the included AC adapter to wall power and also to the board. The AC adapter also includes attachments to support worldwide locals.

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Chapter 1: Introduction and Overview

6. 7.

Turn on the power switch. The character LCD and VGA display, if connected, display various informational messages and instructions. If an audio device is connected, the board offers words of welcome in a variety of languages. Use the rotary/push-button switch to control various board functions. Optionally connect a PS/2-style keyboard to support one of the included demonstrating designs.

8. 9.

10. Optionally connect a PC directly to the board using a standard 9-pin serial cable.
SPI Flash Select Jumpers (both jumpers installed, vertically) Platform Flash Jumper (jumper removed) DONE
CE PROM

J1

GND J46 Power Supply Jumpers (all jumpers installed)

J42 J41

J13 J12

J40 J11

J10

J9

M0 M1 M2 J26 FPGA Mode Select Jumpers (bottom two jumpers installed) (SPI Mode)

UG334_c1_02_052707

Figure 1-2:

Default Jumper Settings for Starter Kit Board

For more information on the demonstration design, visit the Design Examples web page: Spartan-3A/3AN FPGA Starter Kit Demo Design Overview www.xilinx.com/products/boards/s3astarter/reference_designs.htm#demo Restoring the Out of the Box Flash Programming www.xilinx.com/products/boards/s3astarter/reference_designs.htm#out

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Operating the Default Demonstration Design

Operating the Default Demonstration Design

The demonstration design programmed onto the Spartan-3A/3AN Starter Kit board provides various output information, depending on what I/O or display devices are connected. The VGA and audio ports provide the richest experience.

VGA Display
If a VGA display is connected to the board, then the Starter Kit board displays graphics similar to that shown in Figure 1-3. Until one of the four push buttons around the rotary knob (Figure 2-5, page 27) is pressed, the display automatically rotates a graphic image and zooms in and out around the image. This is called AutoPilot mode. A brief text overview describing the board appears along the left edge. Blue text at the bottom of the screen presents the menu system.

Text Description

Rotating and Zooming Graphics

Rotary/Push-Button Menu System

Figure 1-3:

UG330_c1_03_032207

Rotating/Zooming Graphics, Menu System Displayed on VGA Screen

Rotary Knob/Push-Button Menu System

The Spartan-3A/3AN Starter Kit board demonstration design uses the rotary knob and surrounding push-button switches, shown in Figure 2-5, page 27, to implement a menu system. The menu display appears in blue text at the bottom of the VGA output. The menu functions are highlighted in Table 1-1 and Figure 1-4.

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Chapter 1: Introduction and Overview

Table 1-1:

Function of Each Menu Control

Rotate Knob Depends on current mode, as shown in Figure 1-4. Press Push Button Depends on current mode, as shown in Figure 1-4.

Press Knob Move to next menu selection, next mode.

Start Demonstration Design

Select MultiBoot Buttons: Knob Spin: Knob Push: Power-up board Press PROG_B button
MultiBoot MultiBoot

Select FPGA Configuration

MultiBoot

Load Configuration 1. Select Configuration. More Options ...

MultiBoot

Config. 1 Config. 2 Config. 3 Config. 4

Scroll/Rotate Graphic Buttons: Knob Spin: Knob Push:

Press Knob
Rotate

Press Knob

Scroll Image. Rotate Image. More Options ...

Scroll/Scale Graphic Buttons: Knob Spin: Knob Push:

Press Knob
Scale

Scroll Image. Scale Image. More Options ...

AutoPilot/Volume Buttons: Knob Spin: Knob Push:

Figure 1-4:

Press Knob
AutoPilot AutoPilot Volume

Restart AutoPilot. Adjust Volume. More Options ...

AutoPilot AutoPilot

UG334_c1_04_052707

Rotary Knob/Push-Button Menu System

Select MultiBoot Configuration Image

Spartan-3A/3AN FPGAs support a selectable MultiBoot configuration interface. If the FPGA configures in one of its Master configuration modes, then the FPGA always loads the configuration image stored at address 0 in Flash at power-up, or whenever the PROG_B button is pressed. Spin the rotary knob to select a new FPGA configuration image. The blue text at the bottom of the display updates with each click of the rotary knob. For example, the application displays Buttons: Load Configuration x where x corresponds to the bitstream image listed in Table 1-2. Table 1-2 describes the bitstreams preloaded on the board. After selecting the desired image, press one of the four push-button switches that surround the rotary knob. This action causes the FPGA to load the selected image from external Flash memory. To change to the Scroll or Rotate Graphic mode, press the rotary knob.

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Operating the Default Demonstration Design

Table 1-2:

FPGA Configuration Bitstreams Preprogrammed on the Starter Kit Board

FPGA Configuration Bitstream 0 (default) 1

FPGA Application/Reference Design Example Starter Kit board demonstration design. Loaded at power-up. www.xilinx.com/products/boards/s3astarter/reference_designs.htm#demo Device DNA Reader: Reads the FPGAs unique Device ID value and displays it on the character LCD screen. www.xilinx.com/products/boards/s3astarter/reference_designs.htm#dna_reader Fractal Generator: Computes fractal images in real time and displays on the VGA port. A usercontributed design by Matthias Alles. Rotate knob to zoom fractal image; press surrounding push buttons to scroll the image. www-user.rhrk.uni-kl.de/~alles/fpga/files.htm ASCII Terminal: Implements a text terminal using an attached VGA display and PS/2 keyboard and will communicate with HyperTerminal on a PC via an RS-232 serial connection. Source included in www.xilinx.com/products/boards/s3astarter/reference_designs.htm#out. STMicro M29DW323DT Parallel Flash Programmer: Communicates to a PC using HyperTerminal via an RS-232 serial connection. Programs, erases, and reads the STMicro M29DW323DT parallel Flash PROM on the Starter Kit board. www.xilinx.com/products/boards/s3astarter/reference_designs.htm#parallel_flash_programmer Internal Flash Paint Application: Use a mouse to create drawings and read or write them to In-System Flash. Loaded from internal SPI Flash in Spartan-3AN FPGA Starter Kit Board. Requires setting Mode pins as described in Table 4-1, page 39 for Internal Master SPI mode. For Spartan-3AN Starter Kit Board only. www.xilinx.com/products/boards/s3astarter/reference_designs.htm#paint.

Spartan-3AN FPGA

Scroll or Rotate Graphic

In this mode, rotate the knob to rotate the graphic image clockwise or counterclockwise. Use the four push-button switches to scroll the graphic image up, down, left, or right. Press the rotary knob to change to the Scroll or Scale Graphic mode.

Scroll or Scale Graphic

In this mode, rotate the knob to scale the size of the graphic image, zooming in and out. Use the four push-button switches to scroll the resulting graphic image up, down, left, or right. Press the rotary knob to change to the Restart AutoPilot, Speaker Volume Control mode.

Restart AutoPilot, Speaker Volume Control

In this mode, rotate the knob to control the speaker output volume. Press any of the four push-button switches to restart the AutoPilot function. Press the rotary knob to change to the Select MultiBoot Configuration Image mode.

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Chapter 1: Introduction and Overview

LCD Screen Control Option

While the demonstration design operates best with an attached VGA display, the on-board LCD screen tracks similar functionality, as shown in Figure 1-5. If no VGA display is attached, then the Scroll or Rotate Graphic, Scroll or Scale Graphic, and Restart AutoPilot, Speaker Volume Control modes offer little to no functionality, the exception being the volume control assuming that a speaker is attached to the audio jack.

Start Demonstration Design

Power-up board Press PROG_B button Welcome to XLNX S3A Starter Kit Wait 1 second Select MultiBoot
MultiBoot MultiBoot MultiBoot

Select FPGA Configuration Config. 1 Config. 2 Config. 3 Config. 4

Btns: Load Cfg 1 Spin: Select Cfg

MultiBoot

Scroll/Rotate Graphic Press Knob 3x For Boot Menu

Press Knob
Rotate

Press Knob

Scroll/Scale Graphic Press Knob 2x For Boot Menu

Press Knob
Scale

AutoPilot/Volume Press Knob 1x For Boot Menu

Press Knob
AutoPilot AutoPilot AutoPilot Volume

AutoPilot
UG334_c1_05_052707

Figure 1-5:

LCD Screen Output using Menu System

Power-Saving Suspend Mode

All of the preloaded FPGA configuration bitstreams have the power-saving Suspend mode enabled. Suspend mode reduces FPGA power consumption while preserving the present state of the FPGA application and the FPGAs configuration data. Set the SUSPEND switch to RUN or SUSPEND as described in SUSPEND Switch, page 26.

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Key Components and Features

Using one or two external multimeters, measure the corresponding difference in current consumption, as described in Measuring Power Across Voltage Supply Jumpers, page 137. Caution! Do not set the SUSPEND switch to SUSPEND while programming the parallel NOR
Flash PROM using configuration bitstream #4, as described in Table 1-2.

RS-232 Serial Port Control Option

Optionally, control the demonstration design using a serial port connection to a PC or workstation. On a PC, use the HyperTerminal program to communicate to the FPGA application, as shown in Figure 1-6. Using a standard, straight-through 9-pin serial cable, connect the PCs 9-pin RS-232 port to the boards DCE connector (see Figure 7-1, page 63).

UG334_c1_06_052707

Figure 1-6:

Use HyperTerminal and a Standard Serial Cable to Connect to Board

When the demonstration design begins operating, it transmits a message using the serial port. Press a number key on the PC to load the associated MultiBoot bitstream listed in Table 1-2.

Key Components and Features

The key features of the Spartan-3A FPGA Starter Kit board or the Spartan-3AN FPGA Starter Kit board are: Spartan-3A FPGA Starter Kit Board: Xilinx 700K-gate XC3S700A Spartan-3A FPGA in the Pb-free 484-ball BGA package (FGG484) Spartan-3AN FPGA Starter Kit Board: Xilinx 700K-gate XC3S700AN Spartan-3AN nonvolatile FPGA in the Pb-free 484-ball BGA package (FGG484)

Internal 8 Mbit In-System Flash memory Store FPGA configuration bitstream or nonvolatile data

4 Mbit Xilinx Platform Flash configuration PROM 64 MByte (512 Mbit) of DDR2 SDRAM, 32Mx16 data interface 4 MByte (32 Mbit) of parallel NOR Flash

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Chapter 1: Introduction and Overview

FPGA configuration storage MicroBlaze code storage/shadowing x8 or x16 data interface after configuration STMicroelectronics and Atmel DataFlash serial architectures FPGA configuration storage Supports single configuration bitstream or multiple MultiBoot configuration bitstreams

Two 16 Mbit SPI serial Flash

Nonvolatile data storage MicroBlaze code shadowing

Two-line, 16-character LCD screen PS/2 port

Supports PS/2-compatible mouse or keyboard Supports both mouse and keyboard using a Y-splitter cable (not included)

VGA display port, 12-bit color 10/100 Ethernet PHY (requires Ethernet MAC in FPGA) Two nine-pin RS-232 ports (DTE- and DCE-style) On-board USB-based programming solution

FPGA download/debug SPI serial Flash in-system direct programming

50 MHz clock oscillator 8-pin DIP socket for second oscillator SMA connector for clock inputs or outputs 100-pin Hirose FX2 expansion connector with up to 43 FPGA user I/Os

Compatible with Digilent FX2 add-on cards Receiver: Six data channels or five data channels plus clock Transmitter: Six data channels or five data channels plus clock Supports multiple differential I/O standards, including LVDS, RSDS, mini-LVDS Also supports up to 24 single-ended I/O Uses widely available 34-conductor cables

High-speed differential I/O connectors

Two six-pin expansion connectors for Digilent Peripheral Modules Four-output, SPI-based Digital-to-Analog Converter (DAC) Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain pre-amplifier Stereo audio jack using digital I/O pins ChipScope SoftTouch debugging port Rotary-encoder with push-button shaft Eight discrete LEDs Four slide switches Four push-button switches

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Design Trade-Offs

Design Trade-Offs
A few system-level design trade-offs were required in order to provide the Spartan3A/3AN Starter Kit board with the most functionality.

Configuration Methods Galore!

A typical FPGA application uses a single, nonvolatile memory to store configuration images. A typical Spartan-3AN nonvolatile FPGA application would not require any external memory. To demonstrate new Spartan-3A and Spartan-3AN FPGA capabilities, the starter kit board has four different configuration memory sources that all must function well together. The extra configuration functions make the starter kit board more complex than typical FPGA applications. The starter kit board also includes an on-board USB-based JTAG programming interface. The on-chip circuitry simplifies the device programming experience. In typical applications, the JTAG programming hardware resides off-board or in a separate programming module, such as the Xilinx Platform USB cable.

Voltages for all Applications

The Spartan-3A/3AN FPGA typically operates with two supply rails, 1.2V and 3.3V. The Spartan-3A/3AN Starter Kit board showcases a quadruple-output regulator developed by National Semiconductor specifically to power Spartan-3 generation FPGAs. This regulator is sufficient for most standalone FPGA applications.

Spartan-3A/3AN FPGA Starter Kit Design Examples

Visit the Spartan-3A/3AN FPGA Starter Kit Design Examples web page to download and use the latest applications that specifically target the starter kit board: Spartan-3A/3AN Starter Kit Design Examples Web Page www.xilinx.com/products/boards/s3astarter/reference_designs.htm

The list of designs is ever growing and the applications are often updated to the latest software releases. The following list provides a sample of design examples: Spartan-3A/3AN Starter Kit Demo Design Overview www.xilinx.com/products/boards/s3astarter/reference_designs.htm#demo This describes the out-of-the box demo design shipped with the board. Includes how to set up and operate the demonstration, evaluate MultiBoot and Suspend, and provides demo technical details. Restoring the Out of the Box Flash Programming www.xilinx.com/products/boards/s3astarter/reference_designs.htm#out Provides a short overview of what the starter kit board does out of the box and includes instructions on how to restore the board to the original out of the box state. The ZIP file includes the golden MCS files that are pre-programmed into Flash memory before the board is shipped. The PDF file contains instructions for restoring the board to its original settings using these MCS files in case any of the configuration memories were overwritten during normal use.

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Chapter 1: Introduction and Overview

Spartan-3A/3AN Starter Kit Board Verification Design www.xilinx.com/products/boards/s3astarter/reference_designs.htm#test This example includes the board test specification and the board test design. This design was used during initial board verification and some functions are used during production test. It is provided to test out a board if something is not working as expected. The design files may also be of general interest. The ZIP file has the design source, a script to run them, and the resulting compiled files.

Programmer for the STMicroelectronics M29DW323DT Parallel NOR Flash www.xilinx.com/products/boards/s3astarter/reference_designs.htm #parallel_flash_programmer This design transforms the Spartan-3A or Spartan-3AN FPGA into a programmer for the 32Mbit STMicroelectronics M29DW323DT parallel NOR Flash memory. This memory optionally holds configuration images for the FPGA and provides general non-volatile storage for other applications implemented within the FPGA. Using a simple terminal program, this application provides the following capabilities:

Erase the memory in part or in full Read the memory to verify contents Download complete configuration images using standard MCS files Manually program individual bytes Display the device identifier and 64-bit unique device numbers

Spartan-3A/3AN Device DNA Reader www.xilinx.com/products/boards/s3astarter/reference_designs.htm#dna_reader This design uses a PicoBlaze processor to read the unique Device DNA identifier embedded in each Spartan-3A/3AN FPGA and then display it on the LCD screen.

Choose a Spartan-3 Generation Starter Kit Board for your Needs

The Spartan-3A and Spartan-3AN Starter Kit boards are best for prototyping Spartan-3A/3AN FPGA applications. Depending on specific requirements, however, Xilinx and third-party companies offer development boards that better suit other needs.

Spartan-3A/3AN FPGA Features and Embedded Processing Functions

The Spartan-3A/3AN Starter Kit board highlights the unique features of the Spartan-3A and Spartan-3AN FPGA families and provides a convenient development board for embedded processing applications. The board highlights these features: Spartan-3AN specific features

Nonvolatile configuration from internal SPI Flash Parallel NOR Flash configuration SPI serial Flash configuration using either the STMicroelectronics or Atmel DataFlash architectures MultiBoot FPGA configuration from both Parallel NOR and SPI serial Flash PROMs MicroBlaze 32-bit embedded RISC processor

Spartan-3A/3AN specific features

Embedded development

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Spartan-3A and Spartan-3AN FPGAs

PicoBlaze eight-bit embedded controller

Power management using the Suspend mode feature DDR2 SDRAM memory interfaces

Other Spartan-3 Generation Development Boards

The Spartan-3A/3AN Starter Kit board demonstrates the full capabilities of the Spartan-3A and Spartan-3AN FPGA families and the Xilinx ISE development software. For a development board specific to the Spartan-3E FPGA family, consider the Spartan-3E Starter Kit board. There are multiple ordering codes, depending on the included power supply. Spartan-3E Starter Kit Board (HS-SPAR3E-SK_xx) www.xilinx.com/s3estarter

For MicroBlaze processor development, consider the Spartan-3A DSP Embedded Development board. Spartan-3A DSP S3D1800A MicroBlaze Processor Edition (DO-SD1800A-EDK-DKUNI-G) www.xilinx.com/products/devkits/DO-SD1800A-EDK-DK-UNI-G.htm For PCI Express applications, consider the Spartan-3 PCI Express Starter Kit. Spartan-3 PCI Express Starter Kit (HW-S3PCIE-DK) www.xilinx.com/s3pcie

For simple Spartan-3 FPGA applications, consider the fairly basic Spartan-3 Starter Kit board. Spartan-3 Starter Kit (DO-SPAR3-DK) www.xilinx.com/s3starter

Also consider the capable boards offered by Xilinx partners: Spartan-3 Generation Board Interactive Search www.xilinx.com/products/devboards/index.htm

Spartan-3A and Spartan-3AN FPGAs

The Spartan-3AN FPGA platform offers nonvolatile pin-compatible versions of the Spartan-3A FPGA platform. The Spartan-3AN FPGAs support the same external programming sources as Spartan-3A FPGAs, but add an additional internal SPI Flash programming mode. The internal SPI Flash can also be used for user data. The Spartan-3A/3AN Starter Kit Board supports both external and Spartan-3AN internal configuration options. Spartan-3AN FPGAs require VCCAUX to be 3.3V while Spartan-3A FPGAs allow VCCAUX to be either 2.5V or 3.3V. The Spartan-3A/3AN Starter Kit Board uses a default VCCAUX of 3.3V. Spartan-3A and Spartan-3AN FPGAs have different documentation and availability. Verify the latest version of the appropriate documentation on xilinx.com.

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Chapter 1: Introduction and Overview

Spartan-3A FPGAs

Web page www.xilinx.com/spartan3a Data sheet www.xilinx.com/support/documentation/data_sheets/ds529.pdf Errata www.xilinx.com/support/documentation/spartan-3a_errata.htm Additional documentation www.xilinx.com/support/documentation/spartan-3a.htm Web page www.xilinx.com/spartan3an Data sheet www.xilinx.com/support/documentation/data_sheets/ds557.pdf Errata www.xilinx.com/support/documentation/spartan-3an_errata.htm Additional documentation www.xilinx.com/support/documentation/spartan-3an.htm

Spartan-3AN FPGAs

Related Resources
Refer to the following links for additional information: Spartan-3A/3AN Starter Kit www.xilinx.com/s3astarter

Spartan-3A/3AN Rev D Starter Kit user guide (this document) Spartan-3A Rev C Starter Kit user guide www.xilinx.com/support/documentation/boards_and_kits/ug330.pdf Example User Constraints File (UCF) www.xilinx.com/products/boards/s3astarter/files/s3astarter.ucf Board schematics (annotated) www.xilinx.com/products/boards/s3astarter/s3astarter_schematic.pdf Bill of materials (BOM) list www.xilinx.com/products/boards/s3astarter/s3astarter_bom.xls Link to design examples www.xilinx.com/products/boards/s3astarter/reference_designs.htm

Xilinx MicroBlaze Soft Processor

www.xilinx.com/microblaze

Xilinx PicoBlaze Soft Processor

www.xilinx.com/picoblaze

Xilinx Embedded Development Kit www.xilinx.com/ise/embedded_design_prod/platform_studio.htm Xilinx Software Tutorials www.xilinx.com/support/techsup/tutorials/ Xilinx Technical Support www.xilinx.com/support

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Chapter 2

Switches, Buttons, and Rotary Knob

Slide Switches
Locations and Labels
The Spartan-3A/3AN FPGA Starter Kit board has four slide switches, as shown in Figure 2-1. The slide switches are located in the lower right corner of the board and are labeled SW3 through SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.

HIGH, 1

LOW, 0 SW3 (T9) SW2 (U8) SW1 (U10) SW0 (V8)

UG330_c2_01_021507

Figure 2-1:

Four Slide Switches

Operation
When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce. There is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board.

UCF Location Constraints

Figure 2-2 provides the UCF constraints for the four slide switches, including the I/O pin assignment and the I/O standard used. The PULLUP resistor is not required, but it defines the input value when the switch is in the middle of a transition.

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Chapter 2: Switches, Buttons, and Rotary Knob

NET NET NET NET

"SW<0>" "SW<1>" "SW<2>" "SW<3>"

LOC LOC LOC LOC

= = = =

"V8" | "U10"| "U8" | "T9" |

IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD

= = = =

LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33

; ; ; ;

Figure 2-2: UCF Constraints for Slide Switches

SUSPEND Switch
The SUSPEND slide switch, shown in Figure 2-3, connects directly to the FPGAs SUSPEND input pin. If Suspend mode is enabled in the FPGA application, then the FPGA enters Suspend mode whenever the switch is set to SUSPEND. If the switch is then changed back to RUN, then the FPGA resumes operation from the state before it entered Suspend mode. Likewise, if Suspend mode is enabled, then the AWAKE pin is reserved to indicate when the FPGA is in Suspend mode. See AWAKE LED, page 32.

RUN

SUSPEND
UG334_c2_03_052407

Figure 2-3:

Suspend Switch

To enable Suspend mode, add the configuration string shown in Figure 2-4 to the user constraints file (UCF). If Suspend mode is not enabled in the application, then the SUSPEND switch has no affect on the design and the AWAKE pin is available as a generalpurpose I/O.
CONFIG ENABLE_SUSPEND = FILTERED ;

Figure 2-4: UCF Constraints to Enable Suspend Mode For more information on Suspend mode, see the following application note: XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs www.xilinx.com/support/documentation/application_notes/xapp480.pdf

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Push-Button Switches

Push-Button Switches
Locations and Labels
The Spartan-3A/3AN Starter Kit board has four momentary-contact push-button switches, shown in Figure 2-5. The push buttons are located in the lower right corner of the board and are labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The FPGA pins that connect to the push buttons appear in parentheses in Figure 2-5, and the associated UCF is listed in Figure 2-7.
Rotary Push Button Switch BTN_NORTH (T14) ROT_A: (T13) ROT_B: (R14) ROT_CENTER: (R13) Requires an internal pull-up Requires an internal pull-up Requires an internal pull-down

BTN_WEST (U15)

BTN_EAST (T16)

BTN_SOUTH (T15)

UG334_c2_05_052407

Notes:
1. All BTN_* push-button inputs require an internal pull-down resistor.

Figure 2-5: Four Push-Button Switches Surround the Rotary Push-Button Switch

Operation
Pressing a push button connects the associated FPGA pin to 3.3V, as shown in Figure 2-6. Use an internal pull-down resistor within the FPGA pin to generate a logic Low when the button is not pressed. Figure 2-7 shows how to specify a pull-down resistor within the UCF. There is no active debouncing circuitry on the push button.
3.3V Push Button FPGA I/O Pin

BTN_* Signal

UG230_c2_03_021206

Figure 2-6: Push-Button Switches Require an Internal Pull-Down Resistor in the FPGA Input Pin

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PROG_B Push-Button Switch

The PROG_B push-button switch, shown in Figure 2-14, page 31, is part of the FPGAs configuration circuitry. See PROG Push-Button Switch, page 40.

UCF Location Constraints

Figure 2-7 provides the UCF constraints for the four push-button switches, including the I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each input.
NET NET NET NET "BTN_EAST" "BTN_NORTH" "BTN_SOUTH" "BTN_WEST" LOC LOC LOC LOC = = = = "T16" "T14" "T15" "U15" | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 | | | | PULLDOWN PULLDOWN PULLDOWN PULLDOWN ; ; ; ;

Figure 2-7: UCF Constraints for Push-Button Switches

Rotary Push-Button Switch

Locations and Labels
The rotary push-button switch is located in the center of the four individual push-button switches, as shown in Figure 2-5, page 27. The switch produces three outputs. The two shaft encoder outputs are ROT_A and ROT_B. The center push-button switch is ROT_CENTER.

Operation
The rotary push-button switch integrates two different functions. The switch shaft rotates and outputs values whenever the shaft turns. The shaft can also be pressed, acting as a push-button switch.

Push-Button Switch
Pressing the knob on the rotary/push-button switch connects the associated FPGA pin to 3.3V, as shown in Figure 2-8. Use an internal pull-down resistor within the FPGA pin to generate a logic Low. Figure 2-11 shows how to specify a pull-down resistor within the UCF. There is no active debouncing circuitry on the push button.

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Rotary Push-Button Switch

Rotary / Push Button

3.3V

FPGA I/O Pin

ROT_CENTER Signal

UG230_c2_05_021206

Figure 2-8: Push-Button Switches Require an Internal Pull-up Resistor in the FPGA Input Pin

Rotary Shaft Encoder

In principal, the rotary shaft encoder behaves much like a cam connected to the central shaft. Rotating the shaft then operates two push-button switches, as shown in Figure 2-9. Depending on which way the shaft is rotated, one of the switches opens before the other. Likewise, as the rotation continues, one switch closes before the other. However, when the shaft is stationary, also called the detent position, both switches are closed.

A pull-up resistor in each input pin generates a 1 for an open switch. See the UCF file for details on specifying the pull-up resistor.

FPGA

Vcco

A=0

Vcco
Rotary Shaft Encoder

B=1 GND
Figure 2-9:

UG230_c2_06_030606

Basic Example of Rotary Shaft Encoder Circuitry

Closing a switch connects it to ground, generating a logic Low. When the switch is open, a pull-up resistor within the FPGA pin pulls the signal to a logic High. The UCF constraints in Figure 2-11 describe how to define the pull-up resistor. The FPGA circuitry to decode the A and B inputs is simple but must consider the mechanical switching noise on the inputs, also called chatter. As shown in Figure 2-10, the chatter can falsely indicate extra rotation events or even indicate rotations in the opposite direction!

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Rising edge on A when B is Low indicates RIGHT (clockwise) rotation

Rotating RIGHT

Switch opening chatter on A injects false clicks to the RIGHT

A B
Detent Detent
Switch closing chatter on B injects false clicks to the LEFT (B rising edge when A is Low)

UG230_c2_07_030606

Figure 2-10: Outputs from Rotary Shaft Encoder Might Include Mechanical Chatter

UCF Location Constraints

Figure 2-11 provides the UCF constraints for the rotary encoder/push-button switch, including the I/O pin assignment and the I/O standard used, and defines a pull-up or pull-down resistor for each FPGA input.
NET "ROT_A" LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP ; NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP ; NET "ROT_CENTER" LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN ;

Figure 2-11:

UCF Constraints for Rotary Push-Button Switch

Discrete LEDs
Locations and Labels
The Spartan-3A/3AN Starter Kit board has eight individual surface-mount LEDs located immediately above the slide switches as shown in Figure 2-12. The LEDs are labeled LED7 through LED0. LED7 is the left-most LED, LED0 the right-most LED.
LED7: (W21) LED6: (Y22) LED3: (U19) LED2: (U20) LED0: (R20)
UG334_c2_12_052407

LED5: (V20)

LED4: (V19)

Figure 2-12: Eight Discrete LEDs

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LED1: (T19)

Optional Discrete LEDs

Operation
Each LED has one side connected to ground and the other side connected to a pin on the device via a 390 current limiting resistor. To light an individual LED, drive the associated FPGA control signal High. If the FPGA is not yet configured, the LEDs may be dimly lit because pull-up resistors are enabled during configuration. The FPGAs PUDC_B pin is connected to GND on the board.

UCF Location Constraints

Figure 2-13 provides the UCF constraints for the four push-button switches, including the I/O pin assignment, the I/O standard used, the output slew rate, and the output drive current.
NET NET NET NET NET NET NET NET "LED<7>" "LED<6>" "LED<5>" "LED<4>" "LED<3>" "LED<2>" "LED<1>" "LED<0>" LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = "W21" "Y22" "V20" "V19" "U19" "U20" "T19" "R20" | | | | | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = = = = =

LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33

| | | | | | | |

SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW

= = = = = = = =

SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW

| | | | | | | |

DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE

= = = = = = = =

8 8 8 8 8 8 8 8

; ; ; ; ; ; ;

Figure 2-13:

UCF Constraints for Eight Discrete LEDs

Optional Discrete LEDs

The Spartan-3A/3AN Starter Kit board provides two optional LEDs, shown in Figure 2-14. Depending on which features are used by an application, these LED connections may be also used as user-I/O pins.

FPGA PROG_B Pin (Press to reset/reprogram FPGA)

FPGA_INIT_B (W21)

FPGA_AWAKE (AB15)

RED

YELLOW

FPGA DONE Pin (Lit when FPGA is configured) GREEN UG334_c2_14_052407

Figure 2-14: AWAKE and INIT_B LEDs

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AWAKE LED
The yellow-colored AWAKE LED connects to the FPGAs AWAKE pin and is used if the FPGA Suspend mode is enabled in the bitstream. If the Suspend mode is not used, then the FPGAs AWAKE pin is available as a full user-I/O pin. If the FPGA is not yet configured, the FPGAs AWAKE pin is dimly lit because pull-up resistors are enabled during configuration. The FPGAs PUDC_B pin is connected to GND on the board. To light the AWAKE LED in an application, drive the AWAKE pin High.

INIT_B LED
The red-colored INIT_B LED serves multiple purposes: At power-up or when the PROG_B button is pressed, the LED flashes momentarily while the FPGA clears its configuration memory. If configuration fails for any reason, then the FPGAs DONE LED will be unlit and the INIT_B LED will light. This indicates that the FPGA could not successfully configure. After the FPGA successfully completes, the INIT_B pin is available as a generalpurpose user-I/O pin. If no signal drives INIT_B, then it is defined as an input pin with a pull-down resistor. It might appear that the LED dimly glows. Drive the INIT_B pin High to turn off the LED or Low to light the LED. If using the Readback CRC feature, the INIT_B pin is reserved and signals a CRC error after configuration. If such an error occurs, the FPGA drives INIT_B Low, lighting the LED.

If using the INIT_B pin as a user-I/O pin after configuration, drive the pin Low to light the LED and High to shut it off. Jumper J46, shown in Table 4-2, page 40, must be in either the Disabled or Enabled during Configuration setting. The Always Enabled setting for Jumper J46 allows the FPGA to read additional data from the Platform Flash PROM after configuration, as described in Xilinx application note XAPP694. Caution! The FPGAs INIT_B pin also connects to the Platform Flash PROMs OE/RESET pin. If the jumper controlling the Platform Flash PROM, jumper J46 in Table 4-2, page 40, is set to Always Enabled, then the INIT_B signal controls the PROMs active-Low output-enable (OE) input or active-High RESET input. XAPP694: Reading User Data from Configuration PROMs www.xilinx.com/support/documentation/application_notes/xapp694.pdf

UCF Location Constraints

Figure 2-15 provides the UCF constraints for the optional LEDs, including the I/O pin assignment, the I/O standard used, the output slew rate, and the output drive current. The ENABLE_SUSPEND constraint must be set to NO in order to use FPGA_AWAKE LED.
NET "FPGA_INIT_B" LOC = "V13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # The AWAKE LED is only available if Suspend mode is disabled CONFIG ENABLE_SUSPEND = NO ; NET "FPGA_AWAKE" LOC = "AB15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

Figure 2-15: UCF Constraints for Optional Discrete LEDs

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Chapter 3

Clock Sources
Overview
The Spartan-3A/3AN FPGA Starter Kit board supports three primary clock input sources, as shown in Figure 3-1. The board includes an on-board 50 MHz clock oscillator. Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA can generate clock signals or other high-speed signals on the SMA-style connector. A 133 MHz clock oscillator is installed in the CLK_AUX socket. Optionally substitute a separate eight-pin DIP-style clock oscillator in the provided socket.
CLK_50MHZ (E12)

CLK_AUX (V12)

CLK_SMA (U12)

UG334_c3_01_052407

Figure 3-1: Clock Sources on Starter Kit Board

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Chapter 3: Clock Sources

Clock Connections
Each of the clock inputs connect directly to a global buffer input. As shown in Table 3-1, each of the clock inputs also optimally connects to an associated DCM. Only the CLK_AUX or the CLK_SMA input can use the associated DCM at any time. However, both inputs are available as clock inputs. Table 3-1: Clock Inputs and Associated Global Buffers and DCMs
FPGA Pin E12 V12 U12 I/O Bank 0 2 2 Global Buffer GCLK5 GCLK2 GCLK3 Associated DCM Top Right Bottom Right LOC DCM_X2Y3 DCM_X2Y0

Clock Input CLK_50MHZ CLK_AUX CLK_SMA

50 MHz On-Board Oscillator

The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator is accurate to 2500 Hz or 50 ppm.

Auxiliary Clock Oscillator Socket

A 133 MHz clock oscillator is installed in the auxiliary clock oscillator socket. The provided eight-pin socket accepts clock oscillators that fit the eight-pin DIP (8DIP) footprint. Substitute the oscillator in this socket if the FPGA application requires a frequency other than 50 MHz or 133 MHz. Alternatively, use the FPGAs Digital Clock Manager (DCM) to generate or synthesize other frequencies from the on-board 50 MHz or 133 MHz oscillator. Caution! Be aware of the pin 1 orientation on the crystal oscillator when installing it in the
associated socket.

SMA Clock Input or Output Connector

To provide a clock from an external source, connect the input clock signal to the SMA connector. The FPGA can also generate a single-ended clock output or other high-speed signal on the SMA clock connector for an external device.

UCF Constraints
The clock input sources require two different types of constraints. The location constraints define the I/O pin assignments and I/O standards. The period constraints define the clock periodand consequently the clock frequencyand the duty cycle of the incoming clock signal.

Location
Figure 3-2 provides the UCF constraints for the three clock input sources, including the I/O pin assignment and the I/O standard used.

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Related Resources

NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ; NET "CLK_AUX" LOC = "V12"| IOSTANDARD = LVCMOS33 ; NET "CLK_SMA" LOC = "U12"| IOSTANDARD = LVCMOS33 ;

Figure 3-2:

UCF Location Constraints for Clock Sources

Clock Period Constraints

The Xilinx ISE development software uses timing-driven logic placement and routing. Set the clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3 for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which equates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to 60%.
# Define clock period for 50 MHz oscillator NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;

Figure 3-3: UCF Clock PERIOD Constraint

Related Resources
Refer to the following links for additional information: Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator) http://www.eea.epson.com/portal/pls/portal/docs/1/793426.PDF

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Chapter 3: Clock Sources

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Chapter 4

FPGA Configuration Options

The Spartan-3A/3AN FPGA Starter Kit board supports a variety of FPGA configuration options: Program the Spartan-3AN internal SPI Flash memory, then configure the FPGA at power-up. This option is not available in the Spartan-3A Starter Kit. Download FPGA designs directly to the Spartan-3A/3AN FPGA via JTAG, using the on-board USB interface. The on-board USB-JTAG logic also provides in-system programming for the on-board Platform Flash PROM. SPI serial Flash and StrataFlash programming are performed separately. Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then configure the FPGA from the image stored in the Platform Flash PROM using Master Serial mode. Program the on-board 16 Mbit STMicroelectronics SPI serial Flash PROM or the 16 Mbit Atmel SPI-based DataFlash PROM, then configure the FPGA from the image stored in the SPI serial Flash PROM using SPI mode. Further, an FPGA application can dynamically load different FPGA configurations using the FPGAs MultiBoot mode. See UG332: Spartan-3 Generation Configuration User Guide for additional details on the MultiBoot feature. See Chapter 12, SPI Serial Flash, for more information on using SPI serial Flash memory. Program the on-board 32 Mbit STMicroelectronics parallel NOR Flash PROM, then configure the FPGA from the image stored in the Flash PROM using BPI Up configuration mode. Further, an FPGA application can dynamically load different FPGA configurations using the FPGAs MultiBoot mode. See UG332: Spartan-3 Generation Configuration User Guide for additional details on the MultiBoot feature. See Chapter 11, Parallel NOR Flash PROM, for more information on using parallel Flash memory.

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Chapter 4: FPGA Configuration Options

Figure 4-1 indicates the position of the USB download/programming interface and the on-board non-volatile memories that potentially store FPGA configuration images.
16 Mbit Atmel DataFlash SPI Serial Flash 4 Mbit Platform Flash PROM USB-based Download/ Debugging Port
Uses standard USB cable

16 Mbit ST Micro SPI Serial Flash PROGRAM Button DONE LED In-System SPI Flash (Spartan-3AN Starter Kit board only)

FPGA Mode Select Jumpers

Parallel NOR Flash memory Byte Peripheral Interface (BPI) mode

UG334_c4_01_052407

32 Mbit STMicro Flash

Figure 4-1: Starter Kit FPGA Configuration Options The configuration mode jumpers determine which configuration mode the FPGA uses when power is first applied, or whenever the PROG button is pressed. The DONE pin LED lights when the FPGA successfully finishes configuration. Pressing the PROG button forces the FPGA to restart its configuration process. The Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial mode.

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Configuration Mode Jumpers

Configuration Mode Jumpers

As shown in Table 4-1, the J26 jumper block settings control the FPGAs configuration mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual jumpers to select the FPGAs configuration mode and associated configuration memory source. The J26 jumper block is shown in Figure 4-1. Table 4-1: Configuration Mode Jumper Settings
FPGA Configuration Image Source Spartan-3AN Starter Kit Board only! This mode configures a Spartan-3AN FPGA using the internal In-System Flash memory. This mode is not supported on the Spartan-3A Starter Kit board. Platform Flash PROM
M0 DONE
CE PROM

Mode Pins Configuration Mode M2:M1:M0 Internal Master SPI 0:1:1

J26 Jumper Settings

M0 M1 M2 J26

J46 Jumper Setting

Master Serial

0:0:0

Set the J46 jumper per Table 4-2

M1 M2 J26

GND J46

Master SPI (see Chapter 12, SPI Serial Flash)

0:0:1

Select SPI Serial Flash PROM starting at address 0

M0

Select specific SPI Flash PROM using Jumper J1 (Table 12-2, page 93). Disable the Platform Flash PROM via J46 jumper per Table 4-2. Master BPI Up (see Chapter 11, Parallel NOR Flash PROM) 0:1:0 Parallel NOR Flash PROM, starting at address 0 and incrementing through address space. Disable the Platform Flash PROM via J46 jumper per Table 4-2. JTAG 1:0:1 Downloaded from host via USB-JTAG port

M1 M2 J26

DISABLE
DONE
CE PROM

GND M0 M1 M2 J26 J46

M0 M1 M2 J26

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Chapter 4: FPGA Configuration Options

Xilinx Platform Flash Configuration PROM(s)

The Spartan-3A/3AN Starter Kit board includes a Xilinx Platform Flash configuration interface. A single 4 Mbit XCF04S Platform Flash PROM appears in the JTAG chain with the FPGA. Caution! The J46 jumper, shown in Table 4-2, page 40, enables or disables the Platform Flash
PROM on the board. Be aware of potential data contention issues with the SPI serial Flash and the D0 line of the parallel NOR Flash, depending on the current FPGA Configuration Mode Jumpers, shown in Table 4-1.

Caution! If the J46 jumper shown in Table 4-2, page 40 is set for Always Enabled, then the
FPGAs INIT_B pin controls the Platform Flash PROMs OE/RESET input. The INIT_B pin must be High to read any data, other than from the Platform Flash PROM.

When using the Platform Flash PROM to configure the FPGA, the configuration mode jumpers must be set for Master Serial mode, as shown in Table 4-2. If using any other configuration mode, the Platform Flash PROM must be disabled. Table 4-2: Platform Flash Enable Jumper (J46)
Platform Flash Allowed FPGA Enable (J46) Configuration Mode
DONE

Platform Flash Mode

Precautions/ Contention None. Platform Flash disabled. The FPGA application has full access to SPI serial Flash and parallel NOR Flash PROMs after configuration. None. Platform Flash enabled during configuration and disabled after configuration. The FPGA application has full access to SPI serial Flash and parallel NOR Flash PROMs after configuration. Platform Flash continuously enabled. The FPGA application can read additional data from Platform Flash after configuration as described in application note XAPP694: Reading User Data from Configuration PROMs. The FPGA application has no read access to SPI Flash or parallel NOR Flash.

Disabled (no jumper)

CE PROM

Any (see Table 4-1)

GND J46

DONE

Enabled during FPGA Configuration

CE PROM

Master Serial or JTAG

GND J46

DONE
CE PROM

Always Enabled

GND J46

Master Serial or JTAG

PROG Push-Button Switch

The PROG push-button switch, labeled in Figure 4-1, forces the FPGA to reconfigure from the configuration memory source selected by the Configuration Mode Jumpers, page 39. Press and release this button to restart the FPGA configuration process at any time.

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DONE Pin LED

DONE Pin LED

The DONE pin LED, labeled in Figure 4-1, lights whenever the FPGA is successfully configured. If this LED is not lit, then the FPGA is not configured.

Programming the FPGA or Platform Flash PROM via USB

The Spartan-3A/3AN Starter Kit includes embedded USB-based programming logic and a USB endpoint with a Type B connector. Via a USB cable connection with the host PC, the iMPACT programming software directly programs the FPGA, the Platform Flash PROM, or the on-board CPLD. Direct programming of the parallel or serial Flash PROMs is not presently supported.

Connecting the USB Cable

The kit includes a standard USB Type A/Type B cable, similar to the one shown in Figure 4-2. The actual cable color might vary from the picture.

USB Type B Connector

Connects to Starter Kit's USB connector

USB Type A Connector

Connects to computer's USB connector
UG230_c4_04_030306

Figure 4-2: Standard USB Type A/Type B Cable The wider and narrower Type A connector fits the USB connector at the back of the computer. After installing the Xilinx software, connect the square Type B connector to the Spartan3A/3AN Starter Kit board, as shown in Figure 4-3. The USB connector is on the left side of the board, immediately next to the Ethernet connector. When the board is powered on, the Windows operating system automatically recognizes and installs the associated driver software.

UG334_c4_03_052407

Figure 4-3: Connect the USB Type B Connector to the Starter Kit Board Connector

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Chapter 4: FPGA Configuration Options

When the USB cable driver is successfully installed and the board is correctly connected to the PC, a green LED lights up, indicating that the programming cable is ready. The USB connection also has a red LED, which only lights if the Xilinx software is programming firmware updates to the USB interface.

Platform Flash Programming Example in Spartan-3 Generation Configuration User Guide

The Spartan-3 Generation Configuration User Guide includes step-by-step instructions, some including screen shots, on how to prepare the FPGA bitstream and download it to the FPGA or PROM. UG332: Spartan-3 Generation Configuration User Guide www.xilinx.com/support/documentation/user_guides/ug332.pdf

For formatting and programming Platform Flash PROMs, please refer to the Master Serial Mode chapter.

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Chapter 5

Character LCD Screen

Overview
The Spartan-3A/3AN Starter Kit board prominently features a 2-line by 16-character liquid crystal display (LCD). The FPGA controls the LCD via the eight-bit data interface shown in Figure 5-1. The Spartan-3A/3AN Starter Kit board also supports the four-bit data interface to remain compatible with other Xilinx development boards. Caution! When using four-bit mode, the FPGA must drive the LCD_DB<3:0> signals High.

FPGA (Y15) (AB16)

(Y16)

LCD_DB<7> 390 LCD_DB<6> LCD_DB<5> LCD_DB<4> LCD_DB<3> LCD_DB<2> LCD_DB<1> LCD_DB<0> LCD_E LCD_RS LCD_RW

All

Character LCD Display

Four-bit data interface

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 E RS R/W

(AA12) (AB12) (AB17) (AA13) (Y13) (AB4) (Y14) (W13)

UG334_c5_01_052407

Figure 5-1:

Character LCD Interface

Once mastered, the LCD is a practical way to display a variety of information using standard ASCII and custom characters. However, these displays are not fast. Scrolling the display at half-second intervals tests the practical limit for clarity. Compared with the 50 MHz clock available on the board, the display is slow. A PicoBlaze processor efficiently controls display timing plus the actual content of the display.

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Eight-bit data interface

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Character LCD Interface Signals

Table 5-1 shows the interface character LCD interface signals. Table 5-1: Character LCD Interface
FPGA Pin Y15 AB16 Y16 AA12 AB12 AB17 AB18 Y13 AB4 Data bit DB7 Data bit DB6 Data bit DB5 Data bit DB4 Data bit DB3 Data bit DB2 Data bit DB1 Data bit DB0 Read/Write Enable Pulse 0: Disabled 1: Read/Write operation enabled LCD_RS Y14 Register Select 0: Instruction register during write operations. Busy Flash during read operations 1: Data for read or write operations LCD_RW W13 Read/Write Control 0: Write, LCD accepts data 1: Read, LCD presents data When using the four-bit interface, drive these signals High. Function

Signal Name LCD_DB<7> LCD_DB<6> LCD_DB<5> LCD_DB<4> LCD_DB<3> LCD_DB<2> LCD_DB<1> LCD_DB<0> LCD_E

Voltage Compatibility
The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However, the FPGAs output levels are recognized as valid Low or High logic levels by the LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by the FPGA meet the 5V TTL voltage level requirements. The 390 series resistors on the data lines prevent overstressing on the FPGA and StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD drives the data lines when LCD_RW is High. Most applications treat the LCD as a writeonly peripheral and never read from the display.

UCF Location Constraints

Figure 5-2 provides the UCF constraints for the Character LCD, including the I/O pin assignment and the I/O standard used.

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LCD Controller

NET "LCD_E" NET "LCD_RS" NET "LCD_RW"

NET NET NET NET NET NET NET NET

LOC = "AB4" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; LOC = "Y14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; LOC = "W13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = "Y15" "AB16" "Y16" "AA12" "AB12" "AB17" "AB18" "Y13" | | | | | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = = = = = LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 | | | | | | | | DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE = = = = = = = =

"LCD_DB<7>" "LCD_DB<6>" "LCD_DB<5>" "LCD_DB<4>" "LCD_DB<3>" "LCD_DB<2>" "LCD_DB<1>" "LCD_DB<0>"

8 8 8 8 8 8 8 8

| | | | | | | |

SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW

= = = = = = = =

SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW

; ; ; ; ; ; ; ;

Figure 5-2:

UCF Location Constraints for the Character LCD

LCD Controller
The 2 x 16 character LCD has an internal Sitronix ST7066U graphics controller that is functionally equivalent with the following devices. Samsung S6A0069X or KS0066U Hitachi HD44780 SMOS SED1278

Memory Map
The controller has three internal memory regions, each with a specific purpose: DD RAM, CG ROM, and CG RAM. The display must be initialized before accessing any of these memory regions.

DD RAM
The Display Data RAM (DD RAM) stores the character code to be displayed on the screen. Most applications interact primarily with DD RAM. The character code stored in a DD RAM location references a specific character bitmap stored either in the predefined CG ROM character set or in the user-defined CG RAM character set. Figure 5-3 shows the default address for the 32 character locations on the display. The upper line of characters is stored between addresses 0x00 and 0x0F. The second line of characters is stored between addresses 0x40 and 0x4F.
Character Display Addresses 1 2 00 40 1 01 41 2 02 42 3 03 43 4 04 44 5 05 45 6 06 46 7 07 47 8 08 48 9 09 49 10 0A 4A 11 0B 4B 12 0C 4C 13 0D 4D 14 0E 4E 15 0F 4F 16 Undisplayed Addresses 10 50 17 27 67 40

Figure 5-3: DD RAM Hexadecimal Addresses (No Display Shifting) Physically, there are 80 total character locations in DD RAM with 40 characters available per line. Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other non-display data. Alternatively, these locations can also store characters that can only be displayed using controllers display shifting functions.

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The Set DD RAM Address command initializes the address counter before reading or writing to DD RAM. Write DD RAM data using the Write Data to CG RAM or DD RAM command, and read DD RAM using the Read Data from CG RAM or DD RAM command. The DD RAM address counter either remains constant after read or write operations, or auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry Mode Set command.

CG ROM
The Character Generator ROM (CG ROM) contains the font bitmap for each of the predefined characters that the LCD screen can display, shown in Figure 5-4. The character code stored in DD RAM for each character location subsequently references a position with the CG ROM. For example, a hexadecimal character code of 0x53 stored in a DD RAM location displays the character S. The upper nibble of 0x53 equates to DB[7:4] = 0101 binary and the lower nibble equates to DB[3:0] = 0011 binary. As shown in Figure 5-4, the character S appears on the screen. English/Roman characters are stored in CG ROM at their equivalent ASCII code addresses.

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LCD Controller

DB7 DB6 DB5 DB4

Upper Data Nibble

Lower Data Nibble

DB3 DB2 DB1 DB0

UG230_c5_02_030306

Figure 5-4:

LCD Character Set

The character ROM contains the ASCII English character set and Japanese katakana characters. The controller also provides for eight custom character bitmaps, stored in CG RAM. These eight custom characters are displayed by storing character codes 0x00 through 0x07 in a DD RAM location.

CG RAM
The Character Generator RAM (CG RAM) provides space to create eight custom character bitmaps. Each custom character location consists of a 5-dot by 8-line bitmap, as shown in Figure 5-5. The Set CG RAM Address command initializes the address counter before reading or writing to CG RAM. Write CG RAM data using the Write Data to CG RAM or DD RAM command, and read CG RAM using the Read Data from CG RAM or DD RAM command.

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The CG RAM address counter either remains constant after read or write operations, or auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry Mode Set command. Figure 5-5 provides an example that creates a special checkerboard character. The custom character is stored in the fourth CG RAM character location, which is displayed when a DD RAM location is 0x03. To write the custom character, the CG RAM address is first initialized using the Set CG RAM Address command. The upper three address bits point to the custom character location. The lower three address bits point to the row address for the character bitmap. The Write Data to CG RAM or DD RAM command is used to write each character bitmap row. A 1 lights a bit on the display. A 0 leaves the bit unlit. Only the lower five data bits are used; the upper three data bits are dont care positions. The eighth row of bitmap data is usually left as all zeros to accommodate the cursor.
Upper Nibble Lower Nibble

Write Data to CG RAM or DD RAM A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Character Address 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Row Address 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 -

Dont Care 0 1 0 1 0 1 0 0

Character Bitmap 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0

Figure 5-5:

Example Custom Checkerboard Character with Character Code 0x03

Command Set
Table 5-2 summarizes the available LCD controller commands and bit definitions. Because the display is set up for four-bit operation, each eight-bit command is sent as two four-bit nibbles. The upper nibble is transferred first, followed by the lower nibble. Table 5-2: LCD Character Display Command Set (4-bit mode)
LCD_RW LCD_RS Upper Nibble DB7 DB6 DB5 DB4 DB3 Lower Nibble DB2 DB1 0 1 I/D C DB0 1 S B -

Function

Clear Display Return Cursor Home Entry Mode Set Display On/Off Cursor and Display Shift

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 1

0 0 0 1 S/C

0 0 1 D R/L

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LCD Controller

Table 5-2:

LCD Character Display Command Set (4-bit mode) (Continued)

LCD_RW LCD_RS Upper Nibble DB7 DB6 DB5 DB4 DB3 Lower Nibble DB2 DB1 A1 A1 A1 D1 D1 DB0 A0 A0 A0 D0 D0
49

Function

Function Set Set CG RAM Address Set DD RAM Address Read Busy Flag and Address Write Data to CG RAM or DD RAM Read Data from CG RAM or DD RAM

0 0 0 0 1 1

0 0 0 1 0 1

0 0 1 BF D7 D7

0 1 A6 A6 D6 D6

1 A5 A5 A5 D5 D5

0 A4 A4 A4 D4 D4

1 A3 A3 A3 D3 D3

0 A2 A2 A2 D2 D2

Disabled
If the LCD_E enable signal is Low, all other inputs to the LCD are ignored.

Clear Display
Clears the display and returns the cursor to the home position, the top-left corner. This command writes a blank space (ASCII/ANSI character code 0x20) into all DD RAM addresses. The address counter is reset to 0, location 0x00 in DD RAM. Clears all option settings. The I/D control bit is set to 1 (increment address counter mode) in the Entry Mode Set command. Execution Time: 82 s 1.64 ms

Return Cursor Home

Returns the cursor to the home position, the top-left corner. DD RAM contents are unaffected. Also returns the display being shifted to the original position, shown in Figure 5-3. The address counter is reset to 0, location 0x00 in DD RAM. The display is returned to its original status if it was shifted. The cursor or blink move to the top-left character location. Execution Time: 40 s 1.6 ms

Entry Mode Set

Sets the cursor move direction and specifies whether or not to shift the display. These operations are performed during data reads and writes. Execution Time: 40 s

Bit DB1: (I/D) Increment/Decrement

0 1 Auto-decrement address counter. Cursor/blink moves to left. Auto-increment address counter. Cursor/blink moves to right.

This bit either auto-increments or auto-decrements the DD RAM and CG RAM address counter by one location after each Write Data to CG RAM or DD RAM command or Read

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Chapter 5: Character LCD Screen

Data from CG RAM or DD RAM command. The cursor or blink position moves accordingly.

Bit DB0: (S) Shift

0 1 Shifting disabled During a DD RAM write operation, shift the entire display value in the direction controlled by Bit DB1 (I/D). It appears as though the cursor position remains constant and the display moves.

Display On/Off
The display is turned on or off, controlling all characters. The cursor and cursor position character (underscore) blink. Execution Time: 40 s

Bit DB2: (D) Display On/Off

0 1 No characters displayed. However, data stored in DD RAM is retained. Display characters stored in DD RAM

Bit DB1: (C) Cursor On/Off

The cursor uses the five dots on the bottom line of the character. The cursor appears as a line under the displayed character.
0 1 No cursor Display cursor

Bit DB0: (B) Cursor Blink On/Off

0 1 No cursor blinking Cursor blinks on and off approximately every half second

Cursor and Display Shift

Moves the cursor and shifts the display without changing DD RAM contents. Shift cursor position or display to the right or left without writing or reading display data. This function positions the cursor in order to modify an individual character, or to scroll the display window left or right to reveal additional data stored in the DD RAM, beyond the 16th character on a line. The cursor automatically moves to the second line when it shifts beyond the 40th character location of the first line. The first and second line displays shift at the same time. When the displayed data is shifted repeatedly, both lines move horizontally. The second display line does not shift into the first display line. Execution Time: 40 s

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LCD Controller

Table 5-3:
DB3 DB2 (S/C) (R/L) 0 0 1 1 0 1 0 1

Shift Patterns According to S/C and R/L Bits

Operation Shift the cursor position to the left. The address counter is decremented by one. Shift the cursor position to the right. The address counter is incremented by one. Shift the entire display to the left. The cursor follows the display shift. The address counter is unchanged. Shift the entire display to the right. The cursor follows the display shift. The address counter is unchanged.

Function Set
Sets the interface data length, the number of display lines, and the character font. The Starter Kit board supports a single function set with value 0x28. Execution Time: 40 s

Set CG RAM Address

Sets the initial CG RAM address. After this command, all subsequent read or write operations to the display are to or from CG RAM. Execution Time: 40 s

Set DD RAM Address

Sets the initial DD RAM address. After this command, all subsequent read or write operations to the display are to or from DD RAM. The addresses for displayed characters appear in Figure 5-3. Execution Time: 40 s

Read Busy Flag and Address

Reads the Busy flag (BF) to determine if an internal operation is in progress, and reads the current address counter contents. BF = 1 indicates that an internal operation is in progress. The next instruction is not accepted until BF is cleared or until the current instruction is allowed the maximum time to execute. This command also returns the present value of the address counter. The address counter is used for both CG RAM and DD RAM addresses. The specific context depends on the most recent Set CG RAM Address or Set DD RAM Address command issued. Execution Time: 1 s

Write Data to CG RAM or DD RAM

Writes data into DD RAM if the command follows a previous Set DD RAM Address command, or writes data into CG RAM if the command follows a previous Set CG RAM Address command.

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After the write operation, the address is automatically incremented or decremented by 1 according to the Entry Mode Set command. The entry mode also determines display shift. Execution Time: 40 s

Read Data from CG RAM or DD RAM

Reads data from DD RAM if the command follows a previous Set DD RAM Address command, or reads data from CG RAM if the command follows a previous Set CG RAM Address command. After the read operation, the address is automatically incremented or decremented by 1 according to the Entry Mode Set command. However, a display shift is not executed during read operations. Execution Time: 40 s

Operation
The board has an eight-bit data interface to the character LCD. Other Xilinx boards use a four-bit interface. As shown in Figure 5-1, the Spartan-3A/3AN Starter Kit board supports both an eight-bit and a four-bit interface for compatibility reasons. Many existing reference designs are already built around a four-bit interface.

Four-Bit Data Interface

Figure 5-6 illustrates a write operation to the LCD, showing the minimum times allowed for setup, hold, and enable pulse length relative to the 50 MHz clock (20 ns period) provided on the board.

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Operation

CLOCK 0 = Command, 1 = Data

LCD_RS

LCD_DB<7:4>

Valid Data

LCD_RW

LCD_E 230 ns

40 ns

10 ns

Upper 4 bits LCD_RS LCD_DB<7:4> LCD_RW LCD_E 1 s

Lower 4 bits

40 s
UG330_c5_03_072106

Figure 5-6: Character LCD Interface Timing The data values on LCD_DB<7:4>, and the register select (LCD_RS) and the read/write (LCD_RW) control signals must be set up and stable at least 40 ns before the enable LCD_E goes High. The enable signal must remain High for 230 ns or longerthe equivalent of 12 or more clock cycles at 50 MHz. In many applications, the LCD_RW signal can be tied Low permanently because the FPGA generally has no reason to read information from the display.

Transferring Eight-Bit Data over the Four-Bit Interface

After initializing the display and establishing communication in four-bit mode, all commands and data transfers to the character display are via eight bits, transferred using two sequential four-bit operations. Each eight-bit transfer must be decomposed into two four-bit transfers, spaced apart by at least 1 s, as shown in Figure 5-6. The upper nibble is transferred first, followed by the lower nibble. An eight-bit write operation must be spaced least 40 s before the next communication. This delay must be increased to 1.64 ms following a Clear Display command.

Initializing the Display

After power-on, the display must be initialized to establish the required communication protocol. The initialization sequence is simple and ideally suited to the highly-efficient eight-bit PicoBlaze embedded controller. After initialization, the PicoBlaze controller is available for more complex control or computation beyond simply driving the display.

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Chapter 5: Character LCD Screen

Power-On Initialization
The initialization sequence first establishes that the FPGA application wishes to use the four-bit data interface to the LCD as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Wait 15 ms or longer, although the display is generally ready when the FPGA finishes configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles. Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles. Wait 100 s or longer, which is 5,000 clock cycles at 50 MHz. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles. Wait 40 s or longer, which is 2,000 clock cycles at 50 MHz. Write LCD_DB<7:4> = 0x2, and pulse LCD_E High for 12 clock cycles. Wait 40 s or longer, which is 2,000 clock cycles at 50 MHz.

Display Configuration
After the power-on initialization is completed, the four-bit interface is established. The next part of the sequence configures the display: 1. 2. 3. 4. Issue a Function Set command, 0x28, to configure the display for operation on the Spartan-3A/3AN Starter Kit board. Issue an Entry Mode Set command, 0x06, to set the display to automatically increment the address pointer. Issue a Display On/Off command, 0x0C to turn the display on and disable the cursor and blinking. Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock cycles) after issuing this command.

Writing Data to the Display

To write data to the display, specify the start address, followed by one or more data values. Before writing any data, issue a Set DD RAM Address command to specify the initial seven-bit address in the DD RAM. See Figure 5-3 for DD RAM locations. Write data to the display using a Write Data to CG RAM or DD RAM command. The eightbit data value represents the look-up address into the CG ROM or CG RAM, shown in Figure 5-4. The stored bitmap in the CG ROM or CG RAM drives the 5 x 8 dot matrix to represent the associated character. If the address counter is configured to auto-increment, as described earlier, the application can sequentially write multiple character codes, and each character is automatically stored and displayed in the next available location. Continuing to write characters, however, eventually falls off the end of the first display line. The additional characters do not automatically appear on the second line because the DD RAM map is not consecutive from the first line to the second.

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Related Resources

Disabling the Unused LCD

If the FPGA application does not use the character LCD screen, drive the LCD_E pin Low to disable it. Also drive the LCD_RW pin Low to prevent the LCD screen from presenting data.

Related Resources
Refer to the following links for additional information: PowerTip PC1602-D Character LCD (Basic Electrical and Mechanical Data) www.powertipusa.com/pdf/pc1602d.pdf Sitronix ST7066U Character LCD Controller www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=204& partnum=S6A0069 Samsung S6A0069X Character LCD Controller
www.samsung.com/Products/Semiconductor/DisplayDriverIC/MobileDDI/ BWSTN/S6A0069X/S6A0069X.htm

Design Example: Device DNA Reader and LCD Display Controller www.xilinx.com/products/boards/s3astarter/reference_designs.htm#dna_reader

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Chapter 5: Character LCD Screen

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Chapter 6

VGA Display Port

The Spartan-3A/3AN FPGA Starter Kit board includes a VGA display port via a standard high-density HD-DB15 female connector. Connect this port directly to most PC monitors or flat-panel LCDs using a standard monitor cable. As shown in Figure 6-1, the VGA connector is the left-most connector along the top of the board.

FPGA

(C8) RED (B8 ) (B3) (A3) (D6) GREEN (C6) (D5) (C5) (C9) BLUE (B9) (D7) (C7) (B11)
SYNC

VGA_R<3> 510 VGA_R<2> VGA_R<1> VGA_R<0> VGA_G<3> 510 VGA_G<2> VGA_G<1> VGA_G<0> VGA_B<3> 510 VGA_B<2> VGA_B<1> VGA_B<0> VGA_VSYNC VGA_HSYNC 2 k 4 k 1 k 2 k 4 k 1 k 2 k 4 k 1 k

Red

Green

Blue

5 10 15

4 9 14

3 8 13

2 7 12

1 6 11

HD-DB15 VGA Connector (front view) (not VGA cable)

(C11)

82.5 Vertical 82.5 Horizontal

UG334_c6_01_052407

Figure 6-1: VGA Connections from the Starter Kit Board The FPGA directly drives the five VGA signals via resistors. Each red, green, and blue signal has four outputs from the FPGA that feed a resistor-divider tree. This approach

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Chapter 6: VGA Display Port

provides 4-bit resolution per color, generating 12-bit color, or 4,096 possible colors. The series resistor, in combination with the 75 termination built into the VGA cable, ensures that the color signals remain in the VGA-specified 0V to 0.7V range. The VGA_HSYNC and VGA_VSYNC signals use LVTTL or LVCMOS33 I/O standard drive levels. Drive the VGA_R[3:0], VGA_G[3:0], and VGA_B[3:0] signals High or Low to generate the desired colors. The scaled analog output is generated by a resistor-divider that converts the FPGAs digital outputs for an individual color. Each individual color output supports 16 possible values, as described by Equation 6-1. The three separate controls for red, green, and blue support a maximum of 12-bit color, or 4,096 values. VGA [ 3:0 ] - COLOR COLOR OUT = -------------------------15 Equation 6-1

For simplicity, the FPGA application can also treat the VGA port as a three-bit interface by driving all four color outputs with the same digital value. The corresponding eight basic color values are shown in Table 6-1. Table 6-1: Example Display Color Codes
VGA_G[3:0] 0000 0000 1111 1111 0000 0000 1111 1111 VGA_B[4:0] 0000 1111 0000 1111 0000 1111 0000 1111 Resulting Color Black Blue Green Cyan Red Magenta Yellow White

VGA_R[3:0] 0000 0000 0000 0000 1111 1111 1111 1111

Signal Timing for a 60 Hz, 640x480 VGA Display

VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA). The following VGA system and timing information is provided as an example of how the FPGA might drive the VGA monitor in 640 by 480 mode. For more precise information or for information on higher VGA frequencies, refer to documents available on the VESA website or other electronics websites (see Related Resources, page 61). Standard VGA support is part of the factory demonstration designs, but several extended VGA modes including SVGA are also achievable with faster timing controllers. CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCDs use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCDs have evolved to use the same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and LCDs.

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Signal Timing for a 60 Hz, 640x480 VGA Display

Within a CRT display, current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a raster pattern, horizontally from left to right and vertically from top to bottom. As shown in Figure 6-2, information is only displayed when the beam is moving in the forward directionleft to right and top to bottomand not during the time the beam returns back to the left or top edge of the display. Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass.

pixel 0,0

pixel 0,639

640 pixels are displayed each time the beam traverses the screen

VGA Display Retrace: No information is displayed during this time

Current through the horizontal deflection coil

pixel 479,0

pixel 479,639

Stable current ramp: Information is displayed during this time

Total horizontal time time "front porch" HS Horizontal sync signal sets the retrace frequency
Figure 6-2: CRT Display Timing Example The display resolution defines the size of the beams, the frequency at which the beam traces across the display, and the frequency at which the electron beam is modulated. Modern VGA displays support multiple display resolutions, and the VGA controller dictates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current

Horizontal display time

retrace time "front porch"

"back porch"
UG230_c6_02_021706

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Chapter 6: VGA Display Port

flows through the deflection coils, and it ensures that pixel or video data is applied to the electron guns at the correct time. Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location. The Spartan-3A/3AN Starter Kit board uses 12 bits per pixel, producing one of the 4,096 possible colors. The controller indexes into the video data buffer as the beams move across the display. The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel. As shown in Figure 6-2, the VGA controller generates the horizontal sync (HS) and vertical sync (VS) timing signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the refresh frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the displays phosphor and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz range. The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency.

VGA Signal Timing

The signal timings in Table 6-2 are derived for a 640-pixel by 480-row display using a 25 MHz pixel clock and 60 Hz 1 refresh. Figure 6-3 shows the relation between each of the timing symbols. The timing for the sync pulse width (TPW) and front and back porch intervals (TFP and TBP) is based on observations from various VGA displays. The front and back porch intervals are the pre- and post-sync pulse times. Information cannot be displayed during these times. Table 6-2:
Symbol

640x480 Mode VGA Timing

Vertical Sync Parameter Time Clocks 416,800 384,000 1,600 8,000 23,200 Lines 521 480 2 10 29 Time 32 s 25.6 s 3.84 s 640 ns 1.92 s Clocks 800 640 96 16 48 Sync pulse time Display time Pulse width Front porch Back porch 16.7 ms 15.36 ms 64 s 320 s 928 s Horizontal Sync

TS TDISP TPW TFP TBP

TS Tdisp Tfp

Tpw
Figure 6-3: VGA Control Timing

Tbp
UG230_c6_03_021706

Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded counter values generate the HS signal. This counter tracks the current pixel display location on a given row.

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UCF Location Constraints

A separate counter tracks the vertical timing. The vertical-sync counter increments with each HS pulse, and decoded values generate the VS signal. This counter tracks the current display row. These two continuously running counters form the address into a video display buffer. For example, the on-board DDR2 SDRAM provides an ideal display buffer. No time relationship is specified between the onset of the HS pulse and the onset of the VS pulse. Consequently, the counters can be arranged to easily form video RAM addresses or to minimize decoding logic for sync pulse generation.

UCF Location Constraints

Figure 6-4 provides the UCF constraints for the VGA display port, including the I/O pin assignment, the I/O standard used, the output slew rate, and the output drive current.
NET NET NET NET NET NET NET NET NET NET NET NET NET NET "VGA_R<3>" LOC = "C8" "VGA_R<2>" LOC = "B8" "VGA_R<1>" LOC = "B3" "VGA_R<0>" LOC = "A3" "VGA_G<3>" LOC = "D6" "VGA_G<2>" LOC = "C6" "VGA_G<1>" LOC = "D5" "VGA_G<0>" LOC = "C5" "VGA_B<3>" LOC = "C9" "VGA_B<2>" LOC = "B9" "VGA_B<1>" LOC = "D7" "VGA_B<0>" LOC = "C7" "VGA_HSYNC" LOC = "C11" "VGA_VSYNC" LOC = "B11" | | | | | | | | | | | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = = = = = = = = = = = LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 | | | | | | | | | | | | | | DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE = = = = = = = = = = = = = = 8 8 8 8 8 8 8 8 8 8 8 8 8 8 | | | | | | | | | | | | | | SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW = = = = = = = = = = = = = = FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST ; ; ; ; ; ; ; ; ; ; ; ; ; ;

Figure 6-4: UCF Constraints for VGA Display Port

Related Resources
Refer to the following links for additional information: VESA www.vesa.org VGA timing information www.epanorama.net/documents/pc/vga_timing.html

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Chapter 6: VGA Display Port

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Chapter 7

RS-232 Serial Ports

Overview
As shown in Figure 7-1, the Spartan-3A/3AN FPGA Starter Kit board has two RS-232 serial ports: a female DB9 DCE connector and a male DB9 DTE connector. The DCE-style port connects directly to the serial port connector available on most personal computers and workstations via a standard straight-through serial cable. For typical applications, the board does not require null modem cables, gender changers, or crossover cables. Use the DTE-style connector to control other RS-232 peripherals, such as modems or printers, or perform simple loopback testing with the DCE connector.
Computer Standard 9-pin serial cable Standard 9-pin serial cable RS-232 Peripheral
RS CS TR RD TD CD TALK/DATA TALK

DCE

DTE

DCE Female DB9 5 9 4 8 3 7 2 6 1 5 9 4

DTE Male DB9 3 8 7 2 6 1

J36

J27

GND

GND

RS-232 Voltage Translator (IC3)

RS232_DCE_RXD RS232_DCE_TXD RS232_DTE_RXD RS232_DTE_TXD

(E16) (F15)

(F16) (E15)

FPGA
UG334_c7_01_052407

Figure 7-1: RS-232 Serial Ports

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Chapter 7: RS-232 Serial Ports

Figure 7-1 shows the connection between the FPGA and the two DB9 connectors. The FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device, which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise, the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A series resistor between the Maxim output pin and the FPGAs RXD pin protects against inadvertent logic conflicts such as accidentally connecting the board using a null-modem cable. In this example, both the FPGA and the external serial device are driving data on the transmit line. Hardware flow control is not supported on the connector. The ports DCD, DTR, and DSR signals connect together, as shown in Figure 7-1. Similarly, the ports RTS and CTS signals connect together.

UCF Location Constraints

Figure 7-2 and Figure 7-3 provide the UCF constraints for the DTE and DCE RS-232 ports, respectively, including the I/O pin assignment and the I/O standard used.
NET "RS232_DTE_RXD" LOC = "F16" | IOSTANDARD = LVCMOS33 ; NET "RS232_DTE_TXD" LOC = "E15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

Figure 7-2: UCF Location Constraints for DTE RS-232 Serial Port
NET "RS232_DCE_RXD" LOC = "E16" | IOSTANDARD = LVCMOS33 ; NET "RS232_DCE_TXD" LOC = "F15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

Figure 7-3:

UCF Location Constraints for DCE RS-232 Serial Port

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Chapter 8

PS/2 Mouse/Keyboard Port

The Spartan-3A/3AN FPGA Starter Kit board includes a PS/2 mouse/keyboard port and the standard six-pin mini-DIN connector, labeled J28 on the board. Figure 8-1 shows the PS/2 connector, and Table 8-1 shows the signals on the connector. Use the primary connections indicated to connect a mouse or keyboard directly to the board. Also see Adding a Second PS/2 Port Using a Y-Splitter Cable, page 69.

Secondary Connection
(requires Y-splitter cable)

Primary Connection
270

270

PS2_DATA2: (Y12) 2 4
270

PS2_DATA1: (V11) 1 6 3 5
270

PS2_CLK2: (U11)

PS2_CLK1: (W12)

UG334_c8_01_052407

Figure 8-1: PS/2 Connector Location and Signals Table 8-1: PS/2 Connector Pinout
Signal Primary data connection PS2_DATA1 Secondary data connection when using PS/2 splitter cable PS2_DATA2 GND +5V Primary clock connection PS2_CLK1 Secondary data connection with using PS/2 splitter cable PS2_CLK2 FPGA Pin V11 Y12 GND No Connection W12 U11

PS/2 DIN Pin 1 2 3 4 5 6

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Chapter 8: PS/2 Mouse/Keyboard Port

The PS/2 port I/Os should always be set to LVCMOS33 with the PULLUP attribute set true when used. If this attribute is not set, the voltage on the PS/2 I/Os will be greater than the maximum specified permissible amount in the data sheet. These I/Os can be damaged if the bitstream option for unused I/Os is set to float and the FPGA design is not using the PS/2 port pins. Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host device, the FPGA in this case. The PS/2 bus includes both clock and data. Both a mouse and keyboard drive the bus with identical signal timings, and both use 11-bit words that include a start, a stop, and an odd parity bit. However, the data packets are organized differently for a mouse and keyboard. Both the keyboard and mouse interfaces allows bidirectional data transfers. For example, the FPGA host design can illuminate the state LEDs on the keyboard or change the communicate rate with the mouse. The PS/2 bus timing appears in Table 8-2 and Figure 8-2. The clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at a logic High. The timing defines signal requirements for mouse-to-host communications and bidirectional keyboard communications. As shown in Figure 8-2, the attached keyboard or mouse writes a bit on the data line when the clock signal is High, and the host reads the data line when the clock signal is Low. Table 8-2:
Symbol

PS/2 Bus Timing

Parameter Clock High or Low Time Data-to-clock Setup Time Clock-to-data Hold Time Min 30 s 5 s 5 s Max 50 s 25 s 25 s

TCK TSU THLD

Edge 0 CLK (PS2C) TSU DATA (PS2D)

TCK TCK

Edge 10

THLD

'0' start bit

'1' stop bit

UG230_c8_02_021806

Figure 8-2: PS/2 Bus Timing Waveforms

Keyboard
The keyboard uses open-collector drivers so that either the device or the host can drive the two-wire bus. If the host never sends data, then the host can use simple input pins. A PS/2-style keyboard uses scan codes to communicate key-press data. Each key has a single, unique scan code that is sent whenever the corresponding key is pressed. The scan codes for most keys appear in Figure 8-3. If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or so. When a key is released, the keyboard sends an F0 key-up code, followed by the scan code of the released key. The keyboard sends the same scan code, regardless if a key has

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Keyboard

different shift and non-shift characters and regardless whether the Shift key is pressed or not. The host determines which character is intended. Some keys, called extended keys, send an E0 ahead of the scan code, and furthermore, they might send more than one scan code. When an extended key is released, an E0 F0 key-up code is sent, followed by the scan code.

ESC 76 `~ 0E TA B 0D
Caps Lock

F1 05 1! 16 2@ 1E Q 15 A 1C Z 1Z W 1D

F2 06 3# 26

F3 04 4$ 25 E 24 D 23 C 21

F4 0C 5% 2E R 2D F 2B V 2A T 2C G 34 6^ 36

F5 03 7& 3D Y 35 H 33

F6 0B 8* 3E U 3C J 3B

F7 83 9( 46 I 43 K 42

F8 0A 0) 45 O 44 L 4B >. 49 P 4D

F9 01 -_ 4E

F10 09 =+ 55 [{ 54 '" 52

F11 78

F12 07

E0 75

Back Space

66 ]} 5B \| 5D Enter 5A Shift 59 Ctrl E0 14

E0 74 E0 6B E0 72

58 Shift 12 Ctrl 14

S 1B X 22 Alt 11

;: 4C /? 4A Alt E0 11

B 32

N 31 Space 29

M 3A

,< 41

UG230_c8_03_021806

Figure 8-3:

PS/2 Keyboard Scan Codes

The host can also send commands and data to the keyboard. Table 8-3 provides a short list of some often-used commands. Table 8-3: Common PS/2 Keyboard Commands
Description Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs. The keyboard acknowledges receipt of an ED command by replying with an FA, after which the host sends another byte to set LED status. The bit positions for the keyboard LEDs are shown below. Write a 1 to the specific bit to illuminate the associated keyboard LED. 7 6 5 Ignored EE F3 FE FF 4 3 2 Caps Lock 1 Num Lock 0 Scroll Lock

Command ED

Echo. Upon receiving an echo command, the keyboard replies with the same scan code EE. Set scan code repeat rate. The keyboard acknowledges receipt of an F3 by returning an FA, after which the host sends a second byte to set the repeat rate. Resend. Upon receiving a resend command, the keyboard resends the last scan code. Reset. Resets the keyboard.

The keyboard sends commands or data to the host only when both the data and clock lines are High, the Idle state. Because the host is the bus master, the keyboard checks whether the host is sending data before driving the bus. The clock line can be used as a clear to send signal. If the host pulls the clock line Low, the keyboard must not send any data until the clock is released.

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The keyboard sends data to the host in 11-bit words that contain a 0 start bit, followed by eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a 1 stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to 30 kHz, and data is valid on the falling edge of the clock as shown in Figure 8-2.

Mouse
PS/2-compatible mice potentially support two modes. In polled mode, the host controller interrogates the mouse for activity. In streaming mode, the mouse reports any movement or key presses. Streaming mode is the default operating mode. To specifically enter streaming mode, the FPGA host must transmit a Set Stream Mode command (0xEA) to the mouse. The mouse then generates a clock and data signal when moved or when one or more keys are pressed; otherwise, these signals remain High, indicating the Idle state. Each time the mouse is moved, the mouse sends three 11-bit words to the host. Each of the 11-bit words contains a 0 start bit, followed by 8 data bits (LSB first), followed by an odd parity bit, and terminated with a 1 stop bit. Each data transmission contains 33 total bits, where bits 0, 11, and 22 are 0 start bits, and bits 10, 21, and 32 are 1 stop bits. The three eight-bit data fields contain movement data as shown in Figure 8-4. Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.
Mouse status byte 1 0 L R C 1 XS YS XV YV P 1 X direction byte 0 X0 X1 X2 X3 X4 X5 X6 X7 P 1 Y direction byte 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P Stop bit Start bit Idle state
UG330_c8_04_032007

Start bit Idle state

Stop bit

Start bit

Stop bit

Figure 8-4: PS/2 Mouse Transaction A PS/2-style mouse employs a relative coordinate system (see Figure 8-5), wherein moving the mouse to the right generates a positive value in the X field, and moving to the left generates a negative value. Likewise, moving the mouse up generates a positive value in the Y field, and moving it down represents a negative value. The XS and YS bits in the status byte define the sign of each value, where a 1 indicates a negative value.
+Y values (YS=0)

-X values (XS=1)

+X values (XS=0)

-Y values (YS=1)

UG230_c8_05_021806

Figure 8-5:

The Mouse Uses a Relative Coordinate System to Track Movement

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Voltage Supply

The magnitude of the X and Y values represents the rate of mouse movement. The larger the value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when the X or Y values exceed their maximum value, an overflow condition. A 1 indicates when an overflow occurs. If the mouse moves continuously, the 33-bit transmissions repeat every 50 ms or so. The L, R, and C fields in the status byte correspond to Left, Right, and Center button presses. A 1 indicates that the associated mouse button is being pressed.

Voltage Supply
The PS/2 port on the Spartan-3A/3AN Starter Kit board is powered by 5V. Although the Spartan-3A/3AN FPGA is not a 5V-tolerant device, it can communicate with a 5V device using 270 series current-limiting resistors, as shown in Figure 8-1, page 65.

Adding a Second PS/2 Port Using a Y-Splitter Cable

Most applications that use the PS/2 port will connect a mouse or a keyboard directly to the Spartan-3A/3AN Starter Kit board connector. These applications use the primary FPGA connections to the PS/2 port, as shown in Figure 8-1, page 65. However, it is possible to include a second PS/2 port by connecting a PS/2 Y-splitter cable to the PS/2 connector on the board. Figure 8-6 shows an example of such a cable. The Spartan-3A/3AN Starter Kit does not include such a cable but one can be purchased from a local electronics supply store or via the web. Some example vendors and part numbers are listed below. Check various vendors and suppliers as prices vary greatly! StarTech PS/2 Keyboard/Mouse Y-splitter Cable, KYC1MF American Power Conversion (APC) Mouse and Keyboard Splitter Cable, 62305-1 Belkin Pro Series Notebook Y Cable, F3G117-01 Tripp Lite, P230-001 QVS CC321Y ComputerCableStore.com, 8-1718Y-00.5 CablesToGo, 08017

UG330_c8_02_012507

Figure 8-6: Example PS/2 Y-Splitter Cable When using the splitter cable, use both sets of FPGA connections listed in Figure 8-1, page 65 and Table 8-1, page 65. The primary connections appear at one side of the Y-splitter while the secondary connections appear at the other side of the Y-splitter.

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UCF Location Constraints

Figure 8-7 provides the UCF constraints for the PS/2 port connecting, including the I/O pin assignment and the I/O standard used.
# Primary connection NET "PS2_CLK1" LOC = "W12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; NET "PS2_DATA1" LOC = "V11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; # Secondary connection (requires Y-splitter cable) NET "PS2_CLK2" LOC = "U11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; NET "PS2_DATA2" LOC = "Y12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

Figure 8-7: UCF Location Constraints for PS/2 Port

Related Resources
Refer to the following links for additional information: PS/2 Mouse/Keyboard Protocol www.computer-engineering.org/ps2protocol PS/2 Keyboard Interface www.computer-engineering.org/ps2keyboard PS/2 Mouse Interface www.computer-engineering.org/ps2mouse

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Chapter 9

Analog Capture Circuit

The Spartan-3A/3AN FPGA Starter Kit board includes a two-channel analog capture circuit, consisting of a programmable scaling pre-amplifier and an analog-to-digital converter (ADC), as shown in Figure 9-1.

Linear Tech LTC1407A-1 Dual A/D

SPI_SCK: (AA20) AD_CONV: (Y6) AD_DOUT: (D16)

Linear Tech LTC6912-1 Dual Amp

SPI_MOSI: (AB14) AMP_CS: (W6) SPI_SCK: (AA20) AMP_SHDN: (W15) AMP_DOUT: (T7)

6-pin ADC Header (J22)

UG334_c9_01_052407

Figure 9-1: Analog Capture Circuit and Associated Stake Pin Header (J22) The analog capture circuit consists of a Linear Technology LTC6912-1 programmable preamplifier that scales the incoming analog signal on the J22 header. The output of the preamplifier connects to a Linear Technology LTC1407A-1 ADC. Both the pre-amplifier and the ADC are serially programmed or controlled by the FPGA.

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Chapter 9: Analog Capture Circuit

Header J22 DAC_REF_AB

(3.3V)

DAC_REF_CD
(3.3V)

DAC_REF_CD reference voltage is nominally 3.3V. The reference is supplied by the LP3906 adjustable regulator, IC18. The voltage is adjustable using the regulators I2C interface. LTC 6912-1 AMP

LTC 1407A-1 ADC A/D Channel 0

VINA

14

VINB

A/D Channel 1

GND

VCC
(3.3V) REF = 1.65V 14

FPGA
(D16) (T7) (AB14) (W6) (AA20) (W15) SPI_MOSI AMP_CS SPI_SCK AMP_SHDN DIN 0 1 2 3 0 1 2 3 B GAIN CS/LD A GAIN DOUT 0 ... 13 0 ... 13 SDO

CHANNEL 1 CHANNEL 0 SCK SPI Control Interface CONV

SCK SPI Control Interface SHDN

(Y6)

AD_CONV

AMP_DOUT AD_DOUT
UG334_c9_02_052407

Figure 9-2:

Detailed View of Analog Capture Circuit

Digital Outputs from Analog Inputs

The analog capture circuit converts the analog voltage on VINA or VINB and converts it to a 14-bit digital representation, D[13:0], as expressed by Equation 9-1. ( V IN 1.65 V ) - 8192 D [ 13:0 ] = GAIN ----------------------------------1.25 V Equation 9-1

The GAIN is the current setting loaded into the programmable pre-amplifier. The various allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs appear in Table 9-2. The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage divider shown in Figure 9-2. Consequently, 1.65V is subtracted from the input voltage on VINA or VINB. The maximum range of the ADC is 1.25V, centered around the reference voltage, 1.65V. Hence, 1.25V appears in the denominator to scale the analog input accordingly.

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Programmable Pre-Amplifier

Finally, the ADC presents a 14-bit, twos complement digital output. A 14-bit, twos complement number represents values between -213 and 213-1. Therefore, the quantity is scaled by 8192, or 213. See Programmable Pre-Amplifier to control the GAIN settings on the programmable pre-amplifier. The reference design files provide more information on converting the voltage applied on VINA or VINB to a digital representation (see Related Resources, page 77).

Programmable Pre-Amplifier
The LTC6912-1 provides two independent, inverting amplifiers with programmable gain. The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it maximizes the conversion range of the DAC, namely 1.65 1.25V.

Interface
Table 9-1 lists the interface signals between the FPGA and the amplifier. The SPI_MOSI and SPI_SCK signals are shared with other devices on the SPI bus. The AMP_CS signal is the active-Low slave select input to the amplifier. Table 9-1:
Signal SPI_MOSI

AMP Interface Signals

FPGA Pin AB14 Direction FPGAAMP Description Serial data: Master Output, Slave Input. Presents eight-bit programmable gain settings, as defined in Table 9-2. Active-Low chip select. The amplifier gain is set when the signal returns High. Clock Active-High shutdown, reset Serial data. Echoes previous amplifier gain settings. Can be ignored in most applications.

AMP_CS SPI_SCK AMP_SHDN AMP_DOUT

W6 AA20 W15 T7

FPGAAMP FPGAAMP FPGAAMP FPGAAMP

Programmable Gain
Each analog channel has an associated programmable gain amplifier (see Figure 9-2). Analog signals presented on the VINA or VINB inputs on the J7 header are amplified relative to 1.65V. The 1.65V reference is generated using a voltage divider of the 3.3V voltage supply. The gain of each amplifier is programmable from -1 to -100, as shown in Table 9-2. Table 9-2:
Gain 0 -1 -2

Programmable Gain Settings for Pre-Amplifier

A3 B3 0 0 0 A2 B2 0 0 0 A1 B1 0 0 1 A0 B0 0 1 0 0.4 1.025 2.9 2.275 Input Voltage Range Minimum Maximum

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Table 9-2:
Gain -5 -10 -20 -50 -100

Programmable Gain Settings for Pre-Amplifier (Continued)

A3 B3 0 0 0 0 0 A2 B2 0 1 1 1 1 A1 B1 1 0 0 1 1 A0 B0 1 0 1 0 1 Input Voltage Range Minimum 1.4 1.525 1.5875 1.625 1.6375 Maximum 1.9 1.775 1.7125 1.675 1.6625

SPI Control Interface

Figure 9-3 highlights the SPI-based communications interface with the amplifier. The gain for each amplifier is sent as an eight-bit command word, consisting of two four-bit fields. The most-significant bit, B3, is sent first.
AMP_DOUT

0 SPI_MOSI AMP_CS SPI_SCK

Slave: LTC2624-1

A0 A1 A2 A3 B0 B1 B2 B3
A Gain B Gain
UG334_c9_03_052407

FPGA Master

Figure 9-3:

SPI Serial Interface to Amplifier

The AMP_DOUT output from the amplifier echoes the previous gain settings. These values can be ignored for most applications. The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see Figure 9-4). The amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal. The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK.
AMP_CS
30 50 50

SPI_SCK
30

SPI_MOSI
(from FPGA)

5
85 max

AMP_DOUT
(from AMP)

Previous 7

2
UG230_c10_04_022306

All timing is minimum in nanoseconds unless otherwise noted.

Figure 9-4: SPI Timing When Communicating with Amplifier The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.

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Analog-to-Digital Converter (ADC)

UCF Location Constraints

Figure 9-5 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used.
NET NET NET NET NET "SPI_MOSI" "AMP_CS" "SPI_SCK" "AMP_SHDN" "AMP_DOUT" LOC LOC LOC LOC LOC = = = = = "AB14"| "W6" | "AA20"| "W15" | "T7" | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = = LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 | | | | ; SLEW SLEW SLEW SLEW = = = = SLOW SLOW SLOW SLOW | | | | DRIVE DRIVE DRIVE DRIVE = = = = 8 8 8 8 ; ; ; ;

Figure 9-5:

UCF Location Constraints for the Pre-amplifier Interface (AMP)

Analog-to-Digital Converter (ADC)

The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneously when the AD_CONV signal is applied.

Interface
Table 9-3 lists the interface signals between the FPGA and the ADC. The SPI_SCK signal is shared with other devices on the SPI bus. The active-High AD_CONV signal is the activeLow slave select input to the DAC. The DAC_CLR signal is the active-Low, asynchronous reset input to the DAC. Table 9-3:
Signal SPI_SCK AD_CONV ADC_OUT

ADC Interface Signals

FPGA Pin AA20 Y6 D16 Direction FPGAADC Clock FPGAADC Active-High, initiates conversion process. FPGAADC Serial data. Presents the digital representation of the sample analog values as two 14-bit twos complement binary values. Description

SPI Control Interface

Figure 9-6 provides an example SPI bus transaction to the ADC. When the AD_CONV signal goes High, the ADC simultaneously samples both analog channels. The results of this conversion are not presented until the next time AD_CONV is asserted, a latency of one sample. The maximum sample rate is approximately 1.5 MHz. The ADC presents the digital representation of the sampled analog values as a 14-bit, twos complement binary value.

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Chapter 9: Analog Capture Circuit

ADC_OUT Slave: LTC1407A-1 A/D Converter

AD_CONV

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13

FPGA Master

SPI_SCK

Z Channel 1

Z Channel 0
Converted data is presented with a latency of one sample. The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV. The converted values is then presented after the next AD_CONV pulse. Sample

Sample point AD_CONV SPI_SCK ADC_OUT

point

Channel 0 13

Channel 1 13

Channel 0 13
UG334_c9_06_052407

Figure 9-6:

Analog-to-Digital Conversion Interface

Figure 9-7 shows detailed transaction timing. The AD_CONV signal is not a traditional SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC leaves the ADC_OUT signal in the high-impedance state. As shown in Figure 9-6, use a 34-cycle communications sequence. The ADC 3-states its data output for two clock cycles before and after each 14-bit data transfer.
4ns min

AD_CONV
3ns 19.6ns min

SPI_SCK

3 Channel 0 13

4
8ns

ADC_OUT

High-Z

12

11

AD_CONV
45ns min

SPI_SCK

30

31

32

33
6ns

34

Channel 1 3 ADC_OUT

High-Z

The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
UG330_c10_06_032007

Figure 9-7: Detailed SPI Timing to ADC

UCF Location Constraints

Figure 9-8 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used.
NET "AD_CONV" NET "SPI_SCK" NET "AD_DOUT" LOC = "Y6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; LOC = "D16" | IOSTANDARD = LVCMOS33 ;

Figure 9-8: UCF Location Constraints for the ADC Interface

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Connecting Analog Inputs

Connecting Analog Inputs

Connect AC signals to VINA or VINB via a DC blocking capacitor.

Related Resources
Refer to the following links for additional information: Xilinx PicoBlaze Soft Processor http://www.xilinx.com/picoblaze LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1121,P7596,D5359

LTC1407A-1 Serial 14-bit Simultaneous Sampling ADCs with Shutdown

http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158,P2420,D1295

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Chapter 10

Digital-to-Analog Converter (DAC)

The Spartan-3A/3AN FPGA Starter Kit board includes an SPI-compatible, four-channel, serial Digital-to-Analog Converter (DAC). The DAC device is a Linear Technology LTC2624 quad DAC with 12-bit unsigned resolution. The four outputs from the DAC appear on the J21 header, which uses the Digilent six-pin Peripheral Module format. The DAC and the header are located immediately below the Ethernet RJ-45 connector, as shown in Figure 10-1.

Linear Tech LTC2624 Quad DAC

SPI_MOSI: (AB14) SPI_SCK: (AA20) DAC_CS: (W7) DAC_CLR: (AB13) DAC_OUT: (V7)

6-pin DAC Header (J21)

Figure 10-1:

UG334_c10_01_052407

DAC and Associated Stake Pin Header (J21)

SPI Communication
As shown in Figure 10-2, the FPGA uses a Serial Peripheral Interface (SPI) to communicate digital values to each of the four DAC channels. The SPI bus is a full-duplex, synchronous, character-oriented channel employing a simple four-wire interface. A bus masterthe FPGA in this exampledrives the bus clock signal (SPI_SCK) and transmits serial data (SPI_MOSI) to the selected bus slavethe DAC in this example. At the same time, the bus slave provides serial data (SPI_MISO) back to the bus master.

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LTC 2624 DAC

REF A

Header J5 DAC A
VOUTA

3.3V
12 REF B

DAC B
12

VOUTB

3.3V by default. Programmable reference supplied by adjustable LP3906 regulator, IC18.

REF C

DAC C
12 REF D

VOUTC

DAC D FPGA
(V7) (AB14) (W7) (AA20) (AB13) 12

VOUTD

SPI_MOSI DAC_CS SPI_SCK

SDI CS/LD SCK CLR

SDO

GND

SPI Control Interface

VCC
(3.3V)

DAC_CLR

DAC_OUT

UG334_c10_02_052407

Figure 10-2: Digital-to-Analog Connection Schematics

Interface Signals
Table 10-1 lists the interface signals between the FPGA and the DAC. The SPI_MOSI, DAC_OUT, and SPI_SCK signals are shared with other devices on the SPI bus. The DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is the active-Low, asynchronous reset input to the DAC. Table 10-1:
Signal SPI_MOSI DAC_CS

DAC Interface Signals

FPGA Pin AB14 W7 Direction FPGADAC FPGADAC Description Serial data: Master Output, Slave Input Active-Low chip-select. Digital-to-analog conversion starts when this signal returns High. Clock Asynchronous, active-Low reset input Serial data from the DAC

SPI_SCK DAC_CLR DAC_OUT

AA20 AB13 V7

FPGADAC FPGADAC FPGADAC

The serial data output from the DAC is primarily used to cascade multiple DACs. This signal can be ignored in most applications although it does demonstrate full-duplex communication over the SPI bus.

SPI Communication Details

Figure 10-3 shows a detailed example of the SPI bus timing. Each bit is transmitted or received relative to the SPI_SCK clock signal. The bus is fully static and supports clock rates up to the maximum of 50 MHz. However, check all timing parameters using the LTC2624 data sheet if operating at or close to the maximum speed.

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SPI Communication

DAC _CS SPI_MOSI SPI_SCK DAC _OUT Previous 31

Figure 10-3:

31

30

29

Previous 30

Previous 29
UG330_c9_03 _071906

SPI Communication Waveforms

After driving the DAC_CS slave select signal Low, the FPGA transmits data on the SPI_MOSI signal, MSB first. The LTC2624 captures input data (SPI_MOSI) on the rising edge of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge. The LTC2624 DAC transmits its data on the DAC_OUT signal on the falling edge of SPI_SCK. The FPGA captures this data on the next rising SPI_SCK edge. The FPGA must read the first DAC_OUT value on the first rising SPI_SCK edge after DAC_CS goes Low. Otherwise, bit 31 is missed. After transmitting all 32 data bits, the FPGA completes the SPI bus transaction by returning the DAC_CS slave select signal High. The High-going edge starts the actual digital-to-analog conversion process within the DAC.

Communication Protocol
Figure 10-4 shows the communications protocol required to interface with the LTC2624 DAC. The DAC supports both 24-bit and 32-bit protocol. The 32-bit protocol is shown. Inside the DAC, the SPI interface is formed by a 32-bit shift register. Each 32-bit command word consists of a command and an address, followed by a data value. As a new command enters the DAC, the previous 32-bit command word is echoed back to the master. The response from the DAC can be ignored although it is a useful to confirm correct communication.
DAC_OUT SPI_MOSI DAC_CS

0 31 Slave: LTC2624 DAC x x x x 0 1 2 3 4 5 6 7 8 9 10 11 a0 a1 a2 a3 c0 c1 c2 c3 x x x x x x x x

lsb Dont Care 12-bit Unsigned msb Dont Care

Master FPGA

SPI_SCK

DATA
a3 0 0 0 0 1 a2 0 0 0 0 1 a1 0 0 1 1 1 a0 0 1 0 1 1

COMMAND ADDRESS
DAC A DAC B DAC C DAC D All

UG334_c10_04_052407

Figure 10-4:

SPI Communications Protocol to LTC2624 DAC

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The FPGA first sends eight dummy or dont care bits, followed by a four-bit command. The most commonly used command with the board is COMMAND[3:0] = 0011 binary, which immediately updates the selected DAC output with the specified data value. Following the command, the FPGA selects one or all the DAC output channels via a four-bit address field. Following the address field, the FPGA sends a 12-bit unsigned data value that the DAC converts to an analog value on the selected output(s). Finally, four additional dummy or dont care bits pad the 32-bit command word.

Specifying the DAC Output Voltage

As shown in Figure 10-2, each DAC output level is the analog equivalent of a 12-bit unsigned digital value, D[11:0], written by the FPGA to the DAC via the SPI interface. The voltage on a specific output is generally described in Equation 10-1. The reference voltage, VREFERENCE, is different between the four DAC outputs. Channels A and B use a 3.3V reference voltage. Channels C and D have a separate reference voltage, nominally also 3.3V, supplied by the LP3906 regulator designated as IC18. The reference voltage for Channels C and D can be modified, as described in I2C Voltage Adjustment Interface, page 138. The reference voltages themselves have a 5% tolerance, so there are slight corresponding variances in the output voltage. D [ 11:0 ] - V REFERENCE V OUT = -------------------4096 , Equation 10-1

UCF Location Constraints

Figure 10-5 provides the UCF constraints for the DAC interface, including the I/O pin assignment and the I/O standard used.
NET NET NET NET NET "SPI_MOSI" "SPI_SCK" "DAC_CS" "DAC_CLR" "DAC_OUT" LOC LOC LOC LOC LOC = = = = = "AB14" "AA20" "W7" "AB13" "V7" | | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = = LVCMOS33 | SLEW LVCMOS33 | SLEW LVCMOS33 | SLEW LVCMOS33 | SLEW LVCMOS33 ; = = = = SLOW SLOW SLOW SLOW | | | | DRIVE DRIVE DRIVE DRIVE = = = = 8 8 8 8 ; ; ; ;

Figure 10-5:

UCF Location Constraints for the DAC Interface

Related Resources
Refer to the following links for additional information: LTC2624 Quad DAC Data Sheet
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1005,C1156,P2048,D2170

Xilinx PicoBlaze Soft Processor http://www.xilinx.com/picoblaze Digilent, Inc. Peripheral Modules

http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral

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Chapter 11

Parallel NOR Flash PROM

As shown in Figure 11-1, the Spartan-3A/3AN FPGA Starter Kit board includes a 32 Mbit (4 Mbyte) parallel NOR Flash PROM.

FPGA LDC0 LDC1 HDC LDC2 User-I/O User-I/O User-I/O User-I/O NF_CE NF_OE NF_WE NF_BYTE NF_STS NF_RP NF_WP NF_D<14:8> NF_D<7:1> SPI_MISO NF_A<21:1> NF_A<0> E

STMicro M29DW323DT

G W BYTE RB RP WP DQ[14:8] DQ[7:1] DQ[0] A[20:0] D15/A-1 32 Mbit

D[7:1]
D[0] A[21:1] A[0] A[25:22]

UG334_c11_01_052407

Figure 11-1:

Connections to 32 Mbit Parallel NOR Flash Memory

The parallel NOR Flash PROM provides various functions: Stores a single FPGA configuration in the Flash memory. Stores various, different FPGA configurations in the Flash memory and dynamically switches between the various images using the FPGAs MultiBoot feature. Stores and executes MicroBlaze processor code directly from the Flash memory. Stores MicroBlaze processor code in the Flash memory and shadows the code into the DDR2 SDRAM memory before executing the code. Stores non-volatile user data from the FPGA application.

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Flash Connections
Table 11-1 shows the connections between the FPGA and the Flash memory device. Although the XC3S700A/AN FPGA only requires just slightly over 2.6 Mbits per uncompressed configuration image, the FPGA-to-Flash interface on the board supports up to a 256 Mbit Flash. The Spartan-3A/3AN Starter Kit board ships with a 32 Mbit device. Address lines SF_A<25:22> are not used. In general, the Flash memory device connects to the FPGA to support Byte Peripheral Interface (BPI) configuration, as described in Table 11-1. Table 11-1:
Category

FPGA-to-Flash Connections
NOR Flash Signal Name FPGA Pin Number Function

NF_A25 NF_A24 NF_A23 NF_A22 NF_A21 NF_A20 NF_A19 NF_A18 NF_A17 NF_A16 NF_A15 NF_A14
Address

G17 G18 B21 B22 C21 C22 F21 F22 H20 H21 G22 H22 J20 J21 J22 K22 N17 N18 N19 N20 N21 N22 P18 R19 T18 T17

The upper four Flash addresses are not used on the board. The board only has a 32 Mbit parallel NOR Flash PROM.

Connects to FPGA pins A[21:0] to support the BPI configuration.

NF_A13 NF_A12 NF_A11 NF_A10 NF_A9 NF_A8 NF_A7 NF_A6 NF_A5 NF_A4 NF_A3 NF_A2
NF_A1 NF_A0

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Flash Connections

Table 11-1:
Category

FPGA-to-Flash Connections (Continued)

NOR Flash Signal Name NF_D15 (NF_A0) NF_D14 NF_D13 NF_D12 NF_D11 NF_D10 NF_D9 NF_D8 FPGA Pin Number Function Upper 8 bits of a 16-bit halfword when Flash is configured for x16 data (NF_BYTE=High). The Flash does not have a dedicated D15 pin. Instead, this function is shared with the leastsignificant address pin. On the Flash memory component, this pin is named D15/A-1, which connects to the FPGAs A0 address pin. After configuration, if the FPGA application asserts NF_BYTE-High, use NF_A0 to carry the D15 signal. Connect the other higher-order data lines to FPGA user I/Os.

T17 R21 T22 U22 U21 V22 W22 T20 Y9 AB9 Y11 AB11 U13 AA17 Y17 AB20

Data

NF_D7 NF_D6 NF_D5 NF_D4 NF_D3 NF_D2 NF_D1 NF_D0 (SPI_MISO)

Upper 7 bits of a data byte or lower 8 bits of a 16-bit halfword. Connects to FPGA pins D[7:1] to support the BPI configuration.

Bit 0 of a data byte and a 16-bit halfword. Connects to FPGA pin D0/DIN to support the BPI configuration. Shared with other SPI peripherals and Platform Flash PROM.

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Table 11-1:
Category

FPGA-to-Flash Connections (Continued)

NOR Flash Signal Name NF_BYTE FPGA Pin Number Function Active-Low Flash Byte Enable. Connects to FPGA pin LDC2 to support the BPI configuration. 0: x8 data 1: x16 data NF_CE

Y21

W20

Active-Low Flash Chip Enable. Connects to FPGA pin LDC0 to support the BPI configuration. 0: Enabled 1: Disabled

NF_OE

W19

Active-Low Flash Chip Enable. Connects to FPGA pin LDC1 to support the BPI configuration. 0: Enable data outputs to read Flash data 1: Disabled

Control

NF_RP

R22

Active-Low Flash Reset. Connects to FPGA user-I/O pin. 0: Reset 1: Flash active

NF_STS NF_WE

P22 AA22

Flash Status signal. Optional input to FPGA open-drain output from Flash. Active-Low Flash Write Enable. Connects to FPGA pin HDC to support the BPI configuration. 0: Enable Flash data write operations 1: Disabled

NF_WP

E14

Active-Low Hardware Write Protect. Connects to FPGA user-I/O pin. 0: Protect two outermost Flash boot blocks against all program and erase operations. 1: Hardware protection disabled.

Shared SPI Flash and Platform Flash Data Line

The least-significant Flash data line, NF_D<0>, is shared with data output signals from the serial SPI serial Flash PROMs and the serial output from the Platform Flash PROM as shown in Table 11-2, page 87. To avoid contention, the FPGA application must ensure that only one data source is active at any time.

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UCF Location Constraints

Table 11-2:
Signal or Jumper Jumper J46

Possible Potential Competing Devices on SPI_MISO (NF_D<0>) Data

Disabled Device Platform Flash PROM. Disable Value Set to Disabled or Enable during Configuration as shown in Table 4-2, page 40. FPGA_INIT_B has no effect. If set to Always Enabled, then FPGA_INIT_B must be 1

FPGA_INIT_B

SPI_SS_B

SPI Flash PROM selected by Jumper J1, as shown in Table 12-2, page 93. SPI Flash PROM selected by Jumper J1, as shown in Table 12-2, page 93.

ALT_SS_B

UCF Location Constraints

Address
Figure 11-2 provides the UCF constraints for the Flash address pins, including the I/O pin assignment and the I/O standard used.
NET "NF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<21>" LOC = "C21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<20>" LOC = "C22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<19>" LOC = "F21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<18>" LOC = "F22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<17>" LOC = "H20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<16>" LOC = "H21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<15>" LOC = "G22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<14>" LOC = "H22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<13>" LOC = "J20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<12>" LOC = "J21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<11>" LOC = "J22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<10>" LOC = "K22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<9>" LOC = "N17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<8>" LOC = "N18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<7>" LOC = "N19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<6>" LOC = "N20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<5>" LOC = "N21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<4>" LOC = "N22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<3>" LOC = "P18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<2>" LOC = "R19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<1>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | NET "NF_A<0>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | # Upper four address lines, NF_A<25:22>, are unconnected using a # They are available as user I/Os but do not connect to anything CONFIG PROHIBIT = B22; CONFIG PROHIBIT = B21; CONFIG PROHIBIT = G18; CONFIG PROHIBIT = G17; SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = SLEW = 32Mbit on the SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; SLOW ; Flash board

Figure 11-2:

UCF Location Constraints for Flash Address Signals

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Chapter 11: Parallel NOR Flash PROM

Data
Figure 11-3 provides the UCF constraints for the Flash data pins, including the I/O pin assignment and the I/O standard used.
# NET "NF_D<15>" --> NET "NF_D<14>" LOC = NET "NF_D<13>" LOC = NET "NF_D<12>" LOC = NET "NF_D<11>" LOC = NET "NF_D<10>" LOC = NET "NF_D<9>" LOC = NET "NF_D<8>" LOC = NET "NF_D<7>" LOC = NET "NF_D<6>" LOC = NET "NF_D<5>" LOC = NET "NF_D<4>" LOC = NET "NF_D<3>" LOC = NET "NF_D<2>" LOC = NET "NF_D<1>" LOC = NET "SPI_MISO" LOC = use NF_A<0> on pin T17 when NF_BYTE = "R21" | IOSTANDARD = LVCMOS33 | DRIVE "T22" | IOSTANDARD = LVCMOS33 | DRIVE "U22" | IOSTANDARD = LVCMOS33 | DRIVE "U21" | IOSTANDARD = LVCMOS33 | DRIVE "V22" | IOSTANDARD = LVCMOS33 | DRIVE "W22" | IOSTANDARD = LVCMOS33 | DRIVE "T20" | IOSTANDARD = LVCMOS33 | DRIVE "Y9" | IOSTANDARD = LVCMOS33 | DRIVE "AB9" | IOSTANDARD = LVCMOS33 | DRIVE "Y11" | IOSTANDARD = LVCMOS33 | DRIVE "AB11" | IOSTANDARD = LVCMOS33 | DRIVE "U13" | IOSTANDARD = LVCMOS33 | DRIVE "AA17" | IOSTANDARD = LVCMOS33 | DRIVE "Y17" | IOSTANDARD = LVCMOS33 | DRIVE "AB20" | IOSTANDARD = LVCMOS33 | DRIVE High = 8 | = 8 | = 8 | = 8 | = 8 | = 8 | = 8 | = 8 | = 8 | = 8 | = 8 | = 8 | = 8 | = 8 | = 8 | SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW = = = = = = = = = = = = = = = SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

Figure 11-3:

UCF Location Constraints for Flash Data I/O Pins

Control
Figure 11-4 provides the UCF constraints for the Flash control pins, including the I/O pin assignment and the I/O standard used.
NET NET NET NET NET NET NET "NF_BYTE" "NF_CE" "NF_OE" "NF_RP" "NF_STS" "NF_WE" "NF_WP" LOC LOC LOC LOC LOC LOC LOC = = = = = = = "Y21" "W20" "W19" "R22" "P22" "AA22" "E14" | | | | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = = = = LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 | | | | ; | | DRIVE DRIVE DRIVE DRIVE = = = = 8 8 8 8 | | | | SLEW SLEW SLEW SLEW = = = = SLOW SLOW SLOW SLOW ; ; ; ;

DRIVE = 8 | SLEW = SLOW ; DRIVE = 8 | SLEW = SLOW ;

Figure 11-4:

UCF Location Constraints for Flash Control Pins

Setting the FPGA Mode Select Pins

To configure the FPGA from NOR Flash, set the FPGA configuration mode pins for BPI Up mode, as shown in Table 11-3. The Spartan-3A/3AN FPGA families do not support the BPI Down mode that is available in the Spartan-3E FPGA family. Also be sure to disable the Platform Flash PROM by removing jumper J46, as shown in Table 11-3. Table 11-3: Selecting BPI-Up Configuration Mode (J26)
Mode Pins M2:M1:M0 0:1:0 FPGA Configuration Image in Flash FPGA starts at address 0 and increments through address space. Mode Select Jumper Settings (J26)
M0 M1 M2 J26 J46

Configuration Mode BPI Up

Platform Flash Enable (J46)

DONE
CE PROM

GND

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Creating and Programming Configuration Images for Parallel Flash

Creating and Programming Configuration Images for Parallel Flash

Due to the high fanout of the CCLK signal on the Starter Kit board, it is recommended that the FPGA CCLK frequency be set to 1 MHz when creating FPGA configuration images for the parallel Flash. See UG332 for information on typical configuration clock speeds supported for custom boards. Refer to the Master BPI Mode chapter in the Spartan-3 Generation Configuration User Guide for information on how to create and format FPGA configuration images for parallel Flash. To program the parallel Flash memory, see the associated design example. UG332: Spartan-3 Generation Configuration User Guide www.xilinx.com/support/documentation/user_guides/ug332.pdf Design Example: Programmer for the STMicroelectronics M29DW323DT Parallel NOR Flash www.xilinx.com/products/boards/s3astarter/reference_designs.htm#parallel_flash _programmer

Related Resources
Refer to the following links for additional information: STMicroelectronics M29DW323DT 32 Mbit Parallel NOR Flash PROM www.numonyx.com/Documents/Datasheets/M29DW323D.pdf Design Example: Programmer for the STMicroelectronics M29DW323DT Parallel NOR Flash www.xilinx.com/products/boards/s3astarter/reference_designs.htm#parallel_flash _programmer

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Chapter 12

SPI Serial Flash

The Spartan-3A/3AN FPGA Starter Kit board includes two different styles of SPI serial Flash, as shown in Figure 12-1. Only one style is available to configure the FPGA. After configuration, however, the FPGA application has full access to both PROMs for data storage or Flash update purposes. STMicroelectronics M25P16 16 Mbit SPI serial Flash PROM Atmel AT45DB161D 16 Mbit SPI serial DataFlash PROM
Atmel AT45DB161D Platform Flash Jumper (J46) STMicro M25P16 SPI Flash Select Jumpers (J1)

JTAG and SPI Programming Blocks (J23, J25)

FPGA Mode Select Jumpers (J26)

UG334_c12_01_052407

Figure 12-1:

SPI Serial Flash PROMs and Associated Jumpers

The SPI serial Flash is useful in a variety of applications. The SPI Flash provides a possible means to configure the FPGAa new feature in Spartan-3E and Spartan-3A/3AN FPGAs. The SPI Flash is also available to the FPGA after configuration for a variety of purposes, such as: Simple non-volatile data storage Storage for identifier codes, serial numbers, IP addresses, etc. Storage of MicroBlaze processor code that can be shadowed into DDR SDRAM.

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FPGA
(AB20) (AB14) (AA20) SPI_MISO SPI_MOSI SPI_SCK 16Mbit AT45DB161D SI DATAFLASH_WP DATAFLASH_RST SCK WP RST CS ST_SPI_WP ALT_SS_B
ROM-CS0 CSO-B CSO-SEL ROM-CS1

10

16Mbit M25P16 D C W 1 HLD S Q

10

SO

(C14) (C15)

(C13) (Y5)

= 4.7k to 3.3V

(Y4)

SPI_SS_B SPI Flash Select Jumpers (J1)

UG334_c12_02_052407

Figure 12-2: Table 12-1:

Signal SPI_MISO SPI_MOSI SPI_SCK SPI_SS_B

SPI Serial Flash Interface

SPI Flash PROM Interface Signals

FPGA Pin AB20 AB14 AA20 Y4 Direction
FPGAPROM FPGAPROM FPGAPROM

Description Serial data: Master Input, Slave Output Serial data: Master Output, Slave Input Clock. Actively toggles during configuration. User I/O pin after configuration. Asynchronous, active-Low slave select signal. Actively drives Low during SPI Flash configuration mode. User I/O pin after configuration. Drive High if unused. Steered to selected SPI Flash PROM Select Jumpers (J1), page 93. Second, asynchronous, active-Low slave select signal. Pulled High during configuration. User I/O pin after configuration. Drive High if unused. Steered to selected SPI Flash PROM Select Jumpers (J1), page 93. Write-protect input to Atmel AT45DB161D PROM. Must be High to program the PROM. Has external 4.7k pull-up resistor. Reset input to Atmel AT45DB161D PROM. Must be High to read, program, or erase the PROM. Has external 4.7k pull-up resistor. Write-protect input to ST M25P16 PROM. Must be High to program the PROM. Has external 4.7k pull-up resistor.

FPGAPROM

ALT_SS_B

Y5

FPGAPROM

DATAFLASH_WP

C14 C15 C13

FPGAPROM

DATAFLASH_RST

FPGAPROM

ST_SPI_WP

FPGAPROM

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SPI Flash PROM Select Jumpers (J1)

SPI Flash PROM Select Jumpers (J1)

The J1 jumper block, shown in Figure 12-1, defines which SPI Flash PROM is connected to the FPGA for Master SPI mode configuration and which is optionally available via a separate, second SPI slave select signal. Table 12-2 indicates how the FPGAs CSO_B signal is steered to one of the SPI Flash PROMs during Master SPI configuration mode. The jumpers are designed so that there can be no conflict. If both jumpers are inserted and oriented vertically, then the FPGA configures from the Atmel SPI Flash PROM. After configuration, the FPGA application selects the Atmel PROM using the SPI_SS_B signal and the STMicro PROM using the ALT_SS_B signal. If both jumpers are inserted and oriented horizontally, then the FPGA configures from the STMicro SPI Flash PROM. After configuration, the FPGA application selects the STMicro PROM using SPI_SS_B signal and the Atmel PROM using the ALT_SS_B signal. SPI Flash PROM Select Jumper Settings
After Configuration Jumper J1 Setting
J1

Table 12-2:

Atmel AT45DB161D SPI Mode Configuration Source Slave Select Signal

STMicro M25P16 Slave Select Signal

Atmel AT45DB161D

SPI_SS_B (Y4)

N/A

J1

STMicro M25P16

N/A

SPI_SS_B (Y4)

J1

Atmel AT45DB161D

SPI_SS_B (Y4)

ALT_SS_B (Y5)

J1

STMicro M25P16

ALT_SS_B (Y5)

SPI_SS_B (Y4)

J1

None

None

None

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Shared SPI Flash and Platform Flash Data Line

The SPI_MISO signal from the two SPI Flash PROMs is shared with data output signals from the parallel NOR Flash PROM and the serial output from the Platform Flash PROM as shown in Table 12-3. To avoid contention, the FPGA application must ensure that only one data source is active at any time. Table 12-3:
Signal or Jumper Jumper J46 FPGA_INIT_B

Possible Potential Competing Devices on SPI_MISO (NF_D<0>) Data

Disabled Device Platform Flash PROM. Disable Value Set to Disabled or Enable during Configuration as shown in Table 4-2, page 40. FPGA_INIT_B has no effect. If set to Always Enabled, then FPGA_INIT_B must be 1

SPI_SS_B

SPI Flash PROM selected by Jumper J1, as shown in Table 12-2, page 93. SPI Flash PROM selected by Jumper J1, as shown in Table 12-2, page 93. Parallel Flash PROM

ALT_SS_B

NF_CE NF_OE

NF_CE = 1 or NF_OE = 1

Jumper Settings to Configure FPGA from Selected SPI Flash PROM

To successfully configure the FPGA from the selected external SPI Flash PROM, set the following jumpers as described below. Set the FPGA configure mode, using the Jumper J26 jumper header, shown in Table 12-4. Disable the Platform Flash PROM using Jumper J46, shown in Table 12-4. Configuration Mode Jumper Settings for Master SPI Mode (J26, J46)
Mode Pins M2:M1:M0 0:0:1
M0 M1 M2 J26 J46

Table 12-4:

Configuration Mode Master SPI

Jumper J26 Settings

Platform Flash Enable (J46)

DONE
CE PROM

GND

Select one of the SPI serial Flash PROMs as the SPI configuration source, as shown in Table 12-2.

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UCF Location Constraints

UCF Location Constraints

Figure 12-3 provides the UCF constraints for the SPI serial Flash PROM, including the I/O pin assignment and the I/O standard used.
# some connections shared with NET "SPI_MISO" LOC = "AB20" | NET "SPI_MOSI" LOC = "AB14" | NET "SPI_SCK" LOC = "AA20" | NET "SPI_SS_B" LOC = "Y4" | NET "ALT_SS_B" LOC = "Y5" | SPI Flash, IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD DAC, ADC, and AMP = LVCMOS33 ; = LVCMOS33 | SLEW = LVCMOS33 | SLEW = LVCMOS33 | SLEW = LVCMOS33 | SLEW

= = = =

SLOW SLOW SLOW SLOW

| | | |

DRIVE DRIVE DRIVE DRIVE

= = = =

8 8 8 8

; ; ; ;

# write-protect and reset controls for Atmel AT45DB161D PROM NET "DATAFLASH_WP" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "DATAFLASH_RST" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # write-protect control for ST M25P16 PROM NET "ST_SPI_WP" LOC = "C13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

Figure 12-3:

UCF Location Constraints for SPI Flash Connections

Creating and Programming Configuration Images for SPI Serial Flash

Refer to the Master SPI Mode chapter in the Spartan-3 Generation Configuration User Guide for information on how to create and format FPGA configuration images for SPI serial Flash and how to program SPI Flash using the Xilinx iMPACT software. UG332: Spartan-3 Generation Configuration User Guide www.xilinx.com/support/documentation/user_guides/ug332.pdf

SPI Flash PROM Programming Options

Starting with ISE 9.1i, Service Pack 2 and later, the iMPACT programming software supports two different methods to program an attached SPI Flash PROM, as summarized in Table 12-5. Using the Direct Programming Method, the programming cable communicates directly to the SPI Flash PROM. The FPGA is not involved in the programming process and the FPGA I/O pins that connect to the PROM must be in their high-impedance state (Hi-Z) during programming. Hold the FPGAs PROG_B input Low using jumper J16 to place the I/Os in Hi-Z; the FPGAs DONE pin remains Low. Using the Indirect Programming Method, the programming cable connects to the FPGAs JTAG port. The iMPACT software first programs the FPGA with a special design that performs the SPI PROM programming and uses the JTAG interface as a serial communications port. During the process, the FPGAs DONE output is High and the DONE LED is lit because the FPGA is configured with the programming logic. All pins that are not connected to the SPI Flash PROM or the JTAG interface have an internal pull-up resistor to the VCCO voltage supply associated with the pin.

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Table 12-5:

Summary of SPI Flash PROM Programming Options

Direct Method Indirect Method ISE 9.1i, Service Pack 2 or later FPGAs JTAG Port High (FPGA is configured with special programming design) N/A Pulled High using internal pull-up resistor to associated VCCO supply input

ISE Version Required Interface/Cable Connection DONE Pin Status during Programming Required PROG_B Control Status of non-SPI Pins during Programming

ISE 9.1i or later Directly to SPI PROM Low PROG_B = Low High-impedance because PROG_B = Low

Direct Programming Method

The iMPACT software supports direct programming of select SPI serial Flash. The Spartan3A/3AN Starter Kit board primarily supports direct programming using the embedded USB JTAG programmer included on the board. Optionally, the SPI Flash can be programmed using a separate programming cable, as well.

Using Embedded USB JTAG Programmer

Follow these steps to prepare the board for direct SPI Flash programming using the embedded USB JTAG programmer included on the board. 1. 2. Disconnect power to the board. Connect either a USB cable between the board and the PC, or connect a separate JTAG cable as described in Using a Separate JTAG Parallel Programming Cable (Optional), page 97. Locate the J1, J23, and J25 jumpers in the upper right corner of the board, using Figure 12-1 as a guide. Figure 12-4 also provides a reference diagram.
STMicro PROM Atmel PROM

3.

J1
ROM-CS0 CSO-B
TMS TDI

J1
CSO-SEL ROM-CS1
GND VCC TDO TCK

ROM-CS0 CSO-B

CSO-SEL ROM-CS1

JTAG Header SPI Header

CSO-B SDO SCK SDI GND VCC

J25 J23

PROG_B GND PROG_B

J16

UG330_c15_05_032907

Figure 12-4:

Jumper Settings for Direct SPI Flash Programming

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Creating and Programming Configuration Images for SPI Serial Flash

4.

Insert a jumper in jumper block J1, as shown in Figure 12-4. The figure shows the setting to program the STMicro M25P16 PROM. Alternatively, set the jumper to program the Atmel AT45DB161D DataFlash PROM. Insert four jumpers between jumper blocks J25 and J23, as shown in Figure 12-4. These jumpers connect the embedded USB JTAG programmer on the J25 jumper pins to the SPI PROM via the J23 jumper pins. Set the FPGA mode select pins for Master SPI mode using jumper J26, as shown in Table 12-4. The location of the J26 jumper appears in Figure 12-1. Disable the Platform Flash PROM by removing jumper J46, shown in Figure 12-1 and Table 12-4. For direct programming, the FPGAs PROG_B pin must be held Low. Insert a jumper in jumper J16, as shown in Figure 12-4. This holds all the FPGAs I/O in three-state to allow the JTAG programmer full access to the SPI PROM pins. Re-apply power to the board.

5.

6. 7. 8.

9.

Using a Separate JTAG Parallel Programming Cable (Optional)

Using Embedded USB JTAG Programmer is the preferred programming method. With the jumpers installed between the J23 and J25 headers, the embedded USB programmer communicates directly to the SPI Flash PROM. However, it is possible to communicate directly to the SPI Flash PROM using another a programming cable, such as: Xilinx Parallel Cable IV with flying leads Digilent JTAG3 or JTAG-USB programming cable

Connect the cable directly to the J23 header block, as illustrated in Figure 12-5. These cables are not provided with the Spartan-3A/3AN Starter Kit board but can be purchased separately.

a) JTAG3 Parallel Connector

b) Parallel Cable III or Parallel Cable IV with Flying Leads

UG334_c12_05_052407

Figure 12-5: Attaching a JTAG Parallel Programming Cable to the Board

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First, turn off the power on the Starter Kit board. If the USB cable is attached to the board, disconnect it. Simultaneously connecting both the USB cable and the parallel cable to the PC confuses the iMPACT software. Connect one end of the JTAG parallel programming cable to the parallel printer port of the PC. Connect the JTAG end of the cable to Header J23, as shown in Figure 12-5a. The J23 header connects directly to the SPI Flash pins; it is not connected to the JTAG chain. The JTAG3 cable directly mounts to Header J23. The labels on the JTAG3 cable face toward the J11 jumpers. If using flying leads, they must be connected as shown in Figure 12-5b and Table 12-6. Note the color coding for the leads. The gray INIT lead is left unconnected. Table 12-6: Cable Connections to J23 Header
Connections SEL TMS TMS/ PROG SDI TDI TDI/ DIN SDO TDO TDO/ DONE SCK TCK TCK/ CCLK GND GND GND/ GND VCC VCC VREF/ VREF

Cable and Labels J23 Header Label JTAG3 Cable Label Flying Leads Label

Direct SPI Flash Programming Using iMPACT

The following steps describe how to program the SPI PROM using the iMPACT software and a Xilinx programming cable. 1. Click Direct SPI Configuration from within iMPACT, as shown in Figure 12-6.

3 1 2

UG332_c4_03_101006

Figure 12-6: 2. 3.

iMPACT Supports Direct Programming for SPI Serial Flash Memories

Right-click in the area indicated. Select Add SPI Device.

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Creating and Programming Configuration Images for SPI Serial Flash

4.

Select a previously formatted PROM file, as shown in Figure 12-7.

4 5

UG332_c4_04_101006

Figure 12-7: 5. 6. Click Open.

Select a Previously Formatted PROM File

Select the Part Name for a supported SPI serial Flash, as shown in Figure 12-8.

6 7

UG332_c4_05_101006

Figure 12-8: Select a Supported SPI Flash Memory Device 7. Click OK.

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8.

The iMPACT software displays the selected SPI Flash PROM, as shown in Figure 12-9.

14
UG332_c4_06_101006

Figure 12-9: 9. Click Program.

Directly Program Supported SPI Flash PROM

Note: Step 14 occurs later. 10. Click the Programming Properties option under Category, as shown in Figure 12-10.

10

11

12 13

UG332_c4_07_101006

Figure 12-10: SPI PROM Programming Options 11. Check Verify. Unchecking Verify reduces programming time but the iMPACT software can only guarantee correct programming for a verified PROM.

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Creating and Programming Configuration Images for SPI Serial Flash

12. Check Erase Before Programming. Unchecking the Erase option reduces programming time. However, Xilinx recommends erasing the PROM when downloading a new FPGA bitstream. 13. Click OK. 14. The iMPACT software indicates successful programming, as shown in Figure 12-9. After programming completes: 15. Turn off power to the board. 16. Remove Jumper J16 to release the FPGAs PROG_B pin. 17. Remove the four jumpers connecting jumper blocks J23 and J25. 18. Reapply power.

Indirect Programming Method

Indirect programming support is available starting with Xilinx ISE 9.1i, Service Pack 2 and later releases. In Indirect mode, the iMPACT software programs the memory attached to the FPGA through the FPGAs JTAG port. During the programming process, the FPGA is configured with a special programming application. Consequently, the FPGAs DONE pin is High and the DONE LED remains lit throughout the programming process. Note: Any information displayed on the LCD screen remains on the screen throughout the programming process. If it appears that programming was successful but that the DONE pin did not go High at the end, double-check the mode pin settings.

Jumper Settings
To program the attached and selected SPI PROM using the Indirect method, configure the board as described below. 1. 2. Disconnect power to the board. Insert a jumper in jumper block J1, as shown in Figure 12-4. The figure shows the setting to program the STMicro M25P16 PROM. Alternatively, set the jumper to program the Atmel AT45DB161D DataFlash PROM. Set the FPGA mode select pins for Master SPI mode using jumper J26, as shown in Table 12-4. The location of the J26 jumper appears in Figure 12-1. Disable the Platform Flash PROM by removing jumper J46, shown in Figure 12-1 and Table 12-4. The PROG_B pin is not used by the Indirect programming mode. Be sure that jumper J16 is removed (PROG_B is left floating). Connect the included USB cable to both the Starter Kit board and the computer running iMPACT. Re-apply power to the board.

3. 4. 5. 6. 7.

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Indirect SPI Flash Programming Using iMPACT

To program the attached and selected SPI PROM using the iMPACT software and the Indirect programming method, follow the steps outlined below. 1. Invoke iMPACT and select Configure devices using Boundary Scan (JTAG), as shown in Figure 12-11.

UG332_c4_22_032807

Figure 12-11: 2. Select Finish.

Indirect Programming Method Uses JTAG

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Creating and Programming Configuration Images for SPI Serial Flash

3.

Select the FPGA bitstream file (*.bit) to be programmed into the FPGA, as shown in Figure 12-12. This step is superfluous but required for iMPACT 9.1i. This step will be eliminated starting in iMPACT 9.2i. This file is not the special FPGA-based SPI programming application.

UG332_c4_23_032807

Figure 12-12: 4. 5. 6.

Select the FPGA Bitstream File and Enable SPI Programming

Select Enable Programming of SPI Flash Device Attached to this FPGA. Click Open. The iMPACT software warns that it changed the Startup clock source over to the JTAG clock pin, TCK. The SPI Flash image is not affected. This warning is safely ignored.

6
UG332_c4_24_032807

Figure 12-13:

iMPACT Uses the JTAG Clock Input TCK for Startup Clock when Programming via JTAG

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Chapter 12: SPI Serial Flash

7.

As shown in Figure 12-14, select the programming file for the attached SPI Flash PROM.

7 8

UG332_c4_26_032907

Figure 12-14: Select the SPI PROM Programming FIle 8. 9. Click Open. Select the part number for the attached SPI Flash PROM, as shown in Figure 12-15.

9 10

UG332_c4_27_032907

Figure 12-15: 10. Click OK.

Select SPI Flash PROM Type

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Creating and Programming Configuration Images for SPI Serial Flash

11. Select Bypass when prompted for the Platform Flash PROM programming file, as shown in Figure 12-16.

11

UG332_c4_28_032907

Figure 12-16: Bypass the Platform Flash PROM 12. As shown in Figure 12-17, the iMPACT software then displays the JTAG chain for the XC3S700A Spartan-3A FPGA followed by the XCF04S Platform Flash PROM. A similar display will be seen for the XC3S700AN Spartan-3AN FPGA. Click to highlight the FLASH memory attached to the XC3S700A FPGA. This action enables the command options shown in Step 13.

12

18 13

UG332_c4_25_032907

Figure 12-17:

iMPACT Presents JTAG Chain, Shows Attached Flash PROM

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Chapter 12: SPI Serial Flash

13. Double-click Program. Note: Step 18 occurs later. 14. Click the Programming Properties option under Category, as shown in Figure 12-18.

14

15

16 17

UG332_c4_29_032907

Figure 12-18: SPI PROM Programming Options 15. Check Verify. Unchecking Verify reduces programming time but the iMPACT software can only guarantee correct programming for a verified PROM. 16. Check Erase Before Programming. Unchecking the Erase option reduces programming time. However, Xilinx recommends erasing the PROM when downloading a new FPGA bitstream. 17. Click OK. 18. The iMPACT software indicates successful programming, as shown in Figure 12-18. The FPGA is configured with the new programming file.

Related Resources
Refer to the following links for additional information: Xilinx Parallel Cable IV with Flying Leads
www.xilinx.com/onlinestore/program_solutions.htm#pc

Digilent JTAG3 Programming Cable

www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Cables&Cat=Cable

Atmel AT45DB161D DataFlash Data Sheet www.atmel.com/dyn/resources/prod_documents/doc3500.pdf STMicroelectronics M25P16 SPI Serial Flash Data Sheet www.numonyx.com/Documents/Datasheets/M25P16.pdf Atmel SPI Serial Flash Programmer, via RS-232 (Reference Design) www.xilinx.com/products/boards/s3astarter/reference_designs.htm# atmel_spi_flash_programmer Universal Scan SPI Flash Programming via JTAG Training Video www.ricreations.com/JTAG-Software-Downloads.htm

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Chapter 13

DDR2 SDRAM
The Spartan-3A/3AN FPGA Starter Kit board includes a 512 Mbit (32M x 16) Micron Technology DDR2 SDRAM (MT47H32M16) with a 16-bit data interface, as shown in Figure 13-1.
5.0V 0.9V 1.8V 1.8V (SSTL_18 Reference Voltage) FPGA See Table (H7) (J1) (J8) VREF_3 (L8) (N1) (R6) (T1) (T6) VCCO_3 See Table See Table (M3) (M4) (N4) (E3) (J5) (K6) (J3) (K2) (K3) (M5) (N3) (M2) (M1) (P1) (H4) SD_LOOP
UG334_c13_01_052407

(SSTL_18 Termination Voltage) (DDR2 SDRAM Supply Voltage)

SW1 REG2 SW2 LDO2 National Semiconductor LP3906 Regulator

0.9V

SD_A<15:0> SD_DQ<15:0> SD_BA<2:0> SD_RAS SD_CAS SSTL_18 Termination SD_WE SD_UDM SD_UDQS_N SD_UDQS_P SD_LDM SD_LDQS_N SD_LDQS_P SD_CS SD_CKE SD_CK_N SD_CK_P SD_ODT

Micron 512Mb DDR2 SDRAM A[12:0] DQ[15:0] BA[1:0] RAS# CAS# WE# UDM UDQS# UDQS LDM LDQS# LDQS CS# CKE CK# CK ODT VREF VDD VDDQ

(H3)

Figure 13-1:

FPGA Interface to Micron 512 Mbit DDR2 SDRAM

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M T47H32M16 (32Mx16)

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All DDR2 SDRAM interface pins connect to the FPGAs I/O Bank 3 on the FPGA. I/O Bank 3 and the DDR2 SDRAM are both powered by 1.8V, supplied by a second National Semiconductor LP3906 regulator from the boards 5V supply input. The 0.9V reference voltage, common to the FPGA and DDR2 SDRAM, is also supplied by the National Semiconductor regulator. See Voltage Regulators in the Starter Kit Schematic. All DDR2 SDRAM interface signals are terminated. See DDR2 SDRAM Termination Network in the Starter Kit Schematic for information on the SSTL18 termination scheme used on the board.

DDR2 SDRAM Connections

Table 13-1 shows the connections between the FPGA and the DDR2 SDRAM. Also see 32Mx16 DDR2 SDRAM in the Starter Kit Schematic. Table 13-1:
Category

FPGA-to-DDR2 SDRAM Connections

DDR2 SDRAM Signal Name SD_A15 SD_A14 SD_A13 SD_A12 SD_A11 SD_A10 SD_A9 FPGA Pin Number W3 V4 V3 Y2 V1 T3 W2 W1 Y1 U1 U4 U2 U3 R1 T4 R2 Address inputs Function Unused on 512 Mbit DDR2 SDRAM device but provided for potential future upgrades

Address

SD_A8 SD_A7 SD_A6 SD_A5 SD_A4 SD_A3 SD_A2 SD_A1 SD_A0

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DDR2 SDRAM Connections

Table 13-1:
Category

FPGA-to-DDR2 SDRAM Connections (Continued)

DDR2 SDRAM Signal Name SD_DQ15 SD_DQ14 SD_DQ13 SD_DQ12 SD_DQ11 SD_DQ10 SD_DQ9 FPGA Pin Number F3 G3 F1 H5 H6 G1 G4 F2 H2 K4 L1 L5 L3 K1 K5 H1 P5 R3 P3 M3 M4 N4 M2 M1 N3 M5 E3 J3 J5 K6 K2 K3 Lower differential data strobe Upper differential data strobe Active-High clock enable input Active-Low chip select input Data Mask. Upper and Lower data masks. Differential clock input Command inputs Bank address inputs Function Data input/output. Outputs defined for compatibility with the Xilinx Memory Interface Generator (MIG) software.

Data

SD_DQ8 SD_DQ7 SD_DQ6 SD_DQ5 SD_DQ4 SD_DQ3 SD_DQ2 SD_DQ1 SD_DQ0 SD_BA2 SD_BA1 SD_BA0 SD_RAS SD_CAS SD_WE SD_CK_N

Control

SD_CK_P SD_CKE SD_CS SD_UDM SD_LDM SD_UDQS_N SD_UDQS_P SD_LDQS_N SD_LDQS_P

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Chapter 13: DDR2 SDRAM

Table 13-1:
Category Miscellaneous

FPGA-to-DDR2 SDRAM Connections (Continued)

DDR2 SDRAM Signal Name SD_LOOP_IN SD_LOOP_OUT SD_ODT FPGA Pin Number H4 H3 P1 Function I/O self-calibration loop. Direction can be reversed if more convenient in the FPGA application. DDR2 SDRAM on-device termination control

UCF Location Constraints

Address
Figure 13-2 provides the User Constraint File (UCF) constraints for the DDR2 SDRAM address pins, including the I/O pin assignment and the I/O standard used.
NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "SD_A<15>" "SD_A<14>" "SD_A<13>" "SD_A<12>" "SD_A<11>" "SD_A<10>" "SD_A<9>" "SD_A<8>" "SD_A<7>" "SD_A<6>" "SD_A<5>" "SD_A<4>" "SD_A<3>" "SD_A<2>" "SD_A<1>" "SD_A<0>" LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = "W3" "V4" "V3" "Y2" "V1" "T3" "W2" "W1" "Y1" "U1" "U4" "U2" "U3" "R1" "T4" "R2" | | | | | | | | | | | | | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = = = = = = = = = = = = = SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

Figure 13-2:

UCF Location Constraints for DDR2 SDRAM Address Inputs

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UCF Location Constraints

Data
Figure 13-3 provides the User Constraint File (UCF) constraints for the DDR2 SDRAM data pins, including the I/O pin assignment and I/O standard used.
NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "SD_DQ<15>" "SD_DQ<14>" "SD_DQ<13>" "SD_DQ<12>" "SD_DQ<11>" "SD_DQ<10>" "SD_DQ<9>" "SD_DQ<8>" "SD_DQ<7>" "SD_DQ<6>" "SD_DQ<5>" "SD_DQ<4>" "SD_DQ<3>" "SD_DQ<2>" "SD_DQ<1>" "SD_DQ<0>" LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = "F3" "G3" "F1" "H5" "H6" "G1" "G4" "F2" "H2" "K4" "L1" "L5" "L3" "K1" "K5" "H1" | | | | | | | | | | | | | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = = = = = = = = = = = = = SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

Figure 13-3:

UCF Location Constraints for DDR2 SDRAM Data I/O Pins

Control
Figure 13-4 provides the User Constraint File (UCF) constraints for the DDR2 SDRAM control pins, including the I/O pin assignment and the I/O standard used.
NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "SD_BA<2>" LOC = "SD_BA<1>" LOC = "SD_BA<0>" LOC = "SD_RAS" LOC = "SD_CAS" LOC = "SD_WE" LOC = "SD_CK_N" LOC = "SD_CK_P" LOC = "SD_CKE" LOC = "SD_CS" LOC = "SD_UDM" LOC = "SD_UDQS_N" LOC = "SD_UDQS_P" LOC = "SD_LDM" LOC = "SD_LDQS_N" LOC = "SD_LDQS_P" LOC = "SD_ODT" LOC = "SD_LOOP_IN" LOC "SD_LOOP_OUT" LOC "P5" | "R3" | "P3" | "M3" | "M4" | "N4" | "M2" | "M1" | "N3" | "M5" | "E3" | "J5" | "K6" | "J3" | "K2" | "K3" | "P1" | = "H4" = "H3" IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD = | IOSTANDARD | IOSTANDARD SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; SSTL18_II ; = SSTL18_II ; = SSTL18_II ;

Figure 13-4:

UCF Location Constraints for DDR2 SDRAM Control Pins

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Reserve FPGA VREF Pins

Five pins in I/O Bank 3 are dedicated as voltage reference inputs, VREF. These pins cannot be used for general-purpose I/Os in a design. Prohibit the software from using these pins with the constraints provided in Figure 13-5.
5i

# Prohibit VREF CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT

pins on FPGA I/O Bank 3 = H7; = J1; = J8; = L8; = N1; = R6; = T1; = T6;

Figure 13-5: UCF Location Constraints for FPGA VREF Pins

Special Layout Recommendations

The Xilinx Memory Interface Generator (MIG) tool, version 1.7 and later, generates DDR2 SDRAM interfaces for Spartan-3A and Spartan-3AN FPGAs. The MIG implementation leverages the FPGAs local clocking resources to capture the DDR2 SDRAM read data. Consequently, there is a close relationship between the memory data pins (SD_DQ<15:8>, SD_DQ_<7:0>) and their associated strobe signals. The MIG software automatically assigns pins based on this requirement and the Spartan-3A/3AN Starter Kit board is designed accordingly. The MIG core for Spartan-3A/3AN FPGAs includes a loopback signal to calibrate the read strobe timing. The loopback signal uses two FPGA pins, labeled SD_LOOP_IN and SD_LOOP_OUT. For best performance, the length of the loop back trace must be equal to the clock delay from the FPGA to the memory, plus the strobe delay from the memory back to the FPGA. Put another way, the loopback trace must be one round trip time to and from the memory. Also, the loopback signal should be in the center of the data interface pins for best results, not near the edge or in another FPGA I/O bank. The Spartan-3A/3AN Starter Kit board was designed accordingly. The Xilinx Memory Interface Generator (MIG) User Guide provides additional layout recommendations in Appendix A: Memory Implementation Guidelines. The board layout has been optimized for reaching frequencies above 133 MHz and 167 MHz. It can actually achieve the DDR400 performance level of 200 MHz or 400 Mbps per I/O, with an optimized memory interface controller. It is recommended to get the latest updates of the MIG tool that integrates the latest performance enhancements. Memory Interface Generator (MIG) www.xilinx.com/support/download/index.htm (now included with the CORE Generator system) UG086: Xilinx Memory Interface Generator (MIG) User Guide (included with MIG) XAPP458: Implementing DDR2-400 Memory Interfaces in Spartan-3A FPGAs www.xilinx.com/support/documentation/application_notes/xapp458.pdf

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Related Resources

Related Resources
Refer to the following links for additional information: Xilinx Embedded Development Kit (EDK) www.xilinx.com/ise/embedded_design_prod/platform_studio.htm MT47H32M16 (32M x 16) DDR2 SDRAM Data Sheet download.micron.com/pdf/datasheets/dram/ddr2/512MbDDR2.pdf Multi-Channel OPB DDR2 Controller Xilinx IP Core www.xilinx.com/support/documentation/ip_documentation/mch_opb_ddr2.pdf Memory Interface Generator (MIG), Version 1.7 or later www.xilinx.com/memory

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Chapter 14

10/100 Ethernet Physical Layer Interface

The Spartan-3A/3AN FPGA Starter Kit board includes a Standard Microsystems LAN8700 10/100 Ethernet physical layer (PHY) interface and an RJ-45 connector, as shown in Figure 14-1. With an Ethernet Media Access Controller (MAC) implemented in the FPGA, the board can optionally connect to a standard Ethernet network. All timing is controlled from an on-board 25 MHz crystal oscillator.

RJ-45 Ethernet Connector (J32) (integrated magnetics) SMSC LAN8700 10/100 Ethernet PHY

25 MHz Crystal
UG334_c14_01_052407

Figure 14-1: 10/100 Ethernet PHY with RJ-45 Connector

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Ethernet PHY Connections

The FPGA connects to the LAN8700 Ethernet PHY using a standard Media Independent Interface (MII), as shown in Figure 14-2. A more detailed description of the interface signals, including the FPGA pin number, appears in Table 14-1.
FPGA See Table (D8) (B2) (E11) See Table (H10) (G10) (C12) (H12) (G12) (D10) (E10) (D15) E_TXD<3:0> E_TX_EN E_TXD<4> E_TX_CLK E_RXD<3:0> E_RX_DV E_RXD<4> E_RX_CLK E_CRS E_COL E_MDC E_MDIO E_NRST SMSC LAN8700 10/100 Ethernet PHY TXD[3:0] TX_EN TXD4/TX_ER/nINIT TX_CLK RXD[3:0] RX_DV RXD4/RX_ER RX_CLK CRS/PHYAD4 COL_MII_CRS-DV MDC MDIO nRST
UG334_c14_02_052407

Connector (integrated magnetics)

RJ-45

25.000 MHz

Figure 14-2: Table 14-1:

FPGA Connects to Ethernet PHY via MII

FPGA Connections to the LAN83C185 Ethernet PHY

FPGA Pin Number B2 F7 E6 E7 F8 D8 E11 G10 H9 G9 G8 G7 Transmit Enable Transmit Clock. 25 MHz in 100Base-TX mode and 2.5 MHz in 10Base-T mode. Receive Data from the PHY Function Transmit Data to the PHY. E_TXD<4> is also the MII Transmit Error.

Signal Name E_TXD<4> E_TXD<3> E_TXD<2> E_TXD<1> E_TXD<0> E_TX_EN E_TX_CLK E_RXD<4> E_RXD<3> E_RXD<2> E_RXD<1> E_RXD<0>

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MicroBlaze Ethernet IP Cores

Table 14-1:

FPGA Connections to the LAN83C185 Ethernet PHY (Continued)

FPGA Pin Number H10 C12 H12 G12 D10 E10 D15 Receive Data Valid Receive Clock. 25 MHz in 100Base-TX mode and 2.5 MHz in 10Base-T mode. Carrier Sense MII Collision Detect Management Clock. Serial management clock. Management Data Input/Output Active-Low Reset Function

Signal Name E_RX_DV E_RX_CLK E_CRS E_COL E_MDC E_MDIO E_NRST

MicroBlaze Ethernet IP Cores

The Ethernet PHY is primarily intended for use with MicroBlaze applications. As such, an Ethernet MAC is part of the EDK Platform Studios Base System Builder. Both the full Ethernet MAC and the Lite version are available for evaluation. The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for applications that do not require support for interrupts, back-to-back data transfers, and statistics counters. The Ethernet MAC core requires design constraints to meet the required performance. Refer to the OPB Ethernet MAC data sheet (v1.02) for details. The OPB clock frequency must be 65 MHz or higher for 100 Mbps Ethernet operations and 6.5 MHz or faster for 10 Mbps Ethernet operations. The hardware evaluation versions of the Ethernet MAC cores operate for approximately eight hours in silicon before timing out. To order the full version of the core, visit the Xilinx website at: www.xilinx.com/products/ipcenter/OPB_10_100_Lite.htm

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UCF Location Constraints

Figure 14-3 provides the UCF constraints for the 10/100 Ethernet PHY interface, including the I/O pin assignment and the I/O standard used.
NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "E_COL" "E_CRS" "E_MDC" "E_MDIO" "E_NRST" "E_RX_CLK" "E_RX_DV" "E_RXD<0>" "E_RXD<1>" "E_RXD<2>" "E_RXD<3>" "E_RXD<4>" "E_TX_CLK" "E_TX_EN" "E_TXD<0>" "E_TXD<1>" "E_TXD<2>" "E_TXD<3>" LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = = = "G12" "H12" "D10" "E10" "D15" "C12" "H10" "G7" "G8" "G9" "H9" "G10" "E11" "D8" "F8" "E7" "E6" "F7" | | | | | | | | | | | | | | | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = = = = = = = = = = = = = = = LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 | | | | | ; ; | | | | ; ; | | | | | PULLDOWN ; PULLDOWN ; SLEW = SLOW SLEW = SLOW SLEW = SLOW

| DRIVE = 8; | DRIVE = 8; | DRIVE = 8;

PULLUP PULLUP PULLUP PULLUP

; ; ; ;

SLEW SLEW SLEW SLEW SLEW

= = = = =

FAST FAST FAST FAST FAST

| | | | |

DRIVE DRIVE DRIVE DRIVE DRIVE

= = = = =

8; 8; 8; 8; 8;

NET "E_TXD<4>" LOC = "B2" ;

| IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 | PULLUP

Figure 14-3: UCF Location Constraints for 10/100 Ethernet PHY Inputs

Related Resources
Refer to the following links for additional information: Standard Microsystems SMSC LAN8700 10/100 Ethernet PHY http://www.smsc.com/main/catalog/lan8700.html Xilinx OPB Ethernet Media Access Controller (EMAC) (v1.04a) www.xilinx.com/support/documentation/ip_documentation/opb_ethernet.pdf Xilinx OPB Ethernet Lite Media Access Controller (v1.01a) The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for applications the do not require support for interrupts, back-to-back data transfers, and statistics counters. www.xilinx.com/support/documentation/ip_documentation/opb_ethernetlite.pdf EDK Documentation http://www.xilinx.com/ise/embedded/edk_docs.htm

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Chapter 15

Expansion Connectors
The Spartan-3A/3AN FPGA Starter Kit board provides a variety of expansion connectors for easy interface flexibility to other off-board components. The board includes the I/O expansion headers shown in Figure 15-1. A Hirose 100-pin edge connector with 43 associated FPGA user-I/O pins Two stake pin headers, each that supports up to five differential data channels plus a differential clock or 12 single-ended I/O signals. Two six-pin Peripheral Module connections, plus mounting holes for a third module. Landing pads for an Agilent or Tektronix connectorless probe

Differential Receive Header, J2

6 differential pairs, high-performance Optionally, 12 single-ended I/O

Hirose 100-pin FX2 Connector, J17

43 I/O connections, high-performance

Connectorless Probe Landing Pads

For logic analyzer or oscilloscope

Differential Transmit Header, J15

6 differential pairs, high-performance Optionally, 12 single-ended I/O

6-pin Accessory Header, J19

Mounting holes only

6-pin Accessory Header, J20 6-pin Accessory Header, J18

UG334_c15_01_052407

Figure 15-1:

Expansion Headers

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Hirose 100-Pin FX2 Edge Connector (J17)

A 100-pin edge connector is located along the right edge of the board. This connector is a Hirose FX2-100P-1.27DS header with 1.27 mm pitch. Throughout the documentation, this connector is called the FX2 connector. As shown in Figure 15-2, 43 FPGA I/O pins interface to the FX2 connector.

FPGA
(See Table)

Hirose 100-pin Expansion Connector (J17)

FX2_IO<40:1> (See Table)

(M22) (L22) (L21)

FX2_CLKIN FX2_CLKOUT FX2_CLKIO VCCO_012 (3.3V) 5.0V GND

(B.46) (A.47) (B.48)

UG334_c15_02_052407

Figure 15-2:

FPGA Connections to the Hirose 100-Pin Edge Connector

Three signals are reserved primarily as clock signals between the board and FX2 connector, although all three connect to full I/O pins.

Expansion Connector Compatibility

For the majority of applications, the FX2 connector on the Spartan-3A/3AN Starter Kit board is compatible with the other Xilinx development boards. The Spartan-3E Starter Kit board and XC3S1600E Starter Kit board optionally provide limited differential I/O capability on the FX2 connector. The Spartan-3A/3AN Starter Kit board provides enhanced differential I/O support using the Differential I/O Connectors, page 124. Spartan-3E Starter Kit board www.xilinx.com/s3estarter XC3S1600E MicroBlaze Embedded Development Board www.xilinx.com/sp3e1600e

Furthermore, the Spartan-3A/3AN Starter Kit board supports the other FX2-Connector Compatible Boards, page 122.

Voltage Supplies to the Connector

The Spartan-3A/3AN Starter Kit board provides power to the Hirose 100-pin FX connector and any attached board via two supplies (see Figure 15-2). The 5.0V supply provides a voltage source for any 5V logic on the attached board or alternately provides power to any voltage regulators on the attached board.

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Hirose 100-Pin FX2 Edge Connector (J17)

A separate supply provides the same voltage as that applied to the FPGAs I/O Banks 0, 1, and 2 called VCCO_012. This supply is 3.3V by default. All FPGA I/Os that interface to the Hirose connector are in Bank 0 or Bank 1. For improved signal integrity, a majority of pins on the B side of the FX2 connector are tied to GND.

Connector Pinout and FPGA Connections

Table 15-1 shows the pinout for the Hirose 100-pin FX2 connector and the associated FPGA pin connections. The FX2 connect has two rows of connectors, both with 50 connections each, shown in the table using light yellow shading. The pin assignment for the connector is identical to that used on the Spartan-3E Starter Kit board, although the Spartan-3E board pinout includes a few input-only pins. The Spartan3A/3AN Starter Kit board pin assignment uses only full I/O pins and are backwards compatible with the Spartan-3E Starter Kit board.
a

Table 15-1:

Hirose 100-Pin FX2 Connector Pinout and FPGA Connections (J17)

Shared FX2 Connector A (top)
1 2 3 4 5 A13 B13 A14 B15 A15 A16 A17 B17 A18 C18 A19 B19 A20 B20 C19 D19 D18 E17 D20 D21 D22 E22 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Signal Name
Supply to FPGA I/O Banks 0, 1, 2 TMS_B JTSEL TDO_FX2 FX2_IO1 FX2_IO2 FX2_IO3 FX2_IO4 FX2_IO5 FX2_IO6 FX2_IO7 FX2_IO8 FX2_IO9 FX2_IO10 FX2_IO11 FX2_IO12 FX2_IO13 FX2_IO14 FX2_IO15 FX2_IO16 FX2_IO17 FX2_IO18 FX2_IO19 FX2_IO20 FX2_IO21 FX2_IO22

FPGA Pin
VCCO_012 VCCO_012

J34

B (bottom)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

FPGA Pin
GND

Signal Name
SHIELD GND TDO_XC2C TCK_B

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Table 15-1:

Hirose 100-Pin FX2 Connector Pinout and FPGA Connections (J17)

Shared FX2 Connector A (top)
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Signal Name
FX2_IO23 FX2_IO24 FX2_IO25 FX2_IO26 FX2_IO27 FX2_IO28 FX2_IO29 FX2_IO30 FX2_IO31 FX2_IO32 FX2_IO33 FX2_IO34 FX2_IO35 FX2_IO36 FX2_IO37 FX2_IO38 FX2_IO39 FX2_IO40 GND FX2_CLKOUT GND 5.0V 5.0V

FPGA Pin
F18 F19 F20 E20 G20 G19 H19 J18 K18 K17 K19 K20 L19 L18 M20 M18 L20 P20 GND L22 GND

J34

B (bottom)
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

FPGA Pin
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND M22 GND L21

Signal Name
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND FX2_CLKIN GND FX2_CLKIO 5.0V SHIELD

FX2-Connector Compatible Boards

The following boards are compatible with the FX2 connector on the starter kit board. Digilent FX2 Wirewrap Board (FX2WW) from Digilent, Inc. http://www.digilentinc.com/Products/Detail.cfm?Prod=FX2WW Digilent FX2 Breadboard (FX2BB) from Digilent, Inc. http://www.digilentinc.com/Products/Detail.cfm?Prod=FX2BB Video Decoder Board (VDEC1) from Digilent, Inc. http://www.digilentinc.com/Products/Detail.cfm?Prod=VDEC1

Mating Receptacle Connectors

The Spartan-3A/3AN Starter Kit board uses a Hirose FX2-100P-1.27DS header connector. The header mates with any compatible 100-pin receptacle connector, including boardmounted and non-locking cable connectors. Hirose connectors http://www.hirose-connectors.com/ FX2 Series Connector Data Sheet http://www.hirose.co.jp/cataloge_hp/e57220088.pdf

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Hirose 100-Pin FX2 Edge Connector (J17)

UCF Location Constraints

Figure 15-3 provides the UCF constraints for the FX2 connector, including the I/O pin assignment and the I/O standard used, assuming that all connections use single-ended I/O standards.
# ==== FX2 Connector NET "FX2_CLKIN" LOC NET "FX2_CLKIO" LOC NET "FX2_CLKOUT" LOC NET "FX2_IO<1>" LOC NET "FX2_IO<2>" LOC NET "FX2_IO<3>" LOC NET "FX2_IO<4>" LOC NET "FX2_IO<5>" LOC NET "FX2_IO<6>" LOC NET "FX2_IO<7>" LOC NET "FX2_IO<8>" LOC NET "FX2_IO<9>" LOC NET "FX2_IO<10>" LOC NET "FX2_IO<11>" LOC NET "FX2_IO<12>" LOC NET "FX2_IO<13>" LOC NET "FX2_IO<14>" LOC NET "FX2_IO<15>" LOC NET "FX2_IO<16>" LOC NET "FX2_IO<17>" LOC NET "FX2_IO<18>" LOC NET "FX2_IO<19>" LOC NET "FX2_IO<20>" LOC NET "FX2_IO<21>" LOC NET "FX2_IO<22>" LOC NET "FX2_IO<23>" LOC NET "FX2_IO<24>" LOC NET "FX2_IO<25>" LOC NET "FX2_IO<26>" LOC NET "FX2_IO<27>" LOC NET "FX2_IO<28>" LOC NET "FX2_IO<29>" LOC NET "FX2_IO<30>" LOC NET "FX2_IO<31>" LOC NET "FX2_IO<32>" LOC NET "FX2_IO<33>" LOC NET "FX2_IO<34>" LOC NET "FX2_IO<35>" LOC NET "FX2_IO<36>" LOC NET "FX2_IO<37>" LOC NET "FX2_IO<38>" LOC NET "FX2_IO<39>" LOC NET "FX2_IO<40>" LOC (FX2) ==== = "M22" | IOSTANDARD = LVCMOS33 ; = "L21" | IOSTANDARD = LVCMOS33 | SLEW = "L22" | IOSTANDARD = LVCMOS33 | SLEW = "A13" | IOSTANDARD = LVCMOS33 | SLEW = "B13" | IOSTANDARD = LVCMOS33 | SLEW = "A14" | IOSTANDARD = LVCMOS33 | SLEW = "B15" | IOSTANDARD = LVCMOS33 | SLEW = "A15" | IOSTANDARD = LVCMOS33 | SLEW = "A16" | IOSTANDARD = LVCMOS33 | SLEW = "A17" | IOSTANDARD = LVCMOS33 | SLEW = "B17" | IOSTANDARD = LVCMOS33 | SLEW = "A18" | IOSTANDARD = LVCMOS33 | SLEW = "C18" | IOSTANDARD = LVCMOS33 | SLEW = "A19" | IOSTANDARD = LVCMOS33 | SLEW = "B19" | IOSTANDARD = LVCMOS33 | SLEW = "A20" | IOSTANDARD = LVCMOS33 | SLEW = "B20" | IOSTANDARD = LVCMOS33 | SLEW = "C19" | IOSTANDARD = LVCMOS33 | SLEW = "D19" | IOSTANDARD = LVCMOS33 | SLEW = "D18" | IOSTANDARD = LVCMOS33 | SLEW = "E17" | IOSTANDARD = LVCMOS33 | SLEW = "D20" | IOSTANDARD = LVCMOS33 | SLEW = "D21" | IOSTANDARD = LVCMOS33 | SLEW = "D22" | IOSTANDARD = LVCMOS33 | SLEW = "E22" | IOSTANDARD = LVCMOS33 | SLEW = "F18" | IOSTANDARD = LVCMOS33 | SLEW = "F19" | IOSTANDARD = LVCMOS33 | SLEW = "F20" | IOSTANDARD = LVCMOS33 | SLEW = "E20" | IOSTANDARD = LVCMOS33 | SLEW = "G20" | IOSTANDARD = LVCMOS33 | SLEW = "G19" | IOSTANDARD = LVCMOS33 | SLEW = "H19" | IOSTANDARD = LVCMOS33 | SLEW = "J18" | IOSTANDARD = LVCMOS33 | SLEW = "K18" | IOSTANDARD = LVCMOS33 | SLEW = "K17" | IOSTANDARD = LVCMOS33 | SLEW = "K19" | IOSTANDARD = LVCMOS33 | SLEW = "K20" | IOSTANDARD = LVCMOS33 | SLEW = "L19" | IOSTANDARD = LVCMOS33 | SLEW = "L18" | IOSTANDARD = LVCMOS33 | SLEW = "M20" | IOSTANDARD = LVCMOS33 | SLEW = "M18" | IOSTANDARD = LVCMOS33 | SLEW = "L20" | IOSTANDARD = LVCMOS33 | SLEW = "P20" | IOSTANDARD = LVCMOS33 | SLEW

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST

| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

Figure 15-3:

UCF Location Constraints for 100-Pin Hirose FX2 Connector

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Differential I/O Connectors

The Spartan-3A/3AN Starter Kit board includes stake pin headers with excellent signal integrity and matched impedance traces to demonstrate high-performance differential I/O. Each differential pair supports approximately 600 Mbits per second (Mbps) data rates. All I/O pairs support differential input termination (DIFF_TERM) as described in the Spartan-3A and Spartan-3AN data sheets. The board is primarily designed to support loopback operations using a standard 34-pin socket-to-socket cable. The two differential I/O headers, shown in Figure 15-1, page 119, consist of a 2x17 array of stake pins arrange on 0.1-inch centers. The headers are not keyed. Ground pins are interspersed with the signal pins for improved signal integrity over any attached cable. Power is also supplied, via the nominally 3.3V rail, labeled VCCO_012. The power connectors are for potential daughter cards that plug into the connector. The J15 connector is primarily designed to transmit output data while the J2 connector is primarily designed to receive input data. However, both headers are equally good at transmitting differential data. The Receive header does have special provisions for capturing the receive clock input. The pin assignment for the J2 Receive connector appears in Table 15-2 and in Table 15-4. The FPGA ball assignment is listed in parentheses. Table 15-2:
2 4

Receive Header (J2)

6
RXN_0 (B4) RXP_0 (A4)

10
RXN_1 (A5) RXP_1 (B6)

12

14
RXN_2 (A6) RXP_2 (A7)

16

18

20

22
RXN_3 (A8) RXP_3 (A9)

24

26
RXN_4 (C10) RXP_4 (A10)

28

30
RX_ CLK_N (A11) RX_ CLK_P (A12)

32

34

GND GND GND GND

1 3

GND GND
7

GND GND
11

3.3V 3.3V 3.3V 3.3V 3.3V 3.3V

15 17 19

GND GND
23

GND GND
27

GND GND GND GND

31 33

13

21

25

29

The pin assignment for the J15 Transmit connector appears in Table 15-3 and in Table 15-4. The FPGA ball assignment is listed in parentheses. Table 15-3:
2 4

Transmit Header (J15)

6
TXN_0 (AA3) TXP_0 (AB2)

10
TXN_1 (AA4) TXP_1 (AB3)

12

14
TXN_2 (AB6) TXP_2 (AA6)

16

18

20

22
TXN_3 (AB7) TXP_3 (Y7)

24

26
TXN_4 (AB8) TXP_4 (AA8)

28

30
TX_ CLK_N (AB10) TX_ CLK_P (AA10)

32

34

GND GND GND GND

1 3

GND GND
7

GND GND
11

3.3V 3.3V 3.3V 3.3V 3.3V 3.3V

15 17 19

GND GND
23

GND GND
27

GND GND GND GND

31 33

13

21

25

29

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Differential I/O Connectors

Table 15-4 provides further detail on the pin assignment, including the differential pair association, the FPGA ball assignment, and the connecting header pin. Table 15-4: Differential I/O Connections and Header Connections
Signal Name FPGA Ball FPGA Pin Name Signal Direction Header.Pin

Differential Pair

Receive Header, J2 (Top Header) RX_<0> RX_<1> RX_<2> RX_<3> RX_<4> RXN_<0> RXP_<0> RXN_<1> RXP_<1> RXN_<2> RXP_<2> RXN_<3> RXP_<3> RXN_<4> RXP_<4> RX_CLK_N RX_CLK RX_CLK_P Transmit Header J15 (Bottom Header) TX_<0> TX_<1> TX_<2> TX_<3> TX_<4> TX_CLK TXN_<0> TXP_<0> TXN_<1> TXP_<1> TXN_<2> TXP_<2> TXN_<3> TXP_<3> TXN_<4> TXP_<4> TX_CLK_N TX_CLK_P AA3 AB2 AA4 AB3 AB6 AA6 AB7 Y7 AB8 AA8 AB10 AA10 IO_L03N_2 IO_L03P_2 IO_L04N_2 IO_L04P_2 IO_L08N_2 IO_L08P_2 IO_L10N_2 IO_L10P_2 IO_L12N_2 IO_L12P_2 IO_L15N_2 IO_L15P_2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O J1..6 J1.5 J1.10 J1.9 J1.14 J1.13 J1.22 J1.21 J1.26 J1.25 J1.30 J1.29 A12 B4 A4 A5 B6 A6 A7 A8 A9 C10 A10 A11 IO_L31N_0 IO_L31P_0 IO_L28N_0 IO_L28P_0 IO_L26N_0 IO_L26P_0 IO_L22N_0 IO_L22P_0 IO_L21N_0 IO_L21P_0 IO_L18N_0 GLK7 IO_L18P_0 GCLK8 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O J2.6 J2.5 J2.10 J2.9 J2.14 J2.13 J2.22 J2.21 J2.26 J2.25 J2.30 J2.29

Using Differential Inputs

LVDS and RSDS differential inputs require input termination. Two options are generally available. The first option is to use external termination resistors, as shown in Figure 15-4a. External input termination resistors are not provided on the differential I/O pins. The second option, called on-chip differential termination, is highlighted on the Spartan3A/3AN Starter Kit board (see Figure 15-4b). This feature uses the DIFF_TERM attribute available on differential I/O signals. Each differential I/O pin includes a circuit that

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behaves like an internal termination resistor of approximately 100 . On-chip differential termination is only available on full I/O pairs, not on Input-only pairs. Differential inputs are powered by the VCCAUX supply, which is 3.3V by default. Differential inputs are available in any I/O bank.
Pads for 100 surface-mount resistor FPGA IBUFDS or PAD BUFGDS Signal Differential termination (~100) FPGA IBUFDS or BUFGDS Signal

LxxP_0 LxxN_0

LxxP_0 LxxN_0

PAD

a) External 100 termination resistor

(not provided on the Starter Kit)

b) On-chip differential input termination

UG334_c15_04_052407

Figure 15-4:

Differential Input Termination Options

Using Differential Outputs

Differential inputs are supported within any I/O bank. However, with Spartan-3A and Spartan-3AN FPGAs, differential outputs are only supported on I/O Bank 0 or 2. Differential outputs are powered by the respective I/O bank output voltage, VCCO. On the Spartan-3A/3AN Starter Kit board, I/O Banks 0, 1, and 2 are all powered by a 3.3V supply.
I

FPGA OBUFDS Signal PAD LxxP_2 LxxN_2

UG330_c12_06_072706

Figure 15-5: Differential Outputs

Differential Trace Layout Considerations

Figure 15-6 shows board layout extracted from the Starter Kit board that highlights the differential I/O signal traces. These traces were routed for optimal signal integrity. All differential pairs are routed with matched 100 impedance on the top board layer for maximum performance. The traces were routed to avoid via where possible. The trace lengths for differential pairs routed to a specific header (either the Receive or Transmit header) were matched to within 0.25 inches. The differential signals connections on the FPGA use the outer two ball rings to avoid breakout congestion. The Receive differential clock pair, highlighted in blue in Figure 15-6, connects to a differential global clock input pair, GCLK7 and GCLK8. Using these global clock

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Differential I/O Connectors

inputs, the differential input is converted to a single-ended clock signal within the FPGA. This clock input then feeds the upper-right DCM, labeled as DCM_X2Y3.
If using for differential inputs, set the DIFF_TERM=TRUE constraint. There are no external termination resistors provided on the board.

Receive Header (J2)

2 1 34 33

All traces routed with 100 matched impedance. All receive pairs routed with matched trace lengths within 0.25 inches. Receive clock pair connects to global clock inputs GCLK7 and GCLK8 that feed the top-right DCM labeled DCM_X2Y3.
Bank 0

FPGA

Bank 2

All traces routed with 100 matched impedance. All transmit pairs routed with matched trace lengths within 0.25 inches.

2 1

34 33

Transmit Header (J15)

Figure 15-6: Differential I/O Layout

UG330_c12_15_012407

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34-Conductor Cable Assemblies (2x17)

The J2 and J15 headers were designed specifically to connect to 34-conductor flat ribbon cable assemblies that use a 2x17, 0.1-inch form factor. Table 15-5:
Distributor

Example 34-Conductor Cable Assemblies

Manufacturer 3M Distributor Part Number M3AAK-3420K-ND C3AAG-3406G-ND C3AAG-3406M-ND C3AAG-3418G-ND C3AAG-3418M-ND Type Flat ribbon cable, multi-color, twisted pair, gold finish Flat ribbon cable, gray, gold finish Flat ribbon cable, multi-color, gold finish Flat ribbon cable, gray, gold finish Flat ribbon cable, multi-color, gold finish Length 50.80 cm (20 inch) 15.24 cm (6 inch) 45.72 cm (18 inch)

Digi-Key
www.digikey.com

CW Industries

CW Industries

UCF Location Constraints

Figure 15-7 provides the User Constraint File (UCF) constraints for the Receive and Transmit headers, including the I/O pin assignment and the I/O standard used.
# High-Speed LVDS Receive NET "RX_CLK_N" LOC = "A11" NET "RX_CLK_P" LOC = "A12" NET "RX_N<0>" LOC = "B4" NET "RX_P<0>" LOC = "A4" NET "RX_N<1>" LOC = "A5" NET "RX_P<1>" LOC = "B6" NET "RX_N<2>" LOC = "A6" NET "RX_P<2>" LOC = "A7" NET "RX_N<3>" LOC = "A8" NET "RX_P<3>" LOC = "A9" NET "RX_N<4>" LOC = "C10" NET "RX_P<4>" LOC = "A10" Connector (RX) | IOSTANDARD = | IOSTANDARD = | IOSTANDARD = | IOSTANDARD = | IOSTANDARD = | IOSTANDARD = | IOSTANDARD = | IOSTANDARD = | IOSTANDARD = | IOSTANDARD = | IOSTANDARD = | IOSTANDARD = LVDS_33 LVDS_33 LVDS_33 LVDS_33 LVDS_33 LVDS_33 LVDS_33 LVDS_33 LVDS_33 LVDS_33 LVDS_33 LVDS_33 ; ; ; ; ; ; ; ; ; ; ; ;

# High-Speed LVDS Transmit Connector (TX) NET "TX_CLK_N" LOC = "AB10" | IOSTANDARD = LVDS_33 NET "TX_CLK_P" LOC = "AA10" | IOSTANDARD = LVDS_33 NET "TX_N<0>" LOC = "AA3" | IOSTANDARD = LVDS_33 NET "TX_P<0>" LOC = "AB2" | IOSTANDARD = LVDS_33 NET "TX_N<1>" LOC = "AA4" | IOSTANDARD = LVDS_33 NET "TX_P<1>" LOC = "AB3" | IOSTANDARD = LVDS_33 NET "TX_N<2>" LOC = "AB6" | IOSTANDARD = LVDS_33 NET "TX_P<2>" LOC = "AA6" | IOSTANDARD = LVDS_33 NET "TX_N<3>" LOC = "AB7" | IOSTANDARD = LVDS_33 NET "TX_P<3>" LOC = "Y7" | IOSTANDARD = LVDS_33 NET "TX_N<4>" LOC = "AB8" | IOSTANDARD = LVDS_33 NET "TX_P<4>" LOC = "AA8" | IOSTANDARD = LVDS_33

; ; ; ; ; ; ; ; ; ; ; ;

Figure 15-7: UCF Location Constraints for Receive and Transmit Headers

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Six-Pin Accessory Headers

Six-Pin Accessory Headers

The six-pin accessory headers provide easy I/O interface expansion using the various Digilent Peripheral Modules.

J18 Header
The J18 header, shown in Figure 15-8, is located in the bottom right corner of the board, along the right edge, adjacent to the BTN_EAST push button. It uses a female six-pin 90 socket. Four FPGA pins connect to the J18 header, J18_IO<4:1>. The board supplies 3.3V to the accessory board mounted in the J18 socket on the bottom pin.
FPGA (AA21) (AB21) (AA19) (AB19) J18_IO1 J18_IO2 J18_IO3 J18_IO4 GND 3.3V
UG334_c15_08_052407

J18

Figure 15-8:

FPGA Connections to the J18 Accessory Header

J19 Header
The J19 header, shown in Figure 15-9, is left unpopulated on the board. Four FPGA pins connect to the J19 header, J19_IO<4:1>. The board supplies 3.3V to the accessory board mounted in the J19 socket on the bottom pin.
FPGA (Y18) (W18) (V17) J19_IO1 J19_IO2 J19_IO3 J19

(W17) J19_IO4 GND 3.3V These pins connect to unpopulated mounting holes.
UG334_c15_09_052407

Figure 15-9:

FPGA Connections to the J19 Accessory Header

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J20 Header
The J20 header, shown in Figure 15-10, is the top-most six-pin connector along the right edge of the board. It uses a female six-pin 90 socket. Four FPGA pins connect to the J20 header, J20_IO<4:1>. The board supplies 3.3V to the accessory board mounted in the J20 socket on the bottom pin.
FPGA (V14) (V15) (W16) (V16) J20_IO1 J20_IO2 J20_IO3 J20_IO4 GND 3.3V
UG334_c15_10_052407

J20

Figure 15-10: FPGA Connections to the J20 Accessory Header

Digilent Peripheral Modules

Digilent Peripheral Modules (PMODs) are small I/O interface boards that offer an ideal way to extend the capabilities of programmable logic and embedded control boards. They allow sensitive signal conditioning circuits and high-power drive circuits to be placed where they are most effective - near sensors and actuators. PMODs communicate with system boards using six-wire cables that can carry up to four digital control signals, including SPI and other serial protocols. PMODs allow more effective design partitions by routing analog signals and power supplies only where they are needed and away from digital controller boards. Digilent, Inc. Peripheral Modules http://www.digilentinc.com/Products/Catalog.cfm?Cat=Peripheral

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Connectorless Debugging Port Landing Pads (J34)

UCF Location Constraints

Figure 15-11 provides the User Constraint File (UCF) constraints for the accessory headers, including the I/O pin assignment and the I/O standard used.
# ==== 6-pin header J18 ==== NET "J18_IO<1>" LOC = "AA21" NET "J18_IO<2>" LOC = "AB21" NET "J18_IO<3>" LOC = "AA19" NET "J18_IO<4>" LOC = "AB19" | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 | | | | SLEW SLEW SLEW SLEW = = = = SLOW SLOW SLOW SLOW | | | | DRIVE DRIVE DRIVE DRIVE = = = = 8 8 8 8 ; ; ; ;

# ==== 6-pin header J19 ==== # These four connections go to NET "J19_IO<1>" LOC = "Y18" | NET "J19_IO<2>" LOC = "W18" | NET "J19_IO<3>" LOC = "V17" | NET "J19_IO<4>" LOC = "W17" | # ==== 6-pin header J20 ==== NET "J20_IO<1>" LOC = "V14" NET "J20_IO<2>" LOC = "V15" NET "J20_IO<3>" LOC = "W16" NET "J20_IO<4>" LOC = "V16"

through-hole IOSTANDARD = IOSTANDARD = IOSTANDARD = IOSTANDARD =

pads, not to a connector. LVCMOS33 | SLEW = SLOW | LVCMOS33 | SLEW = SLOW | LVCMOS33 | SLEW = SLOW | LVCMOS33 | SLEW = SLOW |

DRIVE DRIVE DRIVE DRIVE

= = = =

8 8 8 8

; ; ; ;

| | | |

IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD

= = = =

LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33

| | | |

SLEW SLEW SLEW SLEW

= = = =

SLOW SLOW SLOW SLOW

| | | |

DRIVE DRIVE DRIVE DRIVE

= = = =

8 8 8 8

; ; ; ;

Figure 15-11:

UCF Location Constraints for Six-Pin Accessory Headers

Connectorless Debugging Port Landing Pads (J34)

Landing pads for a connectorless debugging port are provided as the J34 header. There is no physical connector on the board. Instead a connectorless probe, such as those available from Agilent, provides an interface to a logic analyzer. This debugging port is intended primarily for the Xilinx ChipScope Pro software with the Agilent FPGA Dynamic Probe. It can, however, be used with either the Agilent or Tektronix probes, without the ChipScope software, using FPGA Editors probe command. Xilinx ChipScope Pro Tool www.xilinx.com/ise/optional_prod/cspro.htm Agilent B4655A FPGA Dynamic Probe for Logic Analyzer www.home.agilent.com/agilent/redirector.jspx?action=ref&cname=PRODUCT &ckey=351182&lc=eng&cc=US Agilent 5404A/6A Pro Series Soft Touch Connector http://www.home.agilent.com/agilent/product.jspx?cc=US&lc=eng &pageMode=OV&pid=430362&ct=PRODUCT&id=430362 Tektronix P69xx Probe Modules with D-Max Technology www.tek.com/products/accessories/logic_analyzers/p6800_p6900.html

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Table 15-6 provides the connector pinout. Only 18 FPGA pins attach to the connector; the remaining connector pads are unconnected. All 18 FPGA pins are shared with the FX2 connector (J17). See Table 15-1, page 121 for more information on how these pins are shared. Table 15-6: Connectorless Debugging Port Landing Pads (J34)
FPGA Pin Connectorless Landing Pads FPGA Pin Signal Name

Signal Name

FX2_IO1 FX2_IO2 GND FX2_IO5 FX2_IO6 GND FX2_IO9 FX2_IO10 GND FX2_IO13 FX2_IO14 GND FX2_IO17 FX2_IO18

A13 B13 GND A15 A16 GND A18 C18 GND A20 B20 GND D18 E17

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14

A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14

B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27

GND A14 B15 GND A17 B17 GND A19 B19 GND C19 D19 GND

GND FX2_IO3 FX2_IO4 GND FX2_IO7 FX2_IO8 GND FX2_IO11 FX2_IO12 GND FX2_IO15 FX2_IO16 GND

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Chapter 16

Miniature Stereo Audio Jack

The Spartan-3A/3AN FPGA Starter Kit board includes a miniature stereo audio jack plug, as highlighted in Figure 16-1. The jack plug is located in the upper right corner of the board, immediately above the SUSPEND slide switch.

Stereo audio miniature jack (1/8, 3.5 mm) Connect headphones or amplified speakers 3.3V digital outputs

UG334_c16_01_052407

Figure 16-1:

Stereo Miniature Jack

Supported Audio Devices

The port provides simple audio tones to an attached set of headphones or to amplified speakers. The audio device must use a 1/8th-inch or 3.5 mm audio jack, as shown in Figure 16-2. A stereo connector is highly recommended. The FPGA signal definition appears in Table 16-1. A monophonic connector will function, but with the following limitations. Only drive signals on the AUD_L signal. Drive the AUD_R output to high-impedance (Hi-Z, threestate) so that it does not compete with the AUD_L channel.

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1/8 (3.5 mm)

1/4 (6.3 mm)

2.5 mm

(one insulator band) (left channel only)

Monophonic

Stereophonic
(two insulator bands)
UG330_c16_02_021507

Figure 16-2: Examples of Miniature Stereo Jacks

FPGA Connections
The FPGA drives a 3.3V digital signal to each side of the audio jack, as indicated in Table 16-1. A monophonic connector only uses the left-side channel Table 16-1: Digital Outputs to Stereo Minijack
FPGA Pins Y10 V10 Stereo Jack Left-side audio Right-side audio Mono Jack Audio channel Drive to Hi-Z

Signal Name AUD_L AUD_R

UCF Location Constraints

Figure 16-3 provides the UCF constraints for the audio connector.
# Controls VCCAUX supply rail (IC19) NET "AUD_L" LOC = "Y10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; NET "AUD_R" LOC = "V10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

Figure 16-3: UCF Constraints for Audio Connector

Related Resources
The demonstration design shipped with the board includes an audio example. Spartan-3A/3AN Starter Kit Demo Design Overview www.xilinx.com/products/boards/s3astarter/reference_designs.htm#demo Restoring the Out of the Box Flash Programming www.xilinx.com/products/boards/s3astarter/reference_designs.htm#out

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Chapter 17

Voltage Supplies
The voltage supplies are located in the upper left corner of the board, as shown in Figure 17-1.
AC wall adapter connector (5V DC) Through-hole option to power the board (5V DC)

Power control switch

ON

Power-on status LED

POWER J42 J41 POWER REG2_SCL REG2_SDA J40

OFF

LP3906 (IC18)

Supply to FPGA I/O Bank 3, DDR2 SDRAM

External I2C control input option to IC18

J13
J12
LP3906 (IC19)

Supply to FPGA core (VCCAUX)

External I2C control input option to IC19

J11
REG1_SCL REG1_SDA

Supply to FPGA I/O Banks 0, 1, 2

J10

J9 Supply to FPGA core (VCCINT)

UG330_cx_01_021507

Figure 17-1: Spartan-3A/3AN Starter Kit Board Voltage Supplies The Spartan-3A/3AN FPGA Starter Kit board requires a 5.0V DC voltage input, typically supplied by the AC wall adapter included with the kit. However, there is also a provision to connect the board directly to a 5.0V DC supply using through-hole mounting solder pads. The AC wall adapter must be a regulated 5.0V DC supply, as supplied with the kit. Some components and interfaces on the board, such as the LCD character display and the PS/2 port are powered directly from the 5.0V supply rail. Caution! Connect either the AC wall adapter OR use the through-hole mounting pads, but not
both.

The 5.0V input voltage is then converted to the other supply voltages required by the board components, as summarized in Table 17-1. All non-5V voltages are supplied by two space-efficient and cost-effective National Semiconductor LP3906 Quad-Output voltage

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Chapter 17: Voltage Supplies

regulators. Each regulator incorporates two high-current switching (buck) regulators and two low-drop out (LDO) linear regulators. Table 17-1: Voltage Regulators and Supply Rails
Regulator Output SW1 National Semiconductor LP3906 (IC19) LDO1 LDO2 SW1 National Semiconductor LP3906 (IC18) SW2 LDO1 3.3V 1.8V 0.9V 1.8V 3.3V 1.8V (voltage divided to 0.9V) J11 J12 J40 J13 J41 Voltage Level Series Jumper Control J9 Components Supplied FPGA internal core voltage, VCCINT FPGA I/O Banks 0, 1, and 2 (VCCO_0, VCCO_1, and VCCO_2). All 3.3V components. FPGA internal auxiliary voltage, VCCAUX Embedded USB programmer DDR2 SDRAM termination network DDR2 SDRAM component, FPGA I/O Bank 3 (VCCO_3) Voltage reference to D/A converter channels C and D. DDR2 SDRAM voltage reference, FPGA I/O Bank 3 VREF inputs (VREF_3)

Voltage Regulator

1.2V

SW2

3.3V

J10

LDO2

J42

The board exploits all four regulator outputs for testing and evaluation purposes. However, a typical Spartan-3A/3AN FPGA application uses far fewer rails. The board uses a separate supply for VCCAUX and sets it to 3.3V by default. In a typical application, the FPGAs VCCAUX supply could connect directly to the 3.3V supply used for FPGA I/O Banks 0, 1, and 2.

By default, the VCCAUX supply is set to 3.3V Using the I2C interface on regulator IC19, VCCAUX can be reduced to 2.5V to reduce overall power consumption or to verify operation with VCCAUX = 2.5V.

The DDR2 SDRAM interface uses multiple regulator outputs to test voltage margining.

One high-current 1.8V rail supports the DDR2 SDRAM component itself, and supplies the FPGAs I/O Bank 3, which connects to the DDR2 SDRAM. One high-current 0.9V supplies the DDR2 SDRAM termination network. A low-current 1.8V supply is voltage divided with resistors to provide a highaccuracy 0.9V voltage reference for the DDR2 SDRAM component and to supply the VREF inputs on FPGA I/O Bank 3. See Chapter 13, DDR2 SDRAM for additional information.

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Measuring Power Across Voltage Supply Jumpers

Measuring Power Across Voltage Supply Jumpers

All regulator output supplies have an associated series jumper, as indicated in Table 17-1 and shown in Figure 17-1. This allows for simple and easy current monitoring using just a multimeter. For example, to measure the Suspend mode current on the FPGAs VCCAUX or VCCINT supplies, follow these steps. Caution! The Suspend feature must first be enabled in the actual FPGA application. All the
example designs initially shipped with the board have the Suspend feature enabled.

Disconnect power to the board. Remove the series jumper associated with the supply to be measured, shown in Table 17-2. Locate jumper indicated in Figure 17-1. FPGA Supply Rails and Associated Voltage Supply Jumper
Associated Voltage Supply Jumper J9 J11 Default Voltage 1.2V 3.3V

Table 17-2:

FPGA Supply Rail VCCINT VCCAUX

Connect a digital multimeter across the jumper, as highlighted in Figure 17-2. If the resulting current is negative, simply reverse the connections to the jumpers.

Measured Current (mA)

VCCINT (1.2V) Set Current Range (Jumper J9) VCCAUX (3.3V) (200 mA DC) (Jumper J11)

UG330_c17_02_032207

Figure 17-2:

Measuring Current (Power) Using a Multimeter

Set the meter to measure DC Amperes. Initially set the meter to the Ampere range. If appropriate, switch to a lower range (for example, 200 mA) after initially measuring current in the Ampere range.

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Caution! If the meter offers various current ranges, always start with the largest range first.
Passing too large a current through a meter may damage it.

Reapply power to the board. Record the current measurements across the jumper. If the FPGA design supports the power-saving Suspend mode, measure the current with the SUSPEND switch (see SUSPEND Switch, page 26) set in both the RUN and SUSPEND positions. The default FPGA application shipped with the Starter Kit board does use the Suspend mode. For additional information on the Suspend mode, see the Power Management Solutions chapter in UG331: Spartan-3 Generation FPGA User Guide. Convert the current measurement (Amperes or mA) to a power measurement (Watts or mW), by multiplying the measured result by the supply voltage.

I2C Voltage Adjustment Interface

Each LP3906 regulator has an two-wire, I2C serial interface that optionally controls various functions, such as the regulator output voltage. As indicated in Table 17-3, the I2C interface can be controlled by the FPGA application using the I/O pins indicated or by some external controller using the through-hole mounting pads provided on the board, shown in Figure 17-1. Table 17-3: I2C Voltage Adjustment Interface to Regulator
I2C Control Input SCL IC18 SDA SCL IC19 SDA FPGA Connection REG2_SCL (D11) REG2_SDA (F13) REG1_SCL (E13) REG1_SDA (D13) Through-Hole Connection REG2-SCL REG2-SDA REG1-SCL REG1-SDA

Regulator

Possible Applications
For experimentation purposes only, Xilinx only recommends adjusting the two supplies listed below: By default, the VCCAUX supply to the FPGA is set to 3.3V, as required for Spartan-3AN FPGAs. On Spartan-3A FPGAs, VCCAUX can be either 2.5V or 3.3V, with potentially lower power consumption at 2.5V. Consequently, VCCAUX can be reduced to 2.5V by adjusting the LDO1 output on the LP3906 regulator designated IC19. The corresponding I2C control signals are REG1_SCL and REG1_SDA. By default, the reference voltage to Channels C and D on the D/A converter is 3.3V. However, this voltage can be adjusted to between 1.0V and 3.3V by controlling the LDO1 output on IC18. The corresponding I2C control signals are REG2_SCL and REG2_SDA. See Chapter 10, Digital-to-Analog Converter (DAC) for additional information.

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Related Resources

Restoring Default Voltages

Any voltage adjustments are temporary and apply only as long as the 5.0V supply is connected. To restore the original regulator output voltages, remove and then reconnect the 5.0V supply input. Caution! Simply toggling the power switch will not restore the original regulator output voltage!
Remove and reconnect the external 5.0V supply input.

UCF Location Constraints

Figure 17-3 provides the UCF constraints for the I2C control signals to the regulators.
# Controls VCCAUX supply rail (IC19) NET "REG1_SCL" LOC = "E13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; NET "REG1_SDA" LOC = "D13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; # Control D/A Converter reference voltage for Channels C and D (IC18) NET "REG2_SCL" LOC = "D11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; NET "REG2_SDA" LOC = "F13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

Figure 17-3:

UCF Constraints for Regulator I2C Control Signals

Related Resources
Refer to the following link for additional information: National Semiconductor LP3906 Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface www.national.com/pf/LP/LP3906.html

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