LAYER

L1P5 L1P5 L1P5

SECTION
L1P5 PHY testing L1P5 Error Injection - M-PHY related Cases L1P5 e_rr_or Injection Initialization Sequences L1P5 Reset Scenarios (LINE-RESET & Warm Reset) L1P5 Reset Scenarios (LINE-RESET & Warm Reset)

CATEGORY
COMPLIANCE COMPLIANCE COMPLIANCE

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5 L1P5 L1P5 L1P5

L1P5 INIT Sceanarios L1P5 PHY testing L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Reset Scenarios (LINE-RESET & Warm Reset) L1P5 Reset Scenarios (LINE-RESET & Warm Reset) L1P5 Reset Scenarios (LINE-RESET & Warm Reset) L1P5 Reset Scenarios (LINE-RESET & Warm Reset) L1P5 Reset Scenarios (LINE-RESET & Warm Reset) L1P5 Reset Scenarios (LINE-RESET & Warm Reset) L1P5 Reset Scenarios (LINE-RESET & Warm Reset)

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5

COMPLIANCE

L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5

COMPLIANCE

L1P5

L1P5 Reset Scenarios (LINE-RESET & Warm Reset)

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5 L1P5

L1P5 Low Power Scenarios L1P5 Low Power Scenarios

COMPLIANCE COMPLIANCE

L1P5 L1P5

L1P5 Low Power Scenarios L1P5 Low Power Scenarios

COMPLIANCE COMPLIANCE

L1P5 L1P5

L1P5 Low Power Scenarios L1P5 Low Power Scenarios

COMPLIANCE COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5 L1P5 L1P5 L1P5 L1P5

L1P5 PHY testing L1P5 Reset Scenarios (LINE-RESET & Warm Reset) L1P5 Reset Scenarios (LINE-RESET & Warm Reset) L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5 L1P5

COMPLIANCE RANDOM

L1P5

RANDOM

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5 L1P5

COMPLIANCE RANDOM

L1P5 L1P5

COMPLIANCE COMPLIANCE

L1P5

L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - Framing Errors L1P5 Error Injection - M-PHY related Cases L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences

COMPLIANCE

L1P5

COMPLIANCE

L1P5 L1P5

COMPLIANCE COMPLIANCE

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5

L1P5 INIT Sceanarios

NONE

L1P5

L1P5 INIT Sceanarios

COMPLIANCE

L1P5

L1P5 INIT Sceanarios

COMPLIANCE

L1P5

L1P5 INIT Sceanarios L1P5 Error Injection - Framing Errors

COMPLIANCE

L1P5

COMPLIANCE

L1P5 L1P5 L1P5 L1P5 L1P5

L1P5 Error Injection - Framing Errors L1P5 Reset Scenarios (LINE-RESET & Warm Reset) L1P5 Reset Scenarios (LINE-RESET & Warm Reset) L1P5 DME Access L1P5 DME Access

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5

L1P5 DME Access

COMPLIANCE

L1P5 L1P5 L1P5 L1P5

L1P5 DME Access L1P5 DME Access L1P5 DME Access L1P5 DME Access

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5 L1P5 L1P5 L1P5 L1P5

L1P5 DME Access L1P5 DME Access L1P5 DME Access L1P5 DME Access L1P5 DME Access

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5 L1P5

L1P5 DME Access L1P5 DME Access

COMPLIANCE COMPLIANCE

L1P5 L1P5

L1P5 DME Access L1P5 DME Access

COMPLIANCE COMPLIANCE

L1P5

L1P5 DME Access

COMPLIANCE

L1P5

L1P5 DME Access

COMPLIANCE

L1P5

L1P5 DME Access

COMPLIANCE

L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5

L1P5 DME Access L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5

L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5

L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers L1P5 Normal frame transfers

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5 L1P5

L1P5 PHY testing L1P5 INIT Sceanarios

COMPLIANCE COMPLIANCE

L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5

L1P5 INIT Sceanarios L1P5 INIT Sceanarios L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Error Injection - PACP Frame fields/Sequences

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5

L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Error Injection - PACP Frame fields/Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Error Injection - PACP Frame fields/Sequences L1P5 Error Injection - PACP Frame fields/Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE RANDOM COMPLIANCE COMPLIANCE

L1P5 L1P5

COMPLIANCE NONE

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5

COMPLIANCE

L1P5 L1P5

COMPLIANCE COMPLIANCE

L1P5 L1P5

L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences

COMPLIANCE COMPLIANCE

L1P5

COMPLIANCE

L1P5 L1P5 L1P5

COMPLIANCE COMPLIANCE COMPLIANCE

L1P5 L1P5 L1P5

COMPLIANCE COMPLIANCE COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5 L1P5 L1P5 L1P5

L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Low Power Scenarios

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5

L1P5 Low Power Scenarios

COMPLIANCE

L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5

L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Error Injection - Framing Errors L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 Low Power Scenarios

COMPLIANCE COMPLIANCE COMPLIANCE RANDOM RANDOM RANDOM RANDOM RANDOM

L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5 L1P5

L1P5 Low Power Scenarios L1P5 Low Power Scenarios L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 e_rr_or Injection Initialization Sequences L1P5 PHY testing L1P5 PHY testing L1P5 PHY testing L1P5 PHY testing L1P5 PHY testing L1P5 PHY testing L1P5 INIT Sceanarios L1P5 INIT Sceanarios

RANDOM RANDOM COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L1P5 L1P5

L1P5 INIT Sceanarios L1P5 INIT Sceanarios

COMPLIANCE COMPLIANCE

L1P5

L1P5 INIT Sceanarios

COMPLIANCE

L1P5

L1P5 INIT Sceanarios

COMPLIANCE

L1P5

L1P5 INIT Sceanarios

COMPLIANCE

L1P5

L1P5 INIT Sceanarios

COMPLIANCE

L1P5

L1P5 INIT Sceanarios

COMPLIANCE

L1P5

L1P5 INIT Sceanarios

COMPLIANCE

L1P5 L1P5 L1P5 L2 L2 L2 L2 L2 L2

L1P5 INIT Sceanarios L1P5 INIT Sceanarios L1P5 INIT Sceanarios L2 Init Hib and misc L2 Init Hib and misc L2 Init Hib and misc L2 Init Hib and misc L2 Init Hib and misc L2 Init Hib and misc

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2 L2

L2 Normal transfer L2 Error Injection

COMPLIANCE COMPLIANCE

L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Init Hib and misc L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE RANDOM RANDOM

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2 L2 L2 L2

L2 Error Injection L2 Init Hib and misc L2 Init Hib and misc L2 Error Injection

COMPLIANCE COMPLIANCE COMPLIANCE RANDOM

L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM COMPLIANCE RANDOM

L2 L2 L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Normal transfer L2 Normal transfer L2 Normal transfer

RANDOM RANDOM COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L2

L2 Init Hib and misc

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Init Hib and misc L2 Init Hib and misc

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L2

L2 Normal transfer

RANDOM

L2

L2 Normal transfer

RANDOM

L2 L2

L2 Normal transfer L2 Normal transfer

RANDOM RANDOM

L2 L2

L2 Normal transfer L2 Normal transfer

RANDOM RANDOM

L2

L2 Normal transfer

RANDOM

L2

L2 Normal transfer

RANDOM

L2

L2 Normal transfer

RANDOM

L2

L2 Normal transfer

RANDOM

L2

L2 Normal transfer

RANDOM

L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2

L2 Normal transfer L2 Normal transfer L2 Normal transfer L2 Normal transfer L2 Error Injection L2 Error Injection L2 Init Hib and misc L2 Error Injection L2 Init Hib and misc L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE RANDOM RANDOM COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L2

L2 Error Injection

RANDOM

L2 L2

L2 Error Injection L2 Error Injection

RANDOM COMPLIANCE

L2

L2 Error Injection

RANDOM

L2 L2

L2 Error Injection L2 Error Injection

RANDOM COMPLIANCE

L2

L2 Error Injection

RANDOM

L2

L2 Error Injection

RANDOM

L2 L2 L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM COMPLIANCE COMPLIANCE COMPLIANCE RANDOM RANDOM

L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM COMPLIANCE RANDOM COMPLIANCE RANDOM COMPLIANCE RANDOM RANDOM COMPLIANCE RANDOM COMPLIANCE RANDOM RANDOM COMPLIANCE COMPLIANCE RANDOM

L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM COMPLIANCE COMPLIANCE

L2

L2 Error Injection

RANDOM

L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM RANDOM COMPLIANCE COMPLIANCE

L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM RANDOM RANDOM

L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM RANDOM COMPLIANCE COMPLIANCE RANDOM RANDOM COMPLIANCE RANDOM COMPLIANCE RANDOM RANDOM COMPLIANCE COMPLIANCE RANDOM COMPLIANCE

L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM RANDOM COMPLIANCE

L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM RANDOM COMPLIANCE RANDOM COMPLIANCE COMPLIANCE RANDOM RANDOM COMPLIANCE COMPLIANCE RANDOM RANDOM

L2 L2 L2 L2 L2 L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM COMPLIANCE RANDOM COMPLIANCE RANDOM COMPLIANCE RANDOM RANDOM COMPLIANCE

L2 L2

L2 Error Injection L2 Error Injection

COMPLIANCE COMPLIANCE

L2

L2 Error Injection

RANDOM

L2 L2 L2 L2 L2 L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM COMPLIANCE RANDOM RANDOM COMPLIANCE COMPLIANCE RANDOM RANDOM COMPLIANCE

L2

L2 Error Injection

RANDOM

L2 L2 L2 L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM COMPLIANCE RANDOM COMPLIANCE COMPLIANCE RANDOM RANDOM

L2

L2 Error Injection

RANDOM

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

RANDOM

L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection

COMPLIANCE RANDOM COMPLIANCE

L2 L2

L2 Error Injection L2 Error Injection

RANDOM COMPLIANCE

L2 L2 L2 L2 L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

RANDOM RANDOM RANDOM COMPLIANCE RANDOM COMPLIANCE COMPLIANCE COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2 L2 L2 L2

L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection

COMPLIANCE RANDOM COMPLIANCE RANDOM

L2 L2

L2 Error Injection L2 Error Injection

COMPLIANCE COMPLIANCE

L2

L2 Error Injection

RANDOM

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

RANDOM

L2

L2 Error Injection

RANDOM

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

COMPLIANCE

L2

L2 Error Injection

RANDOM

L2

L2 Error Injection

RANDOM

L2

L2 Error Injection

RANDOM

L2

L2 Error Injection

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2

L2 Normal transfer

COMPLIANCE

L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2 L2

L2 Normal transfer L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Error Injection L2 Normal transfer

COMPLIANCE COMPLIANCE RANDOM COMPLIANCE RANDOM RANDOM RANDOM COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE RANDOM

L2 L3 L3 L3

L2 Normal transfer L3 Normal transfer L3 Normal transfer L3 Normal transfer

RANDOM RANDOM RANDOM RANDOM

L3

L3 Normal transfer

RANDOM

L3

L3 Normal transfer

RANDOM

L3

L3 Normal transfer

RANDOM

L3 L3 L3 L3 L3 L3 L3 L3 L4 L4 L4

L3 Normal transfer L3 Normal transfer L3 Normal transfer L3 Normal transfer L3 Error injection L3 Error injection L3 Error injection L3 Error injection CPort Connection mangement CPort Connection mangement CPort Connection mangement

RANDOM RANDOM RANDOM COMPLIANCE RANDOM COMPLIANCE RANDOM COMPLIANCE COMPLIANCE NONE NONE

L4

CPort Connection mangement

NONE

L4

L4 Normal transfer

RANDOM

L4

L4 Normal transfer

RANDOM

L4

L4 Normal transfer

RANDOM

L4 L4 L4 L4

L4 Normal transfer L4 Normal transfer L4 Normal transfer L4 Normal transfer

RANDOM RANDOM RANDOM RANDOM

L4

L4 Normal transfer

RANDOM

L4

L4 Normal transfer

COMPLIANCE

L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4

L4 Normal transfer L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Normal transfer L4 Normal transfer L4 Normal transfer L4 Normal transfer L4 Normal transfer L4 Error injection L4 Error injection L4 Error injection L4 Error injection

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

L4

L4 Error injection

COMPLIANCE

L4 L4

L4 Error injection L4 Error injection

COMPLIANCE COMPLIANCE

L4

L4 Error injection

COMPLIANCE

L4

L4 Normal transfer

RANDOM

L4

L4 Normal transfer

RANDOM

L4

L4 Normal transfer

RANDOM

L4

L4 Normal transfer

RANDOM

L4

L4 Normal transfer

RANDOM

L4

L4 Normal transfer

RANDOM

L4

L4 Normal transfer

RANDOM

L4

L4 Normal transfer

RANDOM

L4

L4 Normal transfer

RANDOM

L4 L4 L4 L4 L4 L4 L4 L4

L4 Normal transfer L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection

RANDOM COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE RANDOM RANDOM RANDOM

L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4 L4

L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection L4 Error injection

RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM RANDOM

L4

L4 Error injection

RANDOM

L4

L4 Error injection

RANDOM

L4

L4 Error injection

RANDOM

L4

L4 Error injection

RANDOM

L4

L4 Error injection

RANDOM

L4

L4 Error injection

RANDOM

L4 L4

L4 Error injection L4 Error injection

RANDOM RANDOM

L4 L4

L4 Error injection L4 Error injection

COMPLIANCE COMPLIANCE

L4

L4 Error injection

COMPLIANCE

L4

L4 Error injection

COMPLIANCE

L4

L4 Error injection

COMPLIANCE

L4

L4 Error injection

COMPLIANCE

L4

L4 Error injection

COMPLIANCE

L4

L4 Error injection

COMPLIANCE

L4

L4 Error injection

COMPLIANCE

L4 L4 L4 L4 L4 L4 L4 L4 DME

L4 Error injection L4 Test mode L4 Test mode L4 Test mode L4 Test mode L4 Test mode L4 Test mode L4 Test mode DME Interface Error Injection

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

DME

HIBERNATE and Attributes

COMPLIANCE

DME

ATTRIBUTE READ and WRITE tests

COMPLIANCE

DME DME DME DME DME

DME Interface Error Injection DME Interface Error Injection DME Interface Error Injection Overriding the RAL sequnces Overriding the RAL sequnces

COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE COMPLIANCE

DME

ATTRIBUTE READ and WRITE tests

COMPLIANCE

LOGNAME
compliance_l1p5_two_custom_power_mode_change_uvm.log compliance_normal_l1p5_bad_phy_symb_uvm.log compliance_pa_init_all_phase_trg_uprx_e_rr_or_and_recovery_uvm.log

compliance_l1p5_line_reset_bfm_hibernate_req_uvm.log

compliance_l1p5_line_reset_bfm_pacp_pwr_req_uvm.log

compliance_l1p5_bfm_not_start_linkstartup_dut_timeout_uvm.log compliance_l1p5_test_mode_initiated_by_bfm_uvm.log compliance_l1p5_deskew_insetion_multi_lane_uvm.log compliance_l1p5_deskew_insetion_single_lane_uvm.log compliance_l1p5_deskew_pattern_insetion_btwn_data_single_lane_uvm.lo g compliance_l1p5_insertion_of_dskew_pattern_on_multiple_lane_in_btwn_ data_dl_frame_uvm.log compliance_l1p5_init_abort_phase_1_warm_reset_uvm.log compliance_l1p5_init_abort_phase_0b_warm_reset_uvm.log compliance_l1p5_init_abort_phase_3_warm_reset_uvm.log compliance_l1p5_init_abort_phase_2_warm_reset_uvm.log compliance_l1p5_init_abort_phase_0_warm_reset_uvm.log compliance_l1p5_init_abort_phase_4_warm_reset_uvm.log

compliance_l1p5_line_reset_pacp_pwr_req_uvm.log

compliance_l1p5_line_reset_hibernate_req_uvm.log

compliance_l1p5_pacp_pwr_req_err_busy_success_response_uvm.log

compliance_l1p5_pacp_pwr_req_busy_err_success_response_uvm.log compliance_l1p5_pwr_mode_race_dut_reject_local_req_when_remote_req _is_in_process_uvm.log compliance_l1p5_pwr_mode_n_hibernate_race_dut_reject_local_req_when _remote_req_is_in_process_uvm.log compliance_l1p5_hibenate_race_dut_reject_local_req_when_remote_req_is _in_process_uvm.log compliance_l1p5_dut_reject_local_power_req_bfm_true_and_dut_true_uv m.log compliance_l1p5_dut_reject_local_and_remote_hibernate_req_bfm_false_a nd_dut_false_uvm.log compliance_l1p5_pwr_mode_race_bfm_req_reject_uvm.log compliance_l1p5_dut_reject_local_hibernate_req_bfm_true_and_dut_false_ uvm.log compliance_l1p5_hibenate_race_bfm_req_reject_uvm.log compliance_l1p5_dut_reject_local_power_req_bfm_true_and_dut_false_uv m.log compliance_l1p5_pwr_mode_n_hibernate_race_bfm_req_reject_uvm.log compliance_l1p5_dut_reject_local_hiberante_req_bfm_true_and_dut_true_ uvm.log compliance_l1p5_dut_reject_remote_hiberante_req_bfm_true_and_dut_tru e_uvm.log

compliance_l1p5_dut_reject_remote_hiberante_req_bfm_false_and_dut_tr ue_uvm.log compliance_l1p5_dut_reject_remote_power_req_bfm_true_and_dut_true_ uvm.log compliance_l1p5_dut_reject_remote_power_req_bfm_false_and_dut_true_ uvm.log

compliance_l1p5_dut_reject_local_invalid_power_req_uvm.log compliance_l1p5_ep_reset_from_bfm_uvm.log compliance_l1p5_ep_reset_from_dut_uvm.log compliance_l1p5_data_eob_corr_uvm.log compliance_l1p5_data_eob_dnc_corr_uvm.log

compliance_l1p5_data_eob_corr_pacp_uvm.log rand_l1p5_data_eob_dnc_corr_uvm.log

rand_l1p5_filler_corr_uvm.log

compliance_l1p5_filler_corr_pacp_uvm.log

compliance_l1p5_filler_corr_uvm.log

compliance_l1p5_filler_dnc_corr_uvm.log rand_l1p5_sob_dnc_corr_uvm.log

compliance_l1p5_data_sob_corr_pacp_uvm.log compliance_l1p5_data_sob_corr_dnc_uvm.log

compliance_l1p5_data_sob_corr_uvm.log

compliance_l1p5_data_sob_corr_during_init_tx_phase_0_uvm.log

compliance_l1p5_data_sob_corr_during_init_tx_phase_0B_uvm.log compliance_l1p5_res_err_inj_uvm.log

compliance_l1p5_init_abort_phase_3_hibern_uvm.log

compliance_l1p5_init_abort_phase_4_hibern_uvm.log

compliance_l1p5_init_abort_phase_1_hibern_uvm.log

compliance_l1p5_init_abort_phase_0b_hibern_uvm.log

compliance_l1p5_init_abort_phase_2_hibern_uvm.log

compliance_l1p5_init_abort_phase_0_hibern_uvm.log

random_lock_unlock_l1p5_init_phases_uvm.log

compliance_l1p5_init_start_dut_and_bfm_same_time_uvm.log

compliance_l1p5_link_start_bfm_end_after_por_uvm.log

compliance_l1p5_link_start_dut_end_after_por_uvm.log

compliance_l1p5_lane2lane_skew_gt_2_pa_symbols_pacp_frame_uvm.log

compliance_l1p5_lane2lane_skew_gt_2_pa_symbols_dl_frame_uvm.log compliance_l1p5_bfm_line_reset_pa_init_DL_uvm.log compliance_l1p5_dut_line_reset_pa_init_DL_uvm.log compliance_l1p5_lm_peer_get_with_cnf_dropped_once_uvm.log compliance_l1p5_lm_peer_set_with_cnf_dropped_once_uvm.log compliance_l1p5_lm_peer_set_e_rr_or_peer_communication_failure_uvm.l og compliance_l1p5_lm_peer_get_e_rr_or_peer_communication_failure_uvm.l og compliance_l1p5_lm_peer_get_with_cnf_dropped_twice_uvm.log compliance_l1p5_lm_peer_set_with_cnf_dropped_twice_uvm.log compliance_l1p5_lm_peer_get_e_rr_or_bad_index_uvm.log

compliance_l1p5_lm_peer_set_e_rr_or_read_only_mib_attribute_uvm.log compliance_l1p5_lm_peer_set_e_rr_or_locked_mib_attribute_uvm.log compliance_l1p5_lm_peer_set_e_rr_or_invalid_mib_attribute_uvm.log compliance_l1p5_lm_peer_get_e_rr_or_busy_uvm.log compliance_l1p5_lm_peer_set_e_rr_or_busy_uvm.log compliance_l1p5_lm_peer_set_e_rr_or_invalid_mib_attribute_value_uvm.lo g compliance_l1p5_lm_peer_set_e_rr_or_bad_index_uvm.log

compliance_l1p5_lm_peer_get_e_rr_or_write_only_mib_attribute_uvm.log compliance_l1p5_lm_peer_get_e_rr_or_invalid_mib_attribute_uvm.log

compliance_l1p5_lm_peer_get_dut_uvm.log

compliance_l1p5_lm_peer_set_bfm_uvm.log

compliance_l1p5_lm_peer_get_bfm_uvm.log

compliance_l1p5_lm_peer_set_dut_uvm.log compliance_l1p5_pacp_req_ls_to_hs_n_to_ls_both_bfm_uvm.log compliance_l1p5_pacp_req_ls_to_hs_n_to_ls_bfm_dut_uvm.log compliance_l1p5_pacp_req_ls_to_hs_n_to_ls_both_dut_uvm.log compliance_l1p5_pacp_req_ls_to_hs_n_to_ls_dut_bfm_uvm.log compliance_l1p5_pacp_not_complete_uvm.log compliance_l1p5_data_trfr_FAST_HS_G2_B_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G4_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G5_uvm.log compliance_l1p5_data_trfr_FAST_HS_G3_A_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G5_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G3_uvm.log compliance_l1p5_data_trfr_FAST_HS_G3_B_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G2_uvm.log compliance_l1p5_data_trfr_FAST_HS_G1_B_quick_uvm.log compliance_l1p5_data_trfr_FAST_AUTO_HS_G1_B_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G6_uvm.log

compliance_l1p5_data_trfr_SLOW_PWM_G3_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G7_uvm.log compliance_l1p5_data_trfr_fast_HS_G1_A_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G6_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G5_quick_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G4_uvm.log compliance_l1p5_data_trfr_FAST_AUTO_HS_G1_B_quick_uvm.log compliance_l1p5_data_trfr_FAST_HS_G1_B_uvm.log compliance_l1p5_data_trfr_FAST_AUTO_HS_G2_B_uvm.log compliance_l1p5_data_trfr_FAST_AUTO_HS_G2_A_uvm.log compliance_l1p5_data_trfr_FAST_AUTO_HS_G1_A_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G2_uvm.log compliance_l1p5_data_trfr_FAST_HS_G2_A_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G7_uvm.log compliance_l1p5_data_trfr_dut_2_connected_lanes_uvm.log compliance_l1p5_data_trfr_bfm_2_dut_1_uvm.log compliance_l1p5_data_trfr_dut_1_connected_lane_uvm.log compliance_l1p5_data_trfr_bfm_4_dut_3_uvm.log compliance_l1p5_data_trfr_bfm_1_dut_4_uvm.log compliance_l1p5_data_trfr_bfm_3_dut_3_uvm.log compliance_l1p5_data_trfr_bfm_3_dut_1_uvm.log compliance_l1p5_data_trfr_bfm_1_dut_1_uvm.log

compliance_l1p5_data_trfr_bfm_4_dut_4_uvm.log compliance_l1p5_data_trfr_bfm_3_dut_2_uvm.log compliance_l1p5_data_trfr_bfm_2_dut_4_uvm.log compliance_l1p5_data_trfr_bfm_1_dut_2_uvm.log compliance_l1p5_data_trfr_dut_3_connected_lanes_uvm.log compliance_l1p5_data_trfr_bfm_4_dut_2_uvm.log compliance_l1p5_data_trfr_bfm_3_dut_4_uvm.log compliance_l1p5_data_trfr_bfm_2_dut_3_uvm.log compliance_l1p5_data_trfr_bfm_2_dut_2_uvm.log compliance_l1p5_data_trfr_bfm_1_dut_3_uvm.log compliance_l1p5_data_trfr_bfm_4_dut_1_uvm.log compliance_l1p5_not_changing_pwr_mode_bit_long_duration_of_time_uv m.log compliance_dut_pa_init_nac_rrreq_set_uvm.log compliance_dut_pa_init_afcx_creq_set_during_initial_credit_exchange_uvm .log compliance_dut_pa_init_tcx_replay_uvm.log compliance_l1p5_hibern8_enter_from_dut_exit_from_bfm_uvm.log compliance_l1p5_hibern8_enter_from_dut_exit_from_dut_uvm.log compliance_l1p5_hibern8_enter_from_bfm_exit_from_bfm_uvm.log compliance_l1p5_hibern8_enter_from_bfm_exit_from_dut_uvm.log compliance_test_l1p5_pacp_set_cnf_crc_corruption_uvm.log compliance_test_l1p5_pacp_epr_ind_crc_corruption_uvm.log

compliance_test_l1p5_pacp_set_req_crc_corruption_uvm.log compliance_l1p5_pacp_crc_e_rr_or_pacp_req_to_dut_uvm.log compliance_test_l1p5_pacp_get_cnf_crc_corruption_uvm.log compliance_test_l1p5_pacp_get_req_crc_corruption_uvm.log compliance_l1p5_pacp_crc_e_rr_or_pacp_cnf_to_dut_uvm.log rand_l1p5_pacp_crc_e_rr_or_pacp_pwr_req_to_dut_uvm.log compliance_corr_l1p5_pacp_escparam_uvm.log compliance_l1p5_init_pacp_cap_e_rr_or_uvm.log compliance_l1p5_init_pacp_cap_e_rr_or_dut_linkstartup_timer_timeoutuv m.log normal_l1p5_pacp_cap_ind_corrupt_uvm.log

compliance_l1p5_pacp_get_cnf_corrupt_uvm.log

compliance_l1p5_pacp_set_cnf_corrupt_uvm.log compliance_l1p5_pacp_pwr_cnf_pwr_busy_or_e_rr_or_cap_from_bfm_for_ hib_req_uvm.log compliance_l1p5_pacp_pwr_cnf_pwr_busy_or_e_rr_or_cap_from_bfm_for_ power_change_req_uvm.log

compliance_pa_init_phase0_trg_upr0_e_rr_and_recovery_uvm.log compliance_pa_init_phase0_trg_upr0_wrong_lane_num_and_recovery_uvm .log compliance_pa_init_phase0_same_trg_upr0_on_more_than_one_lane_and _recovery_uvm.log compliance_pa_init_phase0_trg_upr0_e_rr_or_and_abort_uvm.log

compliance_pa_init_phase0b_same_trg_upr0_on_more_than_one_lane_an d_recovery_uvm.log compliance_pa_init_phase0b_trg_upr0_e_rr_or_and_recovery_uvm.log compliance_pa_init_phase0b_trg_upr0_wrong_lane_no_and_recovery_uvm. log

compliance_pa_init_phase1_trg_upr1_e_rr_or_and_recovery_uvm.log compliance_pa_init_phase1_trg_upr1_e_rr_or_and_abort_uvm.log compliance_pa_init_phase2_trg_upr1_e_rr_or_and_recovery_uvm.log

compliance_pa_init_phase3_trg_upr2_e_rr_or_and_recovery_uvm.log compliance_pa_init_phase3_trg_upr2_e_rr_or_and_abort_uvm.log compliance_pa_init_phase4_trg_upr2_e_rr_or_and_recovery_uvm.log compliance_l1p5_pwr_mode_pwr_f_a_t_a_l_e_rr_or_due_to_cnf_drop_uv m.log compliance_l1p5_pwr_mode_pwr_f_a_t_a_l_e_rr_or_for_hibernate_req_du e_to_pwr_cnf_error_or_busy_uvm.log compliance_l1p5_pwr_mode_pwr_f_a_t_a_l_e_rr_or_for_hibernate_req_du e_to_cnf_dropuvm.log compliance_l1p5_pwr_mode_pwr_f_a_t_a_l_e_rr_or_due_to_pwr_cnf_erro r_or_busy_uvm.log compliance_l1p5_pwr_mode_invalid_uvm.log compliance_l1p5_pwr_mode_eob_timeout_for_hibernate_req_uvm.log compliance_l1p5_pwr_mode_eob_timeout_uvm.log

compliance_l1p5_hibernate_pwr_cnf_drop_uvm.log

compliance_l1p5_pacp_pwr_req_pwr_cnf_drop_uvm.log compliance_l1p5_pwr_mode_with_user_data_uvm.log compliance_l1p5_random_symbols_before_sob_uvm.log rand_hibenate_entry_exit_uvm.log rand_mixed_pwr_mode_change_and_hibernate_entry_exit_req_uvm.log rand_pwr_mode_change_req_with_max_cap_quick_uvm.log rand_pwr_mode_change_req_with_max_cap_uvm.log rand_pwr_mode_change_req_quick_uvm.log rand_mixed_pwr_mode_change_and_hibernate_entry_exit_req_quick_uvm. log rand_pwr_mode_change_req_uvm.log compliance_pa_init_phase2_skip_uvm.log compliance_pa_init_phase0b_skip_uvm.log compliance_pa_init_phase3_skip_uvm.log compliance_pa_init_phase0_skip_uvm.log compliance_pa_init_phase1_skip_uvm.log compliance_pa_init_phase4_skip_uvm.log compliance_l1p5_phy_test_mode_local_cjtpat_seq_uvm.log compliance_l1p5_phy_test_mode_full_duplex_crpat_seq_uvm.log compliance_l1p5_phy_test_mode_peer_crpat_seq_uvm.log compliance_l1p5_phy_test_mode_peer_cjtpat_seq_uvm.log compliance_l1p5_phy_test_mode_full_duplex_cjtpat_seq_uvm.log compliance_l1p5_phy_test_mode_local_crpat_seq_uvm.log compliance_l1p5_init_bfm_init_restart_PH_1_uvm.log compliance_l1p5_init_bfm_init_restart_PH_3_uvm.log

compliance_l1p5_init_bfm_init_restart_PH_2_uvm.log compliance_l1p5_init_bfm_init_restart_PH_4_uvm.log compliance_pa_init_phase2_unexpected_phy_esc_symbol_and_recovery_uv m.log compliance_pa_init_phase1_unexpected_phy_esc_symbol_and_recovery_uv m.log compliance_pa_init_phase3_unexpected_phy_esc_symbol_and_recovery_uv m.log compliance_pa_init_phase0_unexpected_phy_esc_symbol_and_recovery_uv m.log compliance_pa_init_phase0b_unexpected_phy_esc_symbol_and_recovery_ uvm.log compliance_pa_init_phase4_unexpected_phy_esc_symbol_and_recovery_uv m.log

compliance_l1p5_init_start_inject_symbol_e_rr_or_uvm.log compliance_bfm_pa_lm_linkstartup_req_prog_uvm.log compliance_dut_pa_lm_linkstartup_req_prog_uvm.log compliance_tc0_afc_with_zero_credit_init_val_l2_uvm.log compliance_all_afc_with_zero_credit_init_val_l2_uvm.log compliance_tc0_afc_with_nonzero_valid_credit_init_val_l2_uvm.log compliance_tc1_afc_with_zero_credit_init_val_l2_uvm.log compliance_tc1_afc_with_nonzero_valid_credit_init_val_l2_uvm.log compliance_all_afc_with_nonzero_valid_credit_init_val_l2_uvm.log compliance_basic_dut_rx_preemption_tc0_data_frame_by_promoted_tc1_a fc_frame_l4_uvm.log compliance_basic_dut_tx_preemption_tc0_data_frame_by_promoted_tc1_a fc_frame_l4_uvm.log compliance_basic_dut_tx_preemption_tc0_data_frame_by_nac_frame_l4_u vm.log

compliance_basic_dut_tx_preemption_tc1_data_frame_by_nac_frame_l4_u vm.log compliance_basic_dut_tx_preemption_tc0_rtx_data_frame_by_tc1_afc_fra me_l4_uvm.log compliance_basic_dut_rx_preemption_tc1_data_frame_by_tc1_afc_frame_l 4_uvm.log compliance_basic_dut_rx_preemption_tc0_data_frame_by_promoted_tc0_a fc_frame_l4_uvm.log compliance_basic_dut_rx_preemption_tc0_data_frame_by_tc1_data_frame _l4_uvm.log compliance_basic_dut_tx_preemption_tc0_rtx_data_frame_by_promoted_t c1_afc_frame_l4_uvm.log compliance_basic_dut_tx_preemption_tc1_rtx_data_frame_by_tc1_afc_fra me_l4_uvm.log compliance_basic_dut_tx_preemption_tc1_rtx_data_frame_by_promoted_t c1_afc_frame_l4_uvm.log compliance_basic_dut_rx_preemption_tc1_data_frame_by_promoted_tc1_a fc_frame_l4_uvm.log compliance_basic_dut_tx_preemption_tc0_rtx_data_frame_by_tc1_data_fra me_l4_uvm.log compliance_basic_dut_tx_preemption_tc0_data_frame_by_tc1_afc_frame_l 4_uvm.log compliance_basic_dut_rx_preemption_tc0_data_frame_by_tc0_afc_frame_l 4_uvm.log compliance_basic_dut_tx_preemption_tc1_data_frame_by_tc1_afc_frame_l 4_uvm.log compliance_basic_dut_tx_preemption_tc0_rtx_data_frame_by_tc0_afc_fra me_l4_uvm.log

compliance_basic_dut_rx_preemption_tc0_data_frame_by_tc1_afc_frame_l 4_uvm.log compliance_basic_dut_rx_preemption_tc0_data_frame_by_nac_frame_l4_u vm.log compliance_basic_dut_tx_preemption_tc1_rtx_data_frame_by_promoted_t c0_afc_frame_l4_uvm.log compliance_basic_dut_tx_preemption_tc0_rtx_data_frame_by_promoted_t c0_afc_frame_l4_uvm.log compliance_basic_dut_tx_preemption_tc0_data_frame_by_promoted_tc0_a fc_frame_l4_uvm.log compliance_basic_dut_rx_preemption_tc1_data_frame_by_nac_frame_l4_u vm.log compliance_basic_dut_tx_preemption_tc0_rtx_data_frame_by_nac_frame_l 4_uvm.log compliance_basic_dut_tx_preemption_tc0_data_frame_by_tc1_data_frame _l4_uvm.log compliance_basic_dut_tx_preemption_tc1_rtx_data_frame_by_nac_frame_l 4_uvm.log compliance_basic_dut_rx_preemption_tc1_data_frame_by_promoted_tc0_a fc_frame_l4_uvm.log compliance_basic_dut_tx_preemption_tc1_data_frame_by_promoted_tc0_a fc_frame_l4_uvm.log compliance_basic_dut_tx_preemption_tc0_data_frame_by_tc0_afc_frame_l 4_uvm.log compliance_basic_dut_tx_preemption_tc1_data_frame_by_promoted_tc1_a fc_frame_l4_uvm.log compliance_cause_afcx_transmission_by_credit_diff_gt_threshold_l4_uvm.l og compliance_afc1_request_timer_l4_uvm.log

compliance_afc0_request_timer_l4_uvm.log compliance_afc0_afc1_request_timer_l4_uvm.log compliance_multiple_time_fc1_protection_timer_timeout_l4_uvm.log compliance_multiple_time_fc0_protection_timer_timeout_l4_uvm.log compliance_single_time_fc1_fc0_protection_timer_timeout_l4_uvm.log compliance_single_time_fc0_protection_timer_timeout_l4_uvm.log compliance_single_time_fc1_protection_timer_timeout_l4_uvm.log compliance_tc1_replay_timer_timeout_l4_uvm.log compliance_tc0_replay_timer_timeout_l4_uvm.log compliance_phy_init_failure_l2_uvm.log compliance_dut_rx_overflow_by_corrupting_tc1_sof_l4_uvm.log compliance_dut_rx_overflow_by_corrupting_tc0_sof_l4_uvm.log rand_dut_rx_overflow_with_ack_grouping_l4_uvm.log rand_dut_rx_overflow_wo_ack_grouping_l4_uvm.log compliance_replayed_low_priority_frame_pre_empted_by_non_replayed_h igh_priority_frame_l4_uvm.log

compliance_successive_e_rr_on_tc0_data_frames_single_nac_l4_uvm.log

compliance_successive_e_rr_on_tc1_data_frames_single_nac_l4_uvm.log compliance_changing_dut_link_prop_during_one_data_frame_in_progress_ w_no_afcx_req_timer_running_l4_uvm.log compliance_changing_bfm_link_prop_during_one_data_frame_in_progress _w_afcx_req_timer_running_l4_uvm.log compliance_changing_dut_link_prop_during_one_data_frame_in_progress_ w_afcx_req_timer_running_l4_uvm.log

compliance_changing_bfm_link_prop_during_one_data_frame_in_progress _w_no_afcx_req_timer_running_l4_uvm.log compliance_changing_bfm_link_prop_during_afc0_req_timer_running_l4_u vm.log compliance_changing_bfm_link_prop_during_afc0_afc1_req_timers_running _l4_uvm.log compliance_changing_dut_link_prop_during_afc0_req_timer_running_l4_uv m.log compliance_changing_bfm_link_prop_during_afc1_req_timer_running_l4_u vm.log compliance_changing_dut_link_prop_during_afc0_afc1_req_timers_running _l4_uvm.log compliance_changing_dut_link_prop_during_afc1_req_timer_running_l4_uv m.log compliance_changing_bfm_link_prop_during_preemption_in_progress_w_a fcx_req_timer_running_l4_uvm.log compliance_changing_dut_link_prop_during_preemption_in_progress_w_n o_afcx_req_timer_running_l4_uvm.log compliance_changing_bfm_link_prop_during_preemption_in_progress_w_n o_afcx_req_timer_running_l4_uvm.log compliance_changing_dut_link_prop_during_preemption_in_progress_w_af cx_req_timer_running_l4_uvm.log compliance_changing_bfm_link_prop_during_no_pending_frames_l4_uvm.l og compliance_changing_dut_link_prop_during_no_pending_frames_l4_uvm.lo g compliance_lm_hibernate_l2.log compliance_lm_reset_l2.log rand_drop_afc_rx_data_frame_with_ack_grouping_l4_uvm.log

rand_drop_afc_rx_data_frame_wo_ack_grouping_l4_uvm.log compliance_duplicate_afc1_l4_uvm.log rand_afc_frame_duplication_corrupt_wo_ack_grouping_l4_uvm.log

rand_afc_frame_duplication_corrupt_with_ack_grouping_l4_quick_uvm.log rand_afc_frame_duplication_corrupt_with_ack_grouping_l4_uvm.log compliance_duplicate_afc0_l4_uvm.log compliance_dut_tc1_ack_grouping_mechanism_l4_uvm.log compliance_dut_tc0_tc1_ack_grouping_mechanism_l4_uvm.log compliance_dut_tc0_ack_grouping_mechanism_l4_uvm.log

compliance_fcx_protection_timer_timeout_init_l2_uvm.log

compliance_illegal_preemption_nac_frame_by_tc1_afc_frame_l4_uvm.log compliance_illegal_preemption_tc1_data_frame_by_tc0_data_frame_l4_uv m.log compliance_illegal_preemption_tc0_afc_frame_by_tc1_afc_frame_l4_uvm.l og compliance_illegal_preemption_tc1_data_frame_by_tc1_data_frame_l4_uv m.log

compliance_illegal_preemption_tc1_afc_frame_by_nac_frame_l4_uvm.log

compliance_illegal_preemption_nac_frame_by_tc0_afc_frame_l4_uvm.log

compliance_illegal_preemption_nac_frame_by_tc1_data_frame_l4_uvm.log compliance_illegal_preemption_tc1_afc_frame_by_tc1_data_frame_l4_uvm. log

compliance_illegal_preemption_tc1_afc_frame_by_tc0_afc_frame_l4_uvm.l og compliance_illegal_preemption_tc0_data_frame_by_tc0_data_frame_l4_uv m.log

compliance_illegal_preemption_nac_frame_by_tc0_data_frame_l4_uvm.log compliance_illegal_preemption_tc0_afc_frame_by_tc0_afc_frame_l4_uvm.l og compliance_illegal_preemption_tc0_afc_frame_by_tc1_data_frame_l4_uvm. log compliance_illegal_preemption_tc0_afc_frame_by_tc0_data_frame_l4_uvm. log

compliance_illegal_preemption_tc0_afc_frame_by_nac_frame_l4_uvm.log compliance_illegal_preemption_tc1_afc_frame_by_tc0_data_frame_l4_uvm. log compliance_illegal_preemption_tc1_afc_frame_by_tc1_afc_frame_l4_uvm.l og compliance_illegal_preemption_nac_frame_by_nac_frame_l4_uvm.log compliance_multilevel_preemption_corrupt_tc0_cof_l4_uvm.log compliance_multilevel_preemption_corrupt_tc1_cof_l4_uvm.log

rand_real_normal_frame_tx_rx_tc0_tc1_ack_grouping_l4_uvm.log

rand_full_msg_normal_frame_tx_rx_tc0_ack_grouping_l4_uvm.log

rand_full_msg_normal_frame_tx_rx_tc1_ack_grouping_l4_uvm.log rand_basic_normal_msg_rx_tc0_tc1_uvm.log

rand_basic_normal_msg_rx_tc0_uvm.log rand_basic_normal_msg_rx_tc1_uvm.log rand_basic_normal_msg_tx_rx_tc0_with_preemption_wo_ack_grouping_uv m.log rand_basic_normal_msg_tx_rx_tc1_wo_preemption_wo_ack_grouping_uvm .log rand_basic_normal_msg_tx_rx_tc0_tc1_with_preemption_wo_ack_grouping _uvm.log rand_basic_normal_msg_tx_rx_tc0_tc1_wo_preemption_wo_ack_grouping_ uvm.log rand_basic_normal_msg_tx_rx_tc1_with_preemption_wo_ack_grouping_uv m.log rand_basic_normal_msg_tx_rx_tc0_wo_preemption_wo_ack_grouping_uvm .log rand_basic_normal_msg_tx_tc0_uvm.log rand_basic_normal_msg_tx_tc0_tc1_uvm.log rand_basic_normal_msg_tx_tc1_uvm.log rand_e_r_r_injection_at_l2_layer_with_ack_grouping_l4_uvm.log rand_e_r_r_injection_at_l2_layer_wo_ack_grouping_l4_uvm.log compliance_nac_rreq_reception_init_l2.log compliance_dut_pa_e_rr_or_ind_l2.log compliance_scenario_leading_to_phy_init_l2.log compliance_afc0_frame_corrupt_rsvd_bits_l4_uvm.log rand_afc_frame_corrupt_rsvd_bits_wo_ack_grouping_l4_uvm.log rand_afc_frame_corrupt_rsvd_bits_with_ack_grouping_l4_uvm.log compliance_afc1_frame_corrupt_rsvd_bits_l4_uvm.log

compliance_afc0_data_frame_rtx_in_progress_l4_uvm.log

compliance_afc1_data_frame_rtx_in_progress_l4_uvm.log compliance_tx_cof_cs_before_tc0_data_frame_started_l4_uvm.log compliance_tx_eof_odd_cs_before_tc1_data_frame_started_l4_uvm.log compliance_tx_eof_even_cs_before_tc0_data_frame_started_l4_uvm.log rand_tx_eof_even_cs_before_data_frame_started_with_ack_grouping_l4_u vm.log rand_tx_eof_even_cs_before_data_frame_started_wo_ack_grouping_l4_uv m.log compliance_tx_eof_even_cs_before_tc1_data_frame_started_l4_uvm.log rand_tx_eof_odd_cs_before_data_frame_started_wo_ack_grouping_l4_uvm .log

rand_tx_cof_cs_before_data_frame_started_wo_ack_grouping_l4_uvm.log compliance_tx_eof_odd_cs_before_tc0_data_frame_started_l4_uvm.log

rand_tx_cof_cs_before_data_frame_started_with_ack_grouping_l4_uvm.log rand_tx_cof_cs_before_data_frame_started_wo_ack_grouping_l4_quick_uv m.log rand_tx_eof_odd_cs_before_data_frame_started_with_ack_grouping_l4_uv m.log compliance_tx_cof_cs_before_tc1_data_frame_started_l4_uvm.log compliance_cof_of_tc1_data_frame_continue_diff_tc_l4_uvm.log compliance_cof_of_tc0_data_frame_continue_diff_tc_l4_uvm.log rand_cof_continue_diff_tc_wo_ack_grouping_l4_uvm.log rand_cof_continue_diff_tc_with_ack_grouping_l4_uvm.log

rand_cof_wo_pre_emption_wo_ack_grouping_l4_uvm.log compliance_cof_wo_pre_emption_on_tc1_data_frame_l4_uvm.log rand_cof_wo_pre_emption_with_ack_grouping_l4_uvm.log compliance_cof_wo_pre_emption_on_tc0_data_frame_l4_uvm.log rand_ctrl_nac_frame_crc_corrupt_wo_ack_grouping_l4_uvm.log compliance_nac_crc_corrupt_l4_uvm.log rand_ctrl_nac_frame_crc_corrupt_with_ack_grouping_l4_uvm.log rand_ctrl_afc_frame_crc_corrupt_with_ack_grouping_l4_uvm.log compliance_afc0_crc_corrupt_l4_uvm.log rand_ctrl_afc_frame_crc_corrupt_wo_ack_grouping_l4_uvm.log compliance_afc1_crc_corrupt_l4_uvm.log rand_l2_afc_ctrl_sym_identifier_corrupt_wo_ack_grouping_l4_uvm.log rand_l2_sof_ctrl_sym_identifier_corrupt_with_ack_grouping_l4_uvm.log compliance_l2_nac_ctrl_sym_identifier_corrupt_l4_uvm.log compliance_l2_eof_even_ctrl_sym_identifier_corrupt_l4_uvm.log rand_l2_nac_ctrl_sym_identifier_corrupt_with_ack_grouping_l4_uvm.log rand_l2_eof_even_ctrl_sym_identifier_corrupt_with_ack_grouping_l4_uvm.l og compliance_l2_sof_ctrl_sym_identifier_corrupt_l4_uvm.log compliance_l2_afc_ctrl_sym_identifier_corrupt_l4_uvm.log rand_l2_eof_odd_ctrl_sym_identifier_corrupt_with_ack_grouping_l4_uvm.l og rand_l2_eof_even_ctrl_sym_identifier_corrupt_wo_ack_grouping_l4_uvm.lo g rand_l2_cof_ctrl_sym_identifier_corrupt_with_ack_grouping_l4_uvm.log compliance_l2_eof_odd_ctrl_sym_identifier_corrupt_l4_uvm.log compliance_l2_cof_ctrl_sym_identifier_corrupt_l4_uvm.log

rand_l2_cof_ctrl_sym_identifier_corrupt_wo_ack_grouping_l4_uvm.log rand_l2_afc_ctrl_sym_identifier_corrupt_with_ack_grouping_l4_uvm.log rand_l2_nac_ctrl_sym_identifier_corrupt_wo_ack_grouping_l4_uvm.log

rand_l2_eof_odd_ctrl_sym_identifier_corrupt_wo_ack_grouping_l4_uvm.log rand_l2_sof_ctrl_sym_identifier_corrupt_wo_ack_grouping_l4_uvm.log compliance_cof_tc1_corrupt_to_rsvd_tcx_l4_uvm.log compliance_cof_tc0_corrupt_to_rsvd_tcx_l4_uvm.log rand_sof_tc_corrupt_to_rsvd_tcx_with_ack_grouping_l4_uvm.log rand_afc_tc_corrupt_to_rsvd_tcx_wo_ack_grouping_l4_uvm.log compliance_afc_tc1_corrupt_to_rsvd_tcx_l4_uvm.log rand_sof_tc_corrupt_to_rsvd_tcx_wo_ack_grouping_l4_uvm.log compliance_afc_tc0_corrupt_to_rsvd_tcx_l4_uvm.log rand_afc_tc_corrupt_to_rsvd_tcx_with_ack_grouping_l4_uvm.log rand_cof_tc_corrupt_to_rsvd_tcx_wo_ack_grouping_l4_uvm.log compliance_sof_tc0_corrupt_to_rsvd_tcx_l4_uvm.log compliance_sof_tc1_corrupt_to_rsvd_tcx_l4_uvm.log rand_cof_tc_corrupt_to_rsvd_tcx_with_ack_grouping_l4_uvm.log compliance_tc1_eof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log rand_sof_corrupt_to_rsvd_ctrl_sym_type_wo_ack_grouping_l4_quick_uvm.l og rand_afc_corrupt_to_rsvd_ctrl_sym_type_with_ack_grouping_l4_uvm.log compliance_afc1_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log

rand_eof_corrupt_to_rsvd_ctrl_sym_type_wo_ack_grouping_l4_uvm.log rand_sof_corrupt_to_rsvd_ctrl_sym_type_with_ack_grouping_l4_uvm.log compliance_tc1_cof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log rand_cof_corrupt_to_rsvd_ctrl_sym_type_with_ack_grouping_l4_uvm.log compliance_tc0_cof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log compliance_afc0_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log rand_eof_corrupt_to_rsvd_ctrl_sym_type_with_ack_grouping_l4_uvm.log rand_cof_corrupt_to_rsvd_ctrl_sym_type_wo_ack_grouping_l4_uvm.log compliance_tc0_sof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log compliance_tc0_eof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log rand_afc_corrupt_to_rsvd_ctrl_sym_type_wo_ack_grouping_l4_uvm.log rand_sof_corrupt_to_rsvd_ctrl_sym_type_wo_ack_grouping_l4_uvm.log rand_cof_corrupt_to_rsvd_ctrl_sym_type_with_ack_grouping_l4_quick_uvm .log compliance_tc1_sof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log rand_cof_ctrl_sym_corrupt_rsvd_bits_wo_ack_grouping_l4_uvm.log compliance_tc1_cof_ctrl_sym_corrupt_rsvd_bits_l4_uvm.log rand_data_frame_corrupt_rsvd_bits_with_ack_grouping_l4_uvm.log compliance_tc0_cof_ctrl_sym_corrupt_rsvd_bits_l4_uvm.log rand_data_frame_corrupt_rsvd_bits_wo_ack_grouping_l4_uvm.log rand_cof_ctrl_sym_corrupt_rsvd_bits_with_ack_grouping_l4_uvm.log compliance_tc0_data_frame_corrupt_rsvd_bits_l4_uvm.log

compliance_tc1_data_frame_corrupt_rsvd_bits_l4_uvm.log compliance_tc0_data_frame_payload_corrupt_gt_dl_mtu_l4_uvm.log rand_data_frame_payload_corrupt_gt_dl_mtu_with_ack_grouping_l4_uvm.l og rand_data_frame_payload_corrupt_gt_dl_mtu_wo_ack_grouping_l4_uvm.lo g compliance_tc1_data_frame_payload_corrupt_gt_dl_mtu_l4_uvm.log rand_data_frame_crc_corrupt_with_ack_grouping_l4_uvm.log rand_data_frame_crc_corrupt_wo_ack_grouping_l4_uvm.log compliance_tc1_data_frame_crc_corrupt_l4_uvm.log compliance_tc0_data_frame_crc_corrupt_l4_uvm.log rand_data_frame_crc_corrupt_with_ack_grouping_l4_quick_uvm.log rand_data_frame_crc_corrupt_wo_ack_grouping_l4_quick_uvm.log compliance_tc1_data_frame_fsn_corrupt_to_prev_acked_l4_uvm.log rand_data_frame_fsn_corrupt_to_prev_acked_with_ack_grouping_l4_uvm.l og rand_data_frame_fsn_corrupt_to_prev_acked_wo_ack_grouping_l4_uvm.lo g compliance_tc0_data_frame_fsn_corrupt_to_prev_acked_l4_uvm.log rand_data_frame_fsn_corrupt_with_ack_grouping_l4_uvm.log compliance_tc1_data_frame_fsn_corrupt_l4_uvm.log compliance_tc0_data_frame_fsn_corrupt_l4_uvm.log rand_data_frame_fsn_corrupt_wo_ack_grouping_l4_quick_uvm.log rand_data_frame_fsn_corrupt_wo_ack_grouping_l4_uvm.log

rand_cof_droped_of_resumed_frame_wo_ack_grouping_l4_uvm.log

compliance_cof_droped_of_resumed_tc0_data_frame_l4_uvm.log

rand_cof_droped_of_resumed_frame_with_ack_grouping_l4_uvm.log

compliance_cof_droped_of_resumed_tc1_data_frame_l4_uvm.log rand_tx_incomplete_data_frame_wo_crc_with_ack_grouping_l4_uvm.log compliance_tx_incomplete_tc0_data_frame_wo_crc_l4_uvm.log rand_tx_incomplete_tc1_data_frame_wo_crc_with_ack_grouping_l4_uvm.lo g compliance_tx_incomplete_tc1_data_frame_wo_crc_l4_uvm.log

rand_tx_incomplete_tc1_data_frame_wo_crc_wo_ack_grouping_l4_uvm.log rand_tx_incomplete_data_frame_wo_crc_wo_ack_grouping_l4_uvm.log rand_tx_incomplete_afc_frame_wo_ack_grouping_l4_uvm.log compliance_tx_incomplete_afc1_l4_uvm.log rand_tx_incomplete_afc_frame_with_ack_grouping_l4_uvm.log compliance_tx_incomplete_afc0_l4_uvm.log compliance_tx_incomplete_nac_w_tc0_traffic_l4_uvm.log compliance_tx_incomplete_nac_w_tc1_traffic_l4_uvm.log compliance_tx_nac_no_outstanding_tc0_data_frame_rem_to_acked_l4_uv m.log compliance_tx_nac_no_outstanding_tc1_data_frame_rem_to_acked_l4_uv m.log compliance_tx_nac_outstanding_tc0_data_frame_rem_to_acked_l4_uvm.lo g compliance_tx_nac_outstanding_tc1_data_frame_rem_to_acked_l4_uvm.lo g rand_randomly_nac_transmission_with_ack_grouping_l4_uvm.log compliance_tx_nac_in_tc0_ntx_rtx_in_progress_l4_uvm.log rand_randomly_nac_transmission_wo_ack_grouping_l4_uvm.log

compliance_tx_nac_in_tc1_ntx_rtx_in_progress_l4_uvm.log compliance_nac_frame_corrupt_rsvd_bits_l4_uvm.log rand_sof_instead_of_cof_of_resumed_data_frame_w_ack_grouping_l4_uv m.log

compliance_sof_instead_of_cof_of_resumed_tc1_data_frame_l4_uvm.log

compliance_sof_instead_of_cof_of_resumed_tc0_data_frame_l4_uvm.log rand_sof_instead_of_cof_of_resumed_data_frame_wo_ack_grouping_l4_uv m.log rand_pre_emption_bet_same_priority_tx_data_frame_with_ack_grouping_l 4_uvm.log compliance_pre_emption_bet_same_priority_tx_tc0_data_frame_l4_uvm.lo g compliance_pre_emption_bet_same_priority_tx_tc1_data_frame_l4_uvm.lo g rand_pre_emption_bet_same_priority_tx_data_frame_wo_ack_grouping_l4 _uvm.log rand_lower_priority_frame_pre_empting_higher_priority_frame_with_ack_ grouping_l4_uvm.log rand_lower_priority_frame_pre_empting_higher_priority_frame_wo_ack_gr ouping_l4_uvm.log compliance_lower_priority_frame_pre_empting_higher_priority_frame_l4_u vm.log compliance_dut_tx_tc0_data_frame_w_size_of_non_multiple_32bytes_l4_u vm.log compliance_dut_rx_tc0_tc1_data_frame_w_size_of_non_multiple_32bytes_l 4_uvm.log

compliance_dut_rx_tc1_data_frame_w_size_of_non_multiple_32bytes_l4_u vm.log compliance_dut_tx_tc0_tc1_data_frame_w_size_of_non_multiple_32bytes_l 4_uvm.log compliance_dut_rx_tc0_data_frame_w_size_of_non_multiple_32bytes_l4_u vm.log compliance_dut_tx_tc1_data_frame_w_size_of_non_multiple_32bytes_l4_u vm.log compliance_tx_afc1_w_creq_set_l4_uvm.log rand_tx_afc_w_creq_set_wo_ack_grouping_l4_uvm.log compliance_tx_afc0_w_creq_set_l4_uvm.log rand_tx_afc_w_creq_set_with_ack_grouping_l4_uvm.log rand_unexpected_framing_w_group_ack_l4_uvm.log rand_unexpected_framing_wo_group_ack_l4_uvm.log compliance_unexpected_framing_on_tc0_frame_l4_uvm.log compliance_unexpected_framing_on_tc1_frame_l4_uvm.log compliance_pre_empt_replay_tc0_data_frame_no_nac_l4_uvm.log compliance_pre_empt_replay_tc1_data_frame_no_nac_l4_uvm.log rand_tc1_credit_blocked_and_tc0_making_progress_l4_uvm.log

rand_tc1_fsn_blocked_and_tc0_making_progress_l4_uvm.log rand_long_pkt_tx_rx_tc1_l3_uvm.log rand_long_pkt_tx_rx_tc0_l3_uvm.log rand_long_pkt_tx_rx_tcx_l3_uvm.log

rand_long_tc0_short_mix_tcx_with_user_device_id84_l3_uvm.log

rand_long_tcx_short_mix_tcx_with_user_device_id_min_l3_uvm.log

rand_long_tc1_short_mix_tcx_with_user_device_id_max_l3_uvm.log

rand_long_tc0_short_mix_tcx_with_user_device_id48_l3_uvm.log rand_long_short_mix_tcx_l3_uvm.log rand_long_short_mix_tc0_l3_uvm.log compliance_dut_long_header_drop_l3_uvm.log rand_test_pkt_specific_e_rr_percentage_case_deviceid_enc_l4.log compliance_tx_corr_deviceid_enc_id_true_l3_uvm.log rand_test_pkt_specific_e_rr_percentage_case_deviceid_enc_uvm.log compliance_tx_corr_deviceid_enc_l4.log compliance_msg_on_disconnected_cport_l4_uvm.log normal_message_tx_CportStatus_NoPeerTc_uvm.log normal_message_tx_size0_eom0.log

normal_fc_tx_in_contious_cycles_uvm.log

rand_normal_segment_tx_rx_tc0_e2efc0_l4.log

rand_normal_segment_tx_rx_tc0_e2efc0_l4_uvm.log

rand_normal_segment_tx_rx_tc0_e2efc0_csv_n0_l4_uvm.log

rand_normal_segment_tx_rx_tc0_e2efc0_csv_n0_l4.log rand_normal_message_with_fct_tx_rx_tc0_l4_uvm.log rand_normal_message_tx_rx_rand_l4_uvm.log rand_normal_message_tx_rx_rand_l4.log

rand_normal_message_with_fct_tx_rx_tc0_l4.log

compliance_normal_message_hello_world_tx_rx_tc0_l4.log

compliance_normal_single_message_single_sequence_tx_rx_tc0_l4_uvm.log compliance_tx_seg_DestCportId_0_l4.log compliance_tx_seg_DestCportId_0_l4_uvm.log compliance_tx_seg_corr_tc_l4_uvm.log compliance_tx_seg_corr_tc_l4.log compliance_zero_seg_tc1_eom1_l4_uvm.log compliance_zero_seg_eom1_l4.log compliance_zero_seg_eom1_l4_uvm.log compliance_normal_segment_tx_rx_cport_gt_31_l4.log compliance_normal_segment_tx_rx_cport_gt_31_l4_uvm.log compliance_fct_updates_e2efc0_l4_uvm.log compliance_fct_updates_e2efc0_l4.log compliance_tx_seg_l4s_0_l4_uvm.log compliance_tx_seg_l4s_0_l4.log

compliance_tx_seg_incorr_connectstate_l4.log

compliance_tx_seg_incorr_connectstate_l4_uvm.log compliance_zero_seg_eom_false_l4.log

compliance_zero_seg_eom_false_l4_uvm.log

rand_normal_message_tx_rx_tc1_latency_e2efc0_l4_uvm.log

rand_normal_message_tx_rx_tc1_latency_e2efc1_l4_uvm.log

rand_normal_message_tx_rx_tc0_l4_uvm.log

rand_normal_message_tx_rx_tc0_l4.log

rand_normal_message_tx_rx_tc0_e2efc1_csv_n0_l4_uvm.log

rand_normal_message_tx_rx_tc0_e2efc1_csv_n0_l4.log

rand_normal_message_tx_tc0_l4.log

rand_normal_message_tx_tc0_l4_uvm.log

rand_normal_message_rx_tc0_l4.log

rand_normal_message_rx_tc0_l4_uvm.log compliance_tx_seg_gt_tmtu_l4_uvm.log compliance_tx_seg_gt_tmtu_l4.log compliance_tx_seg_less_tmtu_eom0_l4_uvm.log compliance_tx_seg_lesss_than_tmtu_eom0_l4.log rand_test_seg_DestCportId_e_rr_e2efc0_l4.log rand_test_seg_DestCportId_e_rr_inj_e2efc1_uvm.log rand_test_seg_DestCportId_e_rr_inj_e2efc1_l4.log

rand_test_seg_DestCportId_e_rr_inj_e2efc0_uvm.log rand_test_seg_TC_e_rr_inj_e2efc1_l4.log rand_test_seg_TC_e_rr_inj_e2efc0_l4.log rand_test_seg_TC_e_rr_inj_e2efc1_uvm.log rand_test_seg_TC_e_rr_inj_e2efc0_uvm.log rand_test_EOM_e_rr_inj_e2efc0_uvm.log rand_test_EOM_e_rr_inj_e2efc0_l4.log rand_test_EOM_e_rr_inj_e2efc1_l4.log rand_test_EOM_e_rr_inj_e2efc1_uvm.log rand_test_FCT_e_rr_inj_e2efc0_uvm.log rand_test_FCT_e_rr_inj_e2efc0_l4.log rand_test_HDR_e_rr_inj_e2efc1_l4.log rand_test_HDR_e_rr_inj_e2efc0_l4.log rand_test_HDR_e_rr_inj_e2efc0_uvm.log rand_test_HDR_e_rr_inj_e2efc1_uvm.log rand_test_seg_payload_size_e_rr_inj_e2efc0_uvm.log rand_test_seg_payload_size_e_rr_inj_e2efc1_l4.log rand_test_seg_payload_size_e_rr_inj_e2efc0_l4.log rand_test_seg_payload_size_e_rr_inj_e2efc1_uvm.log

rand_test_seg_specific_e_rr_percentage_case_e2efc0_l4.log

rand_test_seg_specific_e_rr_percentage_case_e2efc0_uvm.log

rand_test_seg_layer_percentage_e_rr_case_e2efc1_l4.log

rand_test_seg_layer_percentage_e_rr_case_e2efc1_uvm.log

rand_test_seg_specific_and_layer_percentage_e_rr_case_e2efc1_uvm.log

rand_test_seg_specific_e_rr_percentage_case_e2efc1_l4.log

rand_test_seg_specific_e_rr_percentage_case_e2efc1_uvm.log rand_test_Rx_BUFFER_OVERFLOW_e_rr_inj_e2efc1_uvm.log

compliance_dut_csv_e2efc1_seg_drop_l4_uvm.log compliance_dut_csv0_e2efc0_csd0_seg_drop_l4_uvm.log

compliance_dut_csd_e2efc0_l4_RxBuffer_grt0_l4.log

compliance_dut_csd_e2efc0_l4_Rx_buffer_grt0_uvm.log

compliance_dut_rx_overflow_e2efc1_credit_grt0_l4.log

compliance_dut_rx_overflow_e2efc1_credit_grt0_uvm.log

compliance_dut_rx_overflow_e2efc1_l4_credit0_l4.log

compliance_dut_rx_overflow_e2efc1_l4_credit0_uvm.log

compliance_dut_csd_e2efc0_l4_rx_buffer0_l4.log

compliance_dut_csd_e2efc0_l4_rx_buffer0_uvm.log compliance_testmode_e_rr_or_inj_uvm.log compliance_testmode_dut_tstsrc_full_duplex_l4_uvm.log compliance_testmode_dut_tstsrc_full_duplex_l4.log compliance_testmode_dut_tstsrc_half_duplex_txbfm_l4_uvm.log compliance_testmode_dut_tstsrc_half_duplex_txbfm_l4.log compliance_testmode_dut_tstsrc_half_duplex_txdut_l4.log compliance_testmode_dut_tstsrc_half_duplex_txdut_l4_uvm.log compliance_lm_set_get_read_write_chk_uvm.log

compliance_retained_attr_restore_after_hibern8_uvm.log

compliance_unipro_basic_attribute_write_read_test_reg_mode_uvm.log

compliance_dut_attributes_check_after_warm_reset.log compliance_lm_set_get_reset_values_chk_uvm.log compliance_normal_l1p5_lm_set_get_err_uvm.log compliance_dut_init_sequence_dme_uvm.log compliance_cport_connect_sequence_dme_uvm.log

compliance_unipro_basic_attribute_write_read_test_dme_mode_uvm.log

TESTNAME

TEST

compliance_l1p5_two_custom_power_mode_chan ge 2 custom power mode change test 3b4b_Error 5b6b_Error and RD_Error compliance_normal_l1p5_bad_phy_symb from BFM Tx side All Phase : Corrupted TRG_UPRx from compliance_pa_init_phase_err_and_recovery BFM for all Phase BFM LINE-RESET with PACP_PWR_Req & PACP_REQUEST_TIMER timeout directed_test_l1p5_pacp_corruption attempt#2(LINE-RESET) BFM LINE-RESET with PACP_PWR_Req & PACP_REQUEST_TIMER timeout directed_test_l1p5_pacp_corruption attempt#2(LINE-RESET) compliance_l1p5_bfm_not_start_linkstartup_till_d BFM not starting the LINKSTARTUP till ut_timeout the DUT timeout CJTPAT and CRPAT packets corruption NA from BFM side Deskew pattern in the middle of Data compliance_l1p5_deskew_insertion frame Deskew pattern in the middle of Data compliance_l1p5_deskew_insertion frame Deskew pattern in the middle of Data frame

compliance_l1p5_deskew_insertion

compliance_l1p5_lane2lane_skew_gt_2_pa_symb Deskew pattern in the middle of Data ols_dl_frame frame DME L1P5 Initialisation Sequence DUT unipro_l1p5_terminate_link_startup Abort DME L1P5 Initialisation Sequence DUT unipro_l1p5_terminate_link_startup Abort DME L1P5 Initialisation Sequence DUT unipro_l1p5_terminate_link_startup Abort DME L1P5 Initialisation Sequence DUT unipro_l1p5_terminate_link_startup Abort DME L1P5 Initialisation Sequence DUT unipro_l1p5_terminate_link_startup Abort DME L1P5 Initialisation Sequence DUT unipro_l1p5_terminate_link_startup Abort DUT LINE-RESET with PACP_PWR_Req & PACP_REQUEST_TIMER timeout directed_test_l1p5_pacp_corruption attempt#2(LINE-RESET)

directed_test_l1p5_pacp_corruption

DUT LINE-RESET with PACP_PWR_Req & PACP_REQUEST_TIMER timeout attempt#2(LINE-RESET)

compliance_l1p5_pacp_pwr_req_busy_err_succes DUT Power Mode Change Errors s_response (PWR_BUSY-PWR_ERROR_CAP-PWR_OK) compliance_l1p5_pacp_pwr_req_busy_err_succes DUT Power Mode Change Errors s_response (PWR_BUSY-PWR_ERROR_CAP-PWR_OK) DUT Power Mode Change Errors Concurrency Resolution DUT Power Mode Change Errors Concurrency Resolution DUT Power Mode Change Errors Concurrency Resolution DUT Power Mode Change Errors Concurrency Resolution(DEV_ID) DUT Power Mode Change Errors Concurrency Resolution(DEV_ID) DUT Power Mode Change Errors Concurrency Resolution(DEV_ID) DUT Power Mode Change Errors Concurrency Resolution(DEV_ID) DUT Power Mode Change Errors Concurrency Resolution(DEV_ID) DUT Power Mode Change Errors Concurrency Resolution(DEV_ID) DUT Power Mode Change Errors Concurrency Resolution(DEV_ID) DUT Power Mode Change Errors Concurrency Resolution(DEV_ID) DUT Power Mode Change Errors Concurrency Resolution(DEV_ID)

test_l1p5_pacp_concurrency_resolution

test_l1p5_pacp_concurrency_resolution

test_l1p5_pacp_concurrency_resolution

test_l1p5_pacp_concurrency_resolution

test_l1p5_pacp_concurrency_resolution test_l1p5_pacp_concurrency_resolution

test_l1p5_pacp_concurrency_resolution test_l1p5_pacp_concurrency_resolution

test_l1p5_pacp_concurrency_resolution test_l1p5_pacp_concurrency_resolution

test_l1p5_pacp_concurrency_resolution

test_l1p5_pacp_concurrency_resolution

test_l1p5_pacp_concurrency_resolution

DUT Power Mode Change Errors Concurrency Resolution(DEV_ID) DUT Power Mode Change Errors Concurrency Resolution(DEV_ID) DUT Power Mode Change Errors Concurrency Resolution(DEV_ID)

test_l1p5_pacp_concurrency_resolution

test_l1p5_pacp_concurrency_resolution

compliance_l1p5_dut_reject_local_invalid_power_ req DUT reject Local invalid power request unipro_l1p5_pacp_ep_reset unipro_l1p5_pacp_ep_reset directed_test_l1p5_framing_corruption directed_test_l1p5_framing_corruption Endpoint reset from BFM (TRG_EPR) Endpoint reset from DUT (TRG_EPR) Errored frame Transfers - EOB Corruption Errored frame Transfers - EOB Corruption

compliance_l1p5_sob_nd_eob_corruption_during_ Errored frame Transfers - EOB pacp_transfer Corruption Errored frame Transfers - EOB unipro_tb_base_test Corruption Errored frame Transfers - FILLER Corruption(UNEXPECTED_PHY_ESC_SYM unipro_tb_base_test BOL insertion) Errored frame Transfers - FILLER compliance_l1p5_sob_nd_eob_corruption_during_ Corruption(UNEXPECTED_PHY_ESC_SYM pacp_transfer BOL insertion) Errored frame Transfers - FILLER Corruption(UNEXPECTED_PHY_ESC_SYM directed_test_l1p5_framing_corruption BOL insertion) Errored frame Transfers - FILLER Corruption(UNEXPECTED_PHY_ESC_SYM directed_test_l1p5_framing_corruption BOL insertion) Errored frame Transfers - SOB unipro_tb_base_test Corruption compliance_l1p5_sob_nd_eob_corruption_during_ Errored frame Transfers - SOB pacp_transfer Corruption Errored frame Transfers - SOB directed_test_l1p5_framing_corruption Corruption

directed_test_l1p5_framing_corruption

Errored frame Transfers - SOB Corruption Errored frame Transfers - SOB Corruption During LinkStartup sequence Errored frame Transfers - SOB Corruption During LinkStartup sequence Frame Transfers with Res_Error Error Initialisation Sequence Abort due to DUT power mode updates to HIBERN8 or OFFMODE Initialisation Sequence Abort due to DUT power mode updates to HIBERN8 or OFFMODE Initialisation Sequence Abort due to DUT power mode updates to HIBERN8 or OFFMODE Initialisation Sequence Abort due to DUT power mode updates to HIBERN8 or OFFMODE Initialisation Sequence Abort due to DUT power mode updates to HIBERN8 or OFFMODE Initialisation Sequence Abort due to DUT power mode updates to HIBERN8 or OFFMODE L1p5 Initialisation Sequence start and Lock and Unlock the BFM INIT phases with the valid random delays

compliance_pa_init_phase_err_and_abort

compliance_pa_init_phase_err_and_abort directed_test_l1p5_framing_corruption

unipro_l1p5_terminate_link_startup

unipro_l1p5_terminate_link_startup

unipro_l1p5_terminate_link_startup

unipro_l1p5_terminate_link_startup

unipro_l1p5_terminate_link_startup

unipro_l1p5_terminate_link_startup

unipro_random_lock_unlock_l1p5_init_phases

unipro_l1p5_link_startup_sequence_start_on_bfm L1p5 Initialisation Sequence start on DUT _end_n_dut_end and BFM simultaneously unipro_l1p5_link_startup_sequence_start_on_bfm L1p5 Link Startup Sequence start on BFM _end_n_dut_end end after power on reset unipro_l1p5_link_startup_sequence_start_on_bfm L1p5 Link Startup Sequence start on DUT _end_n_dut_end end after power on reset compliance_l1p5_lane2lane_skew_gt_2_pa_symb Lane to Lane skew exceeding more than ols_pacp_frame two PA symbols

compliance_l1p5_lane2lane_skew_gt_2_pa_symb Lane to Lane skew exceeding more than ols_dl_frame two PA symbols LINE-RESET with PA_INIT.req from BFMs unipro_bfm_pa_init_line_reset DL LINE-RESET with PA_INIT.req from DUTs unipro_l1p5_pa_init_line_reset DL LM_PEER_SET_* & LM_PEER_GET_* directed_test_l1p5_pacp_get_set_corruption PEER_COMMUNICATION_FAILURE LM_PEER_SET_* & LM_PEER_GET_* directed_test_l1p5_pacp_get_set_corruption PEER_COMMUNICATION_FAILURE LM_PEER_SET_* & LM_PEER_GET_* PEER_COMMUNICATION_FAILURE LM_PEER_SET_* & LM_PEER_GET_* PEER_COMMUNICATION_FAILURE LM_PEER_SET_* & LM_PEER_GET_* PEER_COMMUNICATION_FAILURE LM_PEER_SET_* & LM_PEER_GET_* PEER_COMMUNICATION_FAILURE LM_PEER_SET_* & LM_PEER_GET_* ConfigResultCode other than SUCCESS LM_PEER_SET_* & LM_PEER_GET_* ConfigResultCode other than SUCCESS LM_PEER_SET_* & LM_PEER_GET_* ConfigResultCode other than SUCCESS LM_PEER_SET_* & LM_PEER_GET_* ConfigResultCode other than SUCCESS LM_PEER_SET_* & LM_PEER_GET_* ConfigResultCode other than SUCCESS LM_PEER_SET_* & LM_PEER_GET_* ConfigResultCode other than SUCCESS LM_PEER_SET_* & LM_PEER_GET_* ConfigResultCode other than SUCCESS LM_PEER_SET_* & LM_PEER_GET_* ConfigResultCode other than SUCCESS LM_PEER_SET_* & LM_PEER_GET_* ConfigResultCode other than SUCCESS LM_PEER_SET_* & LM_PEER_GET_* ConfigResultCode other than SUCCESS

directed_test_l1p5_pacp_get_set_corruption

directed_test_l1p5_pacp_get_set_corruption directed_test_l1p5_pacp_get_set_corruption directed_test_l1p5_pacp_get_set_corruption directed_test_l1p5_pacp_get_set_corruption

directed_test_l1p5_pacp_get_set_corruption directed_test_l1p5_pacp_get_set_corruption directed_test_l1p5_pacp_get_set_corruption directed_test_l1p5_pacp_get_set_corruption directed_test_l1p5_pacp_get_set_corruption

directed_test_l1p5_pacp_get_set_corruption directed_test_l1p5_pacp_get_set_corruption

directed_test_l1p5_pacp_get_set_corruption directed_test_l1p5_pacp_get_set_corruption

unipro_l1p5_pacp_get_req

unipro_l1p5_pacp_set_req

unipro_l1p5_pacp_get_req

unipro_l1p5_pacp_set_req unipro_l1p5_pacp_pwr_req unipro_l1p5_pacp_pwr_req unipro_l1p5_pacp_pwr_req unipro_l1p5_pacp_pwr_req compliance_l1p5_pacp_not_complete_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test

LM_PEER_SET_* & LM_PEER_GET_* Transfers from BFM and DUT ConfigResultCode SUCCESS LM_PEER_SET_* & LM_PEER_GET_* Transfers from BFM and DUT ConfigResultCode SUCCESS LM_PEER_SET_* & LM_PEER_GET_* Transfers from BFM and DUT ConfigResultCode SUCCESS LM_PEER_SET_* & LM_PEER_GET_* Transfers from BFM and DUT ConfigResultCode SUCCESS LS -> HS -> LS request from BFM and DUT LS -> HS -> LS request from BFM and DUT LS -> HS -> LS request from BFM and DUT LS -> HS -> LS request from BFM and DUT New PACP frame Transmission before finishing current PACP frame Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR

unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test

Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame Transfers with DIFFERENT MODE AND GEAR Normal frame transmit on different Lanes Normal frame transmit on different Lanes Normal frame transmit on different Lanes Normal frame transmit on different Lanes Normal frame transmit on different Lanes Normal frame transmit on different Lanes Normal frame transmit on different Lanes Normal frame transmit on different Lanes

Normal frame transmit on different unipro_tb_base_test Lanes Normal frame transmit on different unipro_tb_base_test Lanes Normal frame transmit on different unipro_tb_base_test Lanes Normal frame transmit on different unipro_tb_base_test Lanes Normal frame transmit on different unipro_tb_base_test Lanes Normal frame transmit on different unipro_tb_base_test Lanes Normal frame transmit on different unipro_tb_base_test Lanes Normal frame transmit on different unipro_tb_base_test Lanes Normal frame transmit on different unipro_tb_base_test Lanes Normal frame transmit on different unipro_tb_base_test Lanes Normal frame transmit on different unipro_tb_base_test Lanes Not changing PA_POWERMODE bit for compliance_l1p5_not_changing_pwr_mode_bit_lo long duration of time and having data ng_duration_of_time traffic in-between PA_INIT Sequence Re-initiated from DUTunipro_dut_pa_init_nac_rreq_set DL control unipro_dut_pa_init_afcx_creq_set_during_initial_c PA_INIT Sequence Re-initiated from DUTredit_exchange DL control PA_INIT Sequence Re-initiated from DUTunipro_dut_pa_init_tcx_replay DL control PA_LM_HIBERNATE_ENTER/EXIT from unipro_l1p5_hibernate_entry_n_exit BFM/DUT PA_LM_HIBERNATE_ENTER/EXIT from unipro_l1p5_hibernate_entry_n_exit BFM/DUT PA_LM_HIBERNATE_ENTER/EXIT from unipro_l1p5_hibernate_entry_n_exit BFM/DUT PA_LM_HIBERNATE_ENTER/EXIT from unipro_l1p5_hibernate_entry_n_exit BFM/DUT PACP frame Transmission with CRC compliance_test_l1p5_pacp_crc_corruption Errors PACP frame Transmission with CRC compliance_test_l1p5_pacp_crc_corruption Errors

compliance_test_l1p5_pacp_crc_corruption test_l1p5_pacp_crc_corruption compliance_test_l1p5_pacp_crc_corruption compliance_test_l1p5_pacp_crc_corruption test_l1p5_pacp_crc_corruption rand_test_l1p5_pacp_crc_corruption test_l1p5_corr_pacp_frame_esc_param_pa compliance_l1p5_init_pacp_cap_err_inj

PACP frame Transmission with CRC Errors PACP frame Transmission with CRC Errors PACP frame Transmission with CRC Errors PACP frame Transmission with CRC Errors PACP frame Transmission with CRC Errors PACP frame Transmission with CRC Errors PACP frame Transmission with EscParam_PA error PACP_CAP frame corruption with non PACP_CAP frame PACP_CAP frame corruption with non PACP_CAP frame PACP_CAP_ind frame Transmission with field corruption PACP_GET/SET_cnf frame Transmission with ConfigResultCode other than SUCCESS from BFM PACP_GET/SET_cnf frame Transmission with ConfigResultCode other than SUCCESS from BFM PACP_PWR_cnf PWR_BUSY/PWR_ERROR_CAP from BFM PACP_PWR_cnf PWR_BUSY/PWR_ERROR_CAP from BFM Phase 0 : Corrupted TRG_UPR0 followed by correct TRG_UPRO from BFM Phase 0 : Corrupted TRG_UPR0 followed by correct TRG_UPRO from BFM Phase 0 : Corrupted TRG_UPR0 followed by correct TRG_UPRO from BFM Phase 0 : Corrupted TRG_UPR0 till PA_LINKSTARTUP_TIMER timeout

compliance_l1p5_init_pacp_cap_err_inj test_l1p5_pacp_cap_ind_corruption

directed_test_l1p5_pacp_get_set_corruption

directed_test_l1p5_pacp_get_set_corruption

test_l1p5_pacp_pwr_cnf_status_corruption

test_l1p5_pacp_pwr_cnf_status_corruption

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_recovery compliance_pa_init_phase_err_and_abort

compliance_pa_init_phase_err_and_recovery compliance_pa_init_phase_err_and_recovery

Phase 0b : Corrupted TRG_UPR0 from BFM Phase 0b : Corrupted TRG_UPR0 from BFM Phase 0b : Corrupted TRG_UPR0 from BFM Phase 1 : Corrupted TRG_UPR1 followed by correct TRG_UPR1 from BFM Phase 1 : Corrupted TRG_UPR1 till PA_LINKSTARTUP_TIMER timeout Phase 2 : Corrupted TRG_UPR1 from BFM Phase 3 : Corrupted TRG_UPR2 followed by correct TRG_UPR2 from BFM Phase 3 : Corrupted TRG_UPR2 till PA_LINKSTARTUP_TIMER timeout Phase 4 : Corrupted TRG_UPR2 from BFM Power Mode Change Errors PACP_REQUEST_TIMER Timeout attempt#3 (PWR_FATAL_ERROR) Power Mode Change Errors PACP_REQUEST_TIMER Timeout attempt#3 (PWR_FATAL_ERROR) Power Mode Change Errors PACP_REQUEST_TIMER Timeout attempt#3 (PWR_FATAL_ERROR) Power Mode Change Errors PACP_REQUEST_TIMER Timeout attempt#3 (PWR_FATAL_ERROR) Power Mode Change Errors - Invalid configuration detection Power Mode Change Errors PA_PACPReqEoBTimeout Power Mode Change Errors PA_PACPReqEoBTimeout Power Mode Change Errors PACP_REQUEST_TIMER Timeout attempt#1

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_recovery compliance_pa_init_phase_err_and_abort compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_recovery compliance_pa_init_phase_err_and_abort compliance_pa_init_phase_err_and_recovery

directed_test_l1p5_pacp_corruption

directed_test_l1p5_pacp_corruption

directed_test_l1p5_pacp_corruption

directed_test_l1p5_pacp_corruption test_l1p5_invalid_pwr_mode_config_detection test_l1p5_pacpreq_eob_timeout test_l1p5_pacpreq_eob_timeout

directed_test_l1p5_pacp_corruption

directed_test_l1p5_pacp_corruption compliance_l1p5_pwr_mode_with_user_data compliance_l1p5_rand_symbols_before_sob test_rand_unipro_l1p5_pwr_mode_change test_rand_unipro_l1p5_pwr_mode_change test_rand_unipro_l1p5_pwr_mode_change test_rand_unipro_l1p5_pwr_mode_change test_rand_unipro_l1p5_pwr_mode_change

Power Mode Change Errors PACP_REQUEST_TIMER Timeout attempt#1 Power Mode Change PA_PWRModeUserData testing Random data before Deskew pattern before the Start of burst Random Hibernate entry and exit request from BFM or DUT Random Power Mode Change request from BFM or DUT Random Power Mode Change request from BFM or DUT Random Power Mode Change request from BFM or DUT Random Power Mode Change request from BFM or DUT Random Power Mode Change request from BFM or DUT Random Power Mode Change request from BFM or DUT Skip the Phases optional in the Link Startup Sequence Skip the Phases optional in the Link Startup Sequence Skip the Phases optional in the Link Startup Sequence Skip the Phases optional in the Link Startup Sequence Skip the Phases optional in the Link Startup Sequence Skip the Phases optional in the Link Startup Sequence Test mode initiated from BFM Test mode initiated from BFM Test mode initiated from BFM Test mode initiated from BFM Test mode initiated from BFM Test mode initiated from BFM TRG_UPR0 from BFM during Link Init phase 1 2 3 4 TRG_UPR0 from BFM during Link Init phase 1 2 3 4

test_rand_unipro_l1p5_pwr_mode_change test_rand_unipro_l1p5_pwr_mode_change compliance_pa_init_phase_err_and_skip_phase compliance_pa_init_phase_err_and_skip_phase compliance_pa_init_phase_err_and_skip_phase compliance_pa_init_phase_err_and_skip_phase compliance_pa_init_phase_err_and_skip_phase compliance_pa_init_phase_err_and_skip_phase unipro_pa_phy_test unipro_pa_phy_test unipro_pa_phy_test unipro_pa_phy_test unipro_pa_phy_test unipro_pa_phy_test unipro_l1p5_init_bfm_init_restart_PH_test unipro_l1p5_init_bfm_init_restart_PH_test

unipro_l1p5_init_bfm_init_restart_PH_test unipro_l1p5_init_bfm_init_restart_PH_test

TRG_UPR0 from BFM during Link Init phase 1 2 3 4 TRG_UPR0 from BFM during Link Init phase 1 2 3 4 Various Symbol errors during the init sequence Various Symbol errors during the init sequence Various Symbol errors during the init sequence Various Symbol errors during the init sequence Various Symbol errors during the init sequence Various Symbol errors during the init sequence

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_recovery

Various Symbol errors during the init compliance_l1p5_init_start_inject_symbol_e_rr_or sequence WARM_RESET during Data transfer to unipro_l1p5_linkup_state_after_warm_reset BFM WARM_RESET during Data transfer to unipro_l1p5_linkup_state_after_warm_reset DUT test_afc_init_credit_val AFC with ZERO credits during L2 Init test_afc_init_credit_val AFC with ZERO credits during L2 Init test_afc_init_credit_val AFC with ZERO credits during L2 Init test_afc_init_credit_val AFC with ZERO credits during L2 Init test_afc_init_credit_val AFC with ZERO credits during L2 Init test_afc_init_credit_val AFC with ZERO credits during L2 Init

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_legal_l2_preemption

Basic Normal Preemption case

test_cause_afc_transmission test_cause_afcx_request_timer_expiration

Cause AFCx Transmission Cause DUT's AFCx_REQUEST_TIMER timeout

test_cause_afcx_request_timer_expiration test_cause_afcx_request_timer_expiration test_cause_fcx_protection_timer_expiration test_cause_fcx_protection_timer_expiration test_cause_fcx_protection_timer_expiration test_cause_fcx_protection_timer_expiration test_cause_fcx_protection_timer_expiration test_cause_tcx_replay_timer_expiration test_cause_tcx_replay_timer_expiration test_fail_pa_init directed_test_frame_field_corruption directed_test_frame_field_corruption test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj

Cause DUT's AFCx_REQUEST_TIMER timeout Cause DUT's AFCx_REQUEST_TIMER timeout Cause DUT's FCx_PROTECTION_TIMER timeout Cause DUT's FCx_PROTECTION_TIMER timeout Cause DUT's FCx_PROTECTION_TIMER timeout Cause DUT's FCx_PROTECTION_TIMER timeout Cause DUT's FCx_PROTECTION_TIMER timeout Cause DUT's TCx_REPLAY_TIMER timeout Cause DUT's TCx_REPLAY_TIMER timeout

Cause PHY initialization Sequence failure Cause RX Buffer Overflow at DUT Cause RX Buffer Overflow at DUT Cause RX Buffer Overflow at DUT Cause RX Buffer Overflow at DUT Cause the replayed lower priority frames test_replayed_low_priority_frame_pre_empted_b pre-empted by higher priority nony_non_replayed_high_priority_frame replayed frames Cause two random successive errors and check single NAC reception Cause two random successive errors and check single NAC reception Change Link Properties when the one normal data frame tx is in prorgress Change Link Properties when the one normal data frame tx is in prorgress Change Link Properties when the one normal data frame tx is in prorgress

directed_test_frame_field_corruption

directed_test_frame_field_corruption

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_change_link_properties

Change Link Properties when the one normal data frame tx is in prorgress Change Link Properties when the only local AFCx_REQUEST_TIMER is Running Change Link Properties when the only local AFCx_REQUEST_TIMER is Running Change Link Properties when the only local AFCx_REQUEST_TIMER is Running Change Link Properties when the only local AFCx_REQUEST_TIMER is Running Change Link Properties when the only local AFCx_REQUEST_TIMER is Running Change Link Properties when the only local AFCx_REQUEST_TIMER is Running Change link properties when the preemption is in progress Change link properties when the preemption is in progress Change link properties when the preemption is in progress Change link properties when the preemption is in progress Change Link Properties when there is no traffic on link Change Link Properties when there is no traffic on link DL_LM_HIBERNATE_ENTER/EXIT --After L1P5 DL_LM_RESET --- After L1P5 Drop sending AFC for correctly received frame

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_change_link_properties NA NA test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj test_duplicate_control_afc_frame test_l2_layer_percentage_err_inj

Drop sending AFC for correctly received frame Duplicate AFCx Duplicate AFCx

test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_duplicate_control_afc_frame test_dut_grouped_acknowledgment test_dut_grouped_acknowledgment test_dut_grouped_acknowledgment

Duplicate AFCx Duplicate AFCx Duplicate AFCx DUT's Grouped Acknowledgment Mechanism DUT's Grouped Acknowledgment Mechanism DUT's Grouped Acknowledgment Mechanism

test_cause_fcx_protection_timer_expiration_durin FCx_PROTECTION_TIMER timeout during g_l2_init L2 Init

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption

Illegal Preemption case

test_illegal_l2_preemption test_illegal_l2_preemption test_multilevel_preemption_corr_cof_tc test_multilevel_preemption_corr_cof_tc

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test unipro_tb_base_test

Illegal Preemption case Illegal Preemption case Multilevel preemption and COF TC get courrupt (TC1 become TC0) Multilevel preemption and COF TC get courrupt (TC1 become TC0) Normal concurrent frame transmission and reception with ACK grouping and random delay on TC0 and TC1 Normal concurrent frame transmission and reception with ACK grouping and random delay on TC0 or TC1 Normal concurrent frame transmission and reception with ACK grouping and random delay on TC0 or TC1 Normal frame reception without ACK grouping

unipro_tb_base_test unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj NA NA NA test_corr_afc_frame_rsvd_bits test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_corr_afc_frame_rsvd_bits

Normal frame reception without ACK grouping Normal frame reception without ACK grouping Normal frame transmission and reception without grouping and delay between ACKs Normal frame transmission and reception without grouping and delay between ACKs Normal frame transmission and reception without grouping and delay between ACKs Normal frame transmission and reception without grouping and delay between ACKs Normal frame transmission and reception without grouping and delay between ACKs Normal frame transmission and reception without grouping and delay between ACKs Normal frame transmit Normal frame transmit Normal frame transmit Random Error Injection at L2 Layer Random Error Injection at L2 Layer Receiving NAC RReq bit set during L2 Init Reception of PA_ERROR_ind Scenarios leading to PHY initialization Send AFC Frame Corrupted Reserved bits Send AFC Frame Corrupted Reserved bits Send AFC Frame Corrupted Reserved bits Send AFC Frame Corrupted Reserved bits

Send AFCx for data frame being test_tx_afc_fsn_when_same_fsn_data_frame_rtx Retransmitted

Send AFCx for data frame being test_tx_afc_fsn_when_same_fsn_data_frame_rtx Retransmitted Send COF EOF_EVEN or EOF_ODD when directed_test_frame_field_corruption no data frame was started Send COF EOF_EVEN or EOF_ODD when directed_test_frame_field_corruption no data frame was started Send COF EOF_EVEN or EOF_ODD when directed_test_frame_field_corruption no data frame was started Send COF EOF_EVEN or EOF_ODD when no data frame was started Send COF EOF_EVEN or EOF_ODD when no data frame was started Send COF EOF_EVEN or EOF_ODD when no data frame was started Send COF EOF_EVEN or EOF_ODD when no data frame was started Send COF EOF_EVEN or EOF_ODD when no data frame was started Send COF EOF_EVEN or EOF_ODD when no data frame was started Send COF EOF_EVEN or EOF_ODD when no data frame was started Send COF EOF_EVEN or EOF_ODD when no data frame was started Send COF EOF_EVEN or EOF_ODD when no data frame was started Send COF EOF_EVEN or EOF_ODD when no data frame was started Send COF symbol continuing a Data frame of a different TC Send COF symbol continuing a Data frame of a different TC Send COF symbol continuing a Data frame of a different TC Send COF symbol continuing a Data frame of a different TC

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj directed_test_frame_field_corruption directed_test_frame_field_corruption directed_test_frame_field_corruption test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj directed_test_frame_field_corruption test_l2_layer_percentage_err_inj directed_test_frame_field_corruption test_l2_layer_percentage_err_inj test_control_frame_corrupt_crc test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_control_frame_corrupt_crc test_l2_layer_percentage_err_inj test_control_frame_corrupt_crc test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_control_frame_corrupt_crc directed_test_frame_field_corruption test_l2_layer_percentage_err_inj

Send COF without any prior pre-emption Send COF without any prior pre-emption Send COF without any prior pre-emption Send COF without any prior pre-emption Send Control frame corrupted CRC-16 Send Control frame corrupted CRC-16 Send Control frame corrupted CRC-16 Send Control frame corrupted CRC-16 Send Control frame corrupted CRC-16 Send Control frame corrupted CRC-16 Send Control frame corrupted CRC-16 Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL

test_l2_layer_percentage_err_inj directed_test_frame_field_corruption test_control_frame_corrupt_crc

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj directed_test_frame_field_corruption directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj

Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Corrupt ESC_DL Send Control Symbols with Reserved TCx values Send Control Symbols with Reserved TCx values Send Control Symbols with Reserved TCx values Send Control Symbols with Reserved TCx values Send Control Symbols with Reserved TCx values Send Control Symbols with Reserved TCx values Send Control Symbols with Reserved TCx values Send Control Symbols with Reserved TCx values Send Control Symbols with Reserved TCx values Send Control Symbols with Reserved TCx values Send Control Symbols with Reserved TCx values Send Control Symbols with Reserved TCx values Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type

test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj directed_test_frame_field_corruption directed_test_frame_field_corruption test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_control_frame_corrupt_crc test_l2_layer_percentage_err_inj test_control_frame_corrupt_crc test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj directed_test_frame_field_corruption directed_test_frame_field_corruption test_l2_layer_percentage_err_inj directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_control_frame_corrupt_crc

test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj directed_test_frame_field_corruption test_l2_layer_percentage_err_inj directed_test_frame_field_corruption test_control_frame_corrupt_crc test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj directed_test_frame_field_corruption directed_test_frame_field_corruption test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj

Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Control Symbols with the Reserved control symbols type Send Data Frame Corrupted Reserved bits Send Data Frame Corrupted Reserved bits Send Data Frame Corrupted Reserved bits Send Data Frame Corrupted Reserved bits Send Data Frame Corrupted Reserved bits Send Data Frame Corrupted Reserved bits Send Data Frame Corrupted Reserved bits

test_l2_layer_percentage_err_inj directed_test_frame_field_corruption test_l2_layer_percentage_err_inj test_corr_cof_ctrl_sym_rsvd_bits test_l2_layer_percentage_err_inj test_corr_cof_ctrl_sym_rsvd_bits test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_corr_data_frame_rsvd_bits

test_corr_data_frame_rsvd_bits directed_test_frame_field_corruption

Send Data Frame Corrupted Reserved bits Send Data frame crossing DL_SYMBOL_MTU Send Data frame crossing DL_SYMBOL_MTU Send Data frame crossing DL_SYMBOL_MTU Send Data frame crossing DL_SYMBOL_MTU Send Data frame with corrupt CRC-16 Send Data frame with corrupt CRC-16 Send Data frame with corrupt CRC-16 Send Data frame with corrupt CRC-16 Send Data frame with corrupt CRC-16 Send Data frame with corrupt CRC-16 Send Data frame with the Sequence number thats previously ACKed Send Data frame with the Sequence number thats previously ACKed Send Data frame with the Sequence number thats previously ACKed Send Data frame with the Sequence number thats previously ACKed Send Data frame with the wrong Sequence number Send Data frame with the wrong Sequence number Send Data frame with the wrong Sequence number Send Data frame with the wrong Sequence number Send Data frame with the wrong Sequence number Send EOF_EVEN or EOF_ODD or data symbol when a Data frame is pre empted Send EOF_EVEN or EOF_ODD or data symbol when a Data frame is pre empted

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj directed_test_frame_field_corruption test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj directed_test_frame_field_corruption directed_test_frame_field_corruption test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_data_frame_prev_acked_fsn

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj test_data_frame_prev_acked_fsn test_l2_layer_percentage_err_inj directed_test_frame_field_corruption directed_test_frame_field_corruption test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj

Send EOF_EVEN or EOF_ODD or data symbol when a Data frame is pre empted Send EOF_EVEN or EOF_ODD or data symbol when a Data frame is pre empted Send EOF_EVEN/EOF_ODD without CRC symbol Send EOF_EVEN/EOF_ODD without CRC symbol Send EOF_EVEN/EOF_ODD without CRC symbol Send EOF_EVEN/EOF_ODD without CRC symbol Send EOF_EVEN/EOF_ODD without CRC symbol Send EOF_EVEN/EOF_ODD without CRC symbol Send Incomplete AFC symbol Send Incomplete AFC symbol Send Incomplete AFC symbol Send Incomplete AFC symbol Send Incomplete NAC symbol Send Incomplete NAC symbol Send NAC and cause Retransmission from DUT (No Outstanding Frames to be Acked) Send NAC and cause Retransmission from DUT (No Outstanding Frames to be Acked) Send NAC and cause Retransmission from DUT (Outstanding Frames Remaining to be Acked) Send NAC and cause Retransmission from DUT (Outstanding Frames Remaining to be Acked) Send NAC during data frame Transmission/Retransmission Send NAC during data frame Transmission/Retransmission Send NAC during data frame Transmission/Retransmission

directed_test_frame_field_corruption test_l2_layer_percentage_err_inj directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_control_frame_corrupt_crc test_l2_layer_percentage_err_inj test_control_frame_corrupt_crc test_control_frame_corrupt_crc test_control_frame_corrupt_crc test_nac_transmission_when_outstanding_frame_ rem_to_acked_specified test_nac_transmission_when_outstanding_frame_ rem_to_acked_specified test_nac_transmission_when_outstanding_frame_ rem_to_acked_specified test_nac_transmission_when_outstanding_frame_ rem_to_acked_specified test_l2_layer_percentage_err_inj test_nac_transmission_in_ntx_rtx_in_progress test_l2_layer_percentage_err_inj

test_nac_transmission_in_ntx_rtx_in_progress test_corr_nac_frame_rsvd_bits

Send NAC during data frame Transmission/Retransmission Send NAC Frame Corrupted Reserved bits Send SOF when a Preempted Data frame is Resume Send SOF when a Preempted Data frame is Resume Send SOF when a Preempted Data frame is Resume Send SOF when a Preempted Data frame is Resume Send SOF when data frame of same TCx is in progress / Pre-emption between happen Same Priority Frame Send SOF when data frame of same TCx is in progress / Pre-emption between happen Same Priority Frame Send SOF when data frame of same TCx is in progress / Pre-emption between happen Same Priority Frame Send SOF when data frame of same TCx is in progress / Pre-emption between happen Same Priority Frame Send TC0 data frame pre-empting the TC1 data frame / Higher Priority Frame Pre-Empted by Lower one Send TC0 data frame pre-empting the TC1 data frame / Higher Priority Frame Pre-Empted by Lower one Send TC0 data frame pre-empting the TC1 data frame / Higher Priority Frame Pre-Empted by Lower one Send TCx Data Frame with Payload size of non integral multiple of 32 Send TCx Data Frame with Payload size of non integral multiple of 32

test_l2_layer_percentage_err_inj

directed_test_frame_field_corruption

directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

directed_test_frame_field_corruption

directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

directed_test_frame_field_corruption

test_credit_flow_control

test_credit_flow_control

test_credit_flow_control

Send TCx Data Frame with Payload size of non integral multiple of 32 Send TCx Data Frame with Payload size of non integral multiple of 32 Send TCx Data Frame with Payload size of non integral multiple of 32

test_credit_flow_control

test_credit_flow_control

Send TCx Data Frame with Payload size of non integral multiple of 32 Send the AFC with CReq bit set Send the AFC with CReq bit set Send the AFC with CReq bit set Send the AFC with CReq bit set Send unexpected framing Sequence Send unexpected framing Sequence Send unexpected framing Sequence Send unexpected framing Sequence SOF during data frame of same TC is test_pre_emption_by_replay_frame_of_same_tc permitted with pre-emption and replay SOF during data frame of same TC is test_pre_emption_by_replay_frame_of_same_tc permitted with pre-emption and replay TC1 Data Frame Credit blocked and TC0 test_tc1_block_tc0_progress Data Frame making progress TC1 Data Frame FSN blocked due to maximum outstanding and TC0 Data test_tc1_block_tc0_progress Frame making progress Normal Long Packet Transmit and unipro_tb_base_test Receive TC0 Normal Long Packet Transmit and unipro_tb_base_test Receive TC0 Normal Long Packet Transmit and unipro_tb_base_test Receive TC0 and TC1 Normal Long/Short Packet Transmit and Receive TC0 with different Device ID and unipro_tb_base_test Device ID valid Normal Long/Short Packet Transmit and Receive TC0 with different Device ID and unipro_tb_base_test Device ID valid Normal Long/Short Packet Transmit and Receive TC0 with different Device ID and unipro_tb_base_test Device ID valid test_credit_flow_control test_compliance_tx_afc_w_creq_set test_l2_layer_percentage_err_inj test_compliance_tx_afc_w_creq_set test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_l2_layer_percentage_err_inj test_compliance_unexpected_framing test_compliance_unexpected_framing

unipro_tb_base_test unipro_tb_base_test unipro_tb_base_test compliance_dut_long_header_drop NA test_compliance_corr_device_id_enc test_segment_percentage_e_rr_or NA compliance_l4_connect_disconnect_cport NA NA

NA

NA

unipro_tb_base_test

unipro_tb_base_test

NA test_message_normal_with_fct_updation unipro_tb_base_test NA

Normal Long/Short Packet Transmit and Receive TC0 with different Device ID and Device ID valid Normal short header traffic along with the long header traffic with the TC0/1 Normal short header traffic along with the long header traffic with the TC0/1 Transmit Long Header Packet and check support in DUT Transmit packet with the bad DeviceID encoding Transmit packet with the bad DeviceID encoding Transmit packet with the bad DeviceID encoding Transmit packet with the bad DeviceID encoding Message to disconnected Cport MESSAGE transmit on cport of status indication of NO_PEER_TC. MESSAGE transmit with t_tx_eom is not set for msg fragment of zero size. Normal FC Req of Random Credits in continious cycles till t_tx_result = CREDIT EXCEED asserted. Normal Segments transmitting and receiving from default CPortID on TC0 with E2E FC disabled Normal Segments transmitting and receiving from default CPortID on TC0 with E2E FC disabled Normal Segments transmitting and receiving from default CPortID on TC0 with E2E FC disabled Normal Segments transmitting and receiving from default CPortID on TC0 with E2E FC disabled Normal Segments transmitting and receiving on random CPorts Normal Segments transmitting and receiving on random CPorts Normal Segments transmitting and receiving on random CPorts

NA

NA

unipro_single_message_single_sequence_test NA directed_test_segment_field_corruption directed_test_segment_field_corruption NA test_segment_zero_size_data_eom1 NA test_segment_zero_size_data_eom1 NA unipro_tb_base_test directed_test_segment_field_corruption NA directed_test_segment_field_corruption NA

NA

compliance_tx_seg_incorr_connectstate NA

Normal Segments transmitting and receiving on random CPorts Normal single message (T_SDU) transmitting and receiving from default CPortID on TC0 Normal single message (T_SDU) transmitting and receiving from default CPortID on TC0 Send Incorrect Protocol Control Information - DestCPortID Send Incorrect Protocol Control Information - DestCPortID Send Incorrect Protocol Control Information - TC Send Incorrect Protocol Control Information - TC Send zero sized segment with EOM set to TRUE Send zero sized segment with EOM set to TRUE Send zero sized segment with EOM set to TRUE Tranmsit and receive segments with CPortID greater than 31 Tranmsit and receive segments with CPortID greater than 31 Tranmsit FCT when the E2E FC is disabled Tranmsit FCT when the E2E FC is disabled Tranmsit segment with the L4s=0 Tranmsit segment with the L4s=0 Transmit different types of segments when DUT T_ConnectionState is not in CONNECTED Transmit different types of segments when DUT T_ConnectionState is not in CONNECTED Transmit Zero sized segment without EOM being set

test_segment_zero_size_data_eom_field_corrupti Transmit Zero sized segment without on EOM being set

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

NA

unipro_tb_base_test

NA

NA

unipro_tb_base_test

NA

unipro_tb_base_test directed_test_segment_field_corruption NA directed_test_segment_field_corruption NA NA test_segment_percentage_e_rr_or NA

Transmitting and receiving segments (T_PDU) of random size from default CPortID on TC0 from DUT Transmitting and receiving segments (T_PDU) of random size from default CPortID on TC0 from DUT Transmitting and receiving segments (T_PDU) of random size from default CPortID on TC0 from DUT Transmitting and receiving segments (T_PDU) of random size from default CPortID on TC0 from DUT Transmitting and receiving segments (T_PDU) of random size from default CPortID on TC0 from DUT Transmitting and receiving segments (T_PDU) of random size from default CPortID on TC0 from DUT Transmitting segments (T_PDU) of random size from default CPortID on TC0 from BFM Transmitting segments (T_PDU) of random size from default CPortID on TC0 from BFM Transmitting segments (T_PDU) of random size from default CPortID on TC0 from DUT Transmitting segments (T_PDU) of random size from default CPortID on TC0 from DUT Trasmit a segment greater than the T_MTU Trasmit a segment greater than the T_MTU Trasmit a segment with less than T_MTU with out EOM bit to set Trasmit a segment with less than T_MTU with out EOM bit to set Tx segment Destination CportID corruption Tx segment Destination CportID corruption Tx segment Destination CportID corruption

test_segment_percentage_e_rr_or NA NA test_segment_percentage_e_rr_or test_segment_percentage_e_rr_or test_segment_percentage_e_rr_or NA NA test_segment_percentage_e_rr_or test_segment_percentage_e_rr_or NA NA NA test_segment_percentage_e_rr_or test_segment_percentage_e_rr_or test_segment_percentage_e_rr_or NA NA test_segment_percentage_e_rr_or

NA

test_segment_percentage_e_rr_or

NA

test_segment_percentage_e_rr_or

test_segment_percentage_e_rr_or

NA

test_segment_percentage_e_rr_or test_segment_percentage_e_rr_or

Tx segment Destination CportID corruption Tx segment Destination TC corruption Tx segment Destination TC corruption Tx segment Destination TC corruption Tx segment Destination TC corruption Tx segment EOM corruption Tx segment EOM corruption Tx segment EOM corruption Tx segment EOM corruption Tx segment FCT corruption Tx segment FCT corruption Tx segment HDR corruption Tx segment HDR corruption Tx segment HDR corruption Tx segment HDR corruption Tx segment Payload size corruption Tx segment Payload size corruption Tx segment Payload size corruption Tx segment Payload size corruption Tx segment PERCENTAGE ERROR CASE with E2EFC = 0 and multiple specific error injections Tx segment PERCENTAGE ERROR CASE with E2EFC = 0 and multiple specific error injections Tx segment PERCENTAGE ERROR CASE with E2EFC = 1 and enabling all the L4 error injection Tx segment PERCENTAGE ERROR CASE with E2EFC = 1 and enabling all the L4 error injection Tx segment PERCENTAGE ERROR CASE with E2EFC = 1 and enabling all the L4 error injection Tx segment PERCENTAGE ERROR CASE with E2EFC = 1 and multiple specific error injections Tx segment PERCENTAGE ERROR CASE with E2EFC = 1 and multiple specific error injections Tx segment Rx_BUFFER_OVERFLOW corruption

test_seg_dropped_csv_enable test_seg_dropped_csv_enable

NA test_segment_RxBuffer_overflow_e2efc1_credit_g rt0

NA test_segment_RxBuffer_overflow_e2efc1_credit_g rt0

NA

test_segment_RxBuffer_overflow_e2efc1_credit0

NA

test_segment_RxBuffer_overflow_e2efc1_credit0 NA test_message_test_feature NA test_message_test_feature NA NA test_message_test_feature compliance_dme_lm_set_get

Tx segment when E2EFC1 ENABLE and CSV feature is enable Tx segment when E2EFC1 ENABLE and CSV feature is enable Tx segment when the less than needed credits are available with E2EFC set to 0 Rx Overflow Tx segment when the less than needed credits are available with E2EFC set to 0 Rx Overflow Tx segment when the less than needed credits are available with E2EFC set to 1 Rx Overflow Tx segment when the less than needed credits are available with E2EFC set to 1 Rx Overflow Tx segment when the zero credits are available with E2EFC set to 1 - Rx Overflow Tx segment when the zero credits are available with E2EFC set to 1 - Rx Overflow Tx segment when the zero RX BUffer are available with E2EFC0 and CSD feature is enable Tx segment when the zero RX BUffer are available with E2EFC0 and CSD feature is enable UniPro Test mode - Error injection UniPro Test mode - FULL DUPLEX UniPro Test mode - FULL DUPLEX UniPro Test mode HALF_DUPLEX_TxBFM UniPro Test mode HALF_DUPLEX_TxBFM UniPro Test mode HALF_DUPLEX_TxDUT UniPro Test mode HALF_DUPLEX_TxDUT DUT LM_SET_* / LM_GET_* - Power on value and Write/Read check

compliance_retained_attr_restore_after_hibern8_ After Hibernate exit make sure retained test attributes are restored

compliance_unipro_basic_attribute_write_read_te st Custom Read/Write RAL sequence compliance_dut_attributes_check_after_warm_res et DME Warm reset and attributes read DUT LM_SET_* / LM_GET_* - Power on compliance_dme_lm_set_get value and Write/Read check compliance_normal_l1p5_lm_set_get_err LM_SET_* / LM_GET_* Error Transfers unipro_dut_init_user_ral_test Overriding the DUT Init RAL sequnce Overriding the CPORT CONNECT RAL unipro_single_message_single_cport_ral_test sequence compliance_unipro_basic_attribute_write_read_te st Custom Read/Write RAL sequence

DESCRIPTION

PRIOIRITY

arguments provided in below Stimulus section Stimulus: First power request;

P0+PWR_REQ_TX_MODE/PWR

[0] Enable the 3b4b_Error, 5b6b_Error, and RD_Error in the m-phy BFM Tx side [1] Send P0 a message from the BFM wh

- Start the initialization sequence from both DUT, BFM - Transmit upto 10 INVALID_TRG_UPRx_TRIGGERS P0 for DUT's ph

Refer LINE - 1190 , 1191 & 1192 Rx Error injection where the PACP_PWR_cnf from DUT isP0 dropped Cover hibenrate and

Refer LINE - 1190 , 1191 & 1192 Rx Error injection where the PACP_PWR_cnf from DUT isP0 dropped Cover hibenrate and

- Initiate the PA Link Statrtup sequence from DUT - Wait for DUT to timer timedout - Again, P0 Initiate the PA Link Startup

1. BFM initiates the test mode2. Error is injected sometimes in the CJTPAT and CRPAT packets P0 sent via PACP_TEST_DATA

Scenario#1: Single lane - Start off with random HS, LS Mode and single lane - From BFM P0 Start the data frame transmi

Scenario#1: Single lane - Start off with random HS, LS Mode and single lane - From BFM P0 Start the data frame transmi

Scenario#1: Single lane - Start off with random HS, LS Mode and single lane - From BFM P0 Start the data frame transmi

Scenario#1: Single lane - Start off with random HS, LS Mode and single lane - From BFM P0 Start the data frame transmi

[1] Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 [2] A UniPro Link Startup Seq

[1] Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 [2] A UniPro Link Startup Seq

[1] Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 [2] A UniPro Link Startup Seq

[1] Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 [2] A UniPro Link Startup Seq

[1] Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 [2] A UniPro Link Startup Seq

[1] Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 [2] A UniPro Link Startup Seq

Refer LINE - 1190 , 1191 & 1192Cover hibenrate and non-hibernate cases [1] From DUT initiate P0 the PWR Mode change

Refer LINE - 1190 , 1191 & 1192Cover hibenrate and non-hibernate cases [1] From DUT initiate P0 the PWR Mode change

//PWR_BUSY [1]Issue a valid PWR Mode change Request to DUT - Writing the PA_PWRMode P0 completed [2] Figure o

//PWR_BUSY [1]Issue a valid PWR Mode change Request to DUT - Writing the PA_PWRMode P0 completed [2] Figure o

Cover hibenrate and non-hibernate cases Scenario#1: DUT rejecting the local request [1] P0 Send a valid PACP PWR Requ

Cover hibenrate and non-hibernate cases Scenario#1: DUT rejecting the local request [1] P0 Send a valid PACP PWR Requ

Cover hibenrate and non-hibernate cases Scenario#1: DUT rejecting the local request [1] P0 Send a valid PACP PWR Requ

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

Cover hibenrate and non-hibernate casesScenario#1: Local req reject when a remote reqP0 is received when local req is b

P0

[1] Test gives EPR from the BFM[2] Test verifies the end point reset is indicated at the DUT P0side.[3] This verifies the PAC

[1] Test gives EPR from the DUT[2] Test verifies the end point reset is indicated at the BFM P0side[3] This verifies the PAC

Inject EOB_CORR for the PACP / DL Frames Compliance: Scenario #1 : Data and control bit P0 corruption(INJ_DFRAME_EO

Inject EOB_CORR for the PACP / DL Frames Compliance: Scenario #1 : Data and control bit P0 corruption(INJ_DFRAME_EO

Inject EOB_CORR for the PACP / DL Frames Compliance: Scenario #1 : Data and control bit P0 corruption(INJ_DFRAME_EO

Inject EOB_CORR for the PACP / DL Frames Compliance: Scenario #1 : Data and control bit P0 corruption(INJ_DFRAME_EO

Scenario#1 : Corrupted fillers in the middle of DL Data frame [1] Transmit a DL data frame P0 from the BFM [2] In the mi

Scenario#1 : Corrupted fillers in the middle of DL Data frame [1] Transmit a DL data frame P0 from the BFM [2] In the mi

Scenario#1 : Corrupted fillers in the middle of DL Data frame [1] Transmit a DL data frame P0 from the BFM [2] In the mi

Scenario#1 : Corrupted fillers in the middle of DL Data frame [1] Transmit a DL data frame P0 from the BFM [2] In the mi Inject SOB_CORR for the PACP / DL Frames. Compliance: MK0_xx DNC not corrupted(INJ_DFRAME_SOB_CORR) P0

Inject SOB_CORR for the PACP / DL Frames. Compliance: MK0_xx DNC not corrupted(INJ_DFRAME_SOB_CORR) P0 Inject SOB_CORR for the PACP / DL Frames. Compliance: MK0_xx DNC not corrupted(INJ_DFRAME_SOB_CORR) P0

Inject SOB_CORR for the PACP / DL Frames. Compliance: MK0_xx DNC not corrupted(INJ_DFRAME_SOB_CORR) P0

Inject SOB_CORR(MK0_xx) for INIT SYMBOLS . Compliance: DURING TX_INIT_PHASE_0: P0

[1] SOB for INIT_SYMBOL

Inject SOB_CORR(MK0_xx) for INIT SYMBOLS . Compliance: DURING TX_INIT_PHASE_0: P0

[1] SOB for INIT_SYMBOL

[1] Send a message from the BFM [2] From BFM Tx insert a {MARKER3, MAKER4, MARKER5} P0 [3] DUT L1.5 will pass t

- Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 A UniPro Link Startup Sequen

- Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 A UniPro Link Startup Sequen

- Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 A UniPro Link Startup Sequen

- Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 A UniPro Link Startup Sequen

- Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 A UniPro Link Startup Sequen

- Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. P0 A UniPro Link Startup Sequen

- Initiaite the PA Link Startup sequence from the DUT and BFM simultaneously or either P0 end - Using Lock Unlock featu

- Initiaite the PA Link Startup sequence from the DUT and BFM simultaneously - Wait for P0 the initialization to complete

- On power up donot program the DUT L1.5 to start the initialization - Wait for a period less P0 than Link Startup timer tim

- On power up don't program the BFM L1.5 to start the initialization - Wait for a period less P0 than Link Startup timer tim

Scenario#1 : DL Frame - Start off with random HS, LS Mode and max number of lanes supported P0 - Transmit a data fram

Scenario#1 : DL Frame - Start off with random HS, LS Mode and max number of lanes supported P0 - Transmit a data fram

Refer LINE - 1190 , 1191 & 1192Scenario: [1] Configure the TC0_REPLAY_TIMER in P0 L2 of DUT with a small value

Refer LINE - 1190 , 1191 & 1192Scenario: [1] Configure the TC0_REPLAY_TIMER in P0 L2 of DUT with a small value

[1] Issue PA_LM_PEER_SET/GET.req(selected randomly) with the Attr_ID set to PA_SleepNoConfigTime P0 from DUT[2] Blo

[1] Issue PA_LM_PEER_SET/GET.req(selected randomly) with the Attr_ID set to PA_SleepNoConfigTime P0 from DUT[2] Blo

[1] Issue PA_LM_PEER_SET/GET.req(selected randomly) with the Attr_ID set to PA_SleepNoConfigTime P0 from DUT[2] Blo

[1] Issue PA_LM_PEER_SET/GET.req(selected randomly) with the Attr_ID set to PA_SleepNoConfigTime P0 from DUT[2] Blo

[1] Issue PA_LM_PEER_SET/GET.req(selected randomly) with the Attr_ID set to PA_SleepNoConfigTime P0 from DUT[2] Blo

[1] Issue PA_LM_PEER_SET/GET.req(selected randomly) with the Attr_ID set to PA_SleepNoConfigTime P0 from DUT[2] Blo Scenario#1: INVALID_MIB_ATTRIBUTE [1] Issue PA_LM_PEER_SET.req from BFM to an invalid P0 attribute id (Ex: 0x1559)

Scenario#1: INVALID_MIB_ATTRIBUTE [1] Issue PA_LM_PEER_SET.req from BFM to an invalid P0 attribute id (Ex: 0x1559) Scenario#1: INVALID_MIB_ATTRIBUTE [1] Issue PA_LM_PEER_SET.req from BFM to an invalid P0 attribute id (Ex: 0x1559) Scenario#1: INVALID_MIB_ATTRIBUTE [1] Issue PA_LM_PEER_SET.req from BFM to an invalid P0 attribute id (Ex: 0x1559) Scenario#1: INVALID_MIB_ATTRIBUTE [1] Issue PA_LM_PEER_SET.req from BFM to an invalid P0 attribute id (Ex: 0x1559) Scenario#1: INVALID_MIB_ATTRIBUTE [1] Issue PA_LM_PEER_SET.req from BFM to an invalid P0 attribute id (Ex: 0x1559)

Scenario#1: INVALID_MIB_ATTRIBUTE [1] Issue PA_LM_PEER_SET.req from BFM to an invalid P0 attribute id (Ex: 0x1559) Scenario#1: INVALID_MIB_ATTRIBUTE [1] Issue PA_LM_PEER_SET.req from BFM to an invalid P0 attribute id (Ex: 0x1559)

Scenario#1: INVALID_MIB_ATTRIBUTE [1] Issue PA_LM_PEER_SET.req from BFM to an invalid P0 attribute id (Ex: 0x1559) Scenario#1: INVALID_MIB_ATTRIBUTE [1] Issue PA_LM_PEER_SET.req from BFM to an invalid P0 attribute id (Ex: 0x1559)

Scenario#1: Initiated from BFM [1] Issue PA_LM_PEER_SET.req with the Attr_ID set to PA_SleepNoConfigTime P0 from B

Scenario#1: Initiated from BFM [1] Issue PA_LM_PEER_SET.req with the Attr_ID set to PA_SleepNoConfigTime P0 from B

Scenario#1: Initiated from BFM [1] Issue PA_LM_PEER_SET.req with the Attr_ID set to PA_SleepNoConfigTime P0 from B

Scenario#1: Initiated from BFM [1] Issue PA_LM_PEER_SET.req with the Attr_ID set to PA_SleepNoConfigTime P0 from B

Power mode change by BFM from default LS to HS and again from HS to LS on different P0 number of lanes [1] Power mo

Power mode change by BFM from default LS to HS and again from HS to LS on different P0 number of lanes [1] Power mo

Power mode change by BFM from default LS to HS and again from HS to LS on different P0 number of lanes [1] Power mo

Power mode change by BFM from default LS to HS and again from HS to LS on different P0 number of lanes [1] Power mo

This is like PACP frame pre-emption. Its not valid and pre-empted frame is discarded and P0 never resumed. Spec is not Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0 Frames are transferred on Different no. of LANE's with different MODE and GEAR Stimulus: P0

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

+PWR_REQ_TX_MO

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different P0 no.of lane combinatio

-Writing the gear,lane,speed pwr_mode Attribute-Do some message tranfser in between-Then P0 write the PA_PWRmode

Scenario#1

- Do some 2 message from both BFM and DUT. Wait for it to complete

- Send P0 NAC frame with the RReq bit

Scenario#1

- Do some 2 message from both BFM and DUT. Wait for it to complete

- Send P0 NAC frame with the RReq bit

Scenario#1

- Do some 2 message from both BFM and DUT. Wait for it to complete

- Send P0 NAC frame with the RReq bit

- Send 2 data frames both from both BFM and DUT - Initiate HIBRNATE ENTRY command P0with target set to BFM or DU

- Send 2 data frames both from both BFM and DUT - Initiate HIBRNATE ENTRY command P0with target set to BFM or DU

- Send 2 data frames both from both BFM and DUT - Initiate HIBRNATE ENTRY command P0with target set to BFM or DU

- Send 2 data frames both from both BFM and DUT - Initiate HIBRNATE ENTRY command P0with target set to BFM or DU

Compliance test: Request corruption [0] Do couple of full duplex messages [1] Issue a Power P0 mode change request fr

Compliance test: Request corruption [0] Do couple of full duplex messages [1] Issue a Power P0 mode change request fr

Compliance test: Request corruption [0] Do couple of full duplex messages [1] Issue a Power P0 mode change request fr

Compliance test: Request corruption [0] Do couple of full duplex messages [1] Issue a Power P0 mode change request fr

Compliance test: Request corruption [0] Do couple of full duplex messages [1] Issue a Power P0 mode change request fr

Compliance test: Request corruption [0] Do couple of full duplex messages [1] Issue a Power P0 mode change request fr

Compliance test: Request corruption [0] Do couple of full duplex messages [1] Issue a Power P0 mode change request fr

Compliance test: Request corruption [0] Do couple of full duplex messages [1] Issue a Power P0 mode change request fr

Stimulus: [1] Initiate a Power mode change request from BFM [2] Corruput the PACP frames P0 with EscParam_PA oth - From BFM send - Non PACP_CAP.ind frame after Phase_5 of the Link Initialisation. - Wait P0 for the random delay less

- From BFM send - Non PACP_CAP.ind frame after Phase_5 of the Link Initialisation. - Wait P0 for the random delay less PACP_CAP_ind : Corruptable fields t_sleep_no_config - [3:0] max_pwm - [2:0] P0 max_hs - [1:0]

[1] Issue a PA_LM_PEER_GET/SET.req from the DUT [2] Send the PACP_GET/SET_cnf from P0 BFM containing randomly an

[1] Issue a PA_LM_PEER_GET/SET.req from the DUT [2] Send the PACP_GET/SET_cnf from P0 BFM containing randomly an

Cover hibenrate and non-hibernate cases [1] Initiate Power mode change request from P0 DUT [2] Send the PACP_PW

Cover hibenrate and non-hibernate cases [1] Initiate Power mode change request from P0 DUT [2] Send the PACP_PW

- Start the initialization sequence from both DUT, BFM - From BFM - in Phase 0 for lessP0 than Initialization timer timeo

- Start the initialization sequence from both DUT, BFM - From BFM - in Phase 0 for lessP0 than Initialization timer timeo

- Start the initialization sequence from both DUT, BFM - From BFM - in Phase 0 for lessP0 than Initialization timer timeo

- Start the initialization sequence from both DUT, BFM - From BFM send in Phase 0 till PA_LINKSTARTUP_TIMER P0 timeo

- Start the initialization sequence from both DUT, BFM - Wait for the BFM to receive TRG_UPR0 P0 and move to phase 0b

- Start the initialization sequence from both DUT, BFM - Wait for the BFM to receive TRG_UPR0 P0 and move to phase 0b

- Start the initialization sequence from both DUT, BFM - Wait for the BFM to receive TRG_UPR0 P0 and move to phase 0b

- Start the initialization sequence from both DUT, BFM - From BFM - in Phase 1 for lessP0 than Initialization timer timeo

- Start the initialization sequence from both DUT, BFM - From BFM n Phase 1 keep sending P0 the following till PA_LINK

- Start the initialization sequence from both DUT, BFM - Wait for the BFM to receive TRG_UPR1 P0 and move to phase 0b

- Start the initialization sequence from both DUT, BFM - From BFM - in Phase 3 for lessP0 than Initialization timer timeo

- Start the initialization sequence from both DUT, BFM - From BFM n Phase 3 keep sending P0 the following till PA_LINK - Start the initialization sequence from both DUT, BFM - Wait for the BFM to receive TRG_UPR2 P0 and move to phase 4

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request[2] P0 Donot send PACP_P

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request[2] P0 Donot send PACP_P

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request[2] P0 Donot send PACP_P

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request[2] P0 Donot send PACP_P [1] Send the PACP frames with invalid configurations from BFM side

- Randomize P0the invalid values for all the

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request[2] P0 Send PACP_PWR_cnf

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request[2] P0 Send PACP_PWR_cnf

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request[2] P0 Donot send PACP_PW

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request[2] P0 Donot send PACP_PW For both DUT initiated and BFM Initiated hibernate requests check the normal cases with P0 the User data

- Start off with random HS, LS Mode and random number of lanes supported - From BFM P0Start M-PHY burst by assert

Random hibernate entry and exit requests from BFM or DUT generated with background P0 data traffic. Number of Hiber

Random power mode change requests generated with background data traffic. Number P0 of power mode requests gene

Random power mode change requests generated with background data traffic. Number P0 of power mode requests gene

Random power mode change requests generated with background data traffic. Number P0 of power mode requests gene

Random power mode change requests generated with background data traffic. Number P0 of power mode requests gene

Random power mode change requests generated with background data traffic. Number P0 of power mode requests gene

Random power mode change requests generated with background data traffic. Number P0 of power mode requests gene

Skip the phases and verify the DUT is still responding for the Link Startup The DUT will be P0 receiving all the TRG UPR sym

Skip the phases and verify the DUT is still responding for the Link Startup The DUT will be P0 receiving all the TRG UPR sym

Skip the phases and verify the DUT is still responding for the Link Startup The DUT will be P0 receiving all the TRG UPR sym

Skip the phases and verify the DUT is still responding for the Link Startup The DUT will be P0 receiving all the TRG UPR sym

Skip the phases and verify the DUT is still responding for the Link Startup The DUT will be P0 receiving all the TRG UPR sym

Skip the phases and verify the DUT is still responding for the Link Startup The DUT will be P0 receiving all the TRG UPR sym - Cover the cases of starting before phase 0 - Starting after phase 0 and before phase 5 P0- Different lane configuration - Cover the cases of starting before phase 0 - Starting after phase 0 and before phase 5 P0- Different lane configuration - Cover the cases of starting before phase 0 - Starting after phase 0 and before phase 5 P0- Different lane configuration - Cover the cases of starting before phase 0 - Starting after phase 0 and before phase 5 P0- Different lane configuration - Cover the cases of starting before phase 0 - Starting after phase 0 and before phase 5 P0- Different lane configuration - Cover the cases of starting before phase 0 - Starting after phase 0 and before phase 5 P0- Different lane configuration

- Start the Link Startup sequence from BFM.- Complete the Phase 1/2/3/4 and start sending P0 TRG_UPRO again from BFM

- Start the Link Startup sequence from BFM.- Complete the Phase 1/2/3/4 and start sending P0 TRG_UPRO again from BFM

- Start the Link Startup sequence from BFM.- Complete the Phase 1/2/3/4 and start sending P0 TRG_UPRO again from BFM

- Start the Link Startup sequence from BFM.- Complete the Phase 1/2/3/4 and start sending P0 TRG_UPRO again from BFM

[1] Initiate the Link startup initialization sequence [2] During the different phases injectP0 the

- BAD_PHY_SYMBOL

[1] Initiate the Link startup initialization sequence [2] During the different phases injectP0 the

- BAD_PHY_SYMBOL

[1] Initiate the Link startup initialization sequence [2] During the different phases injectP0 the

- BAD_PHY_SYMBOL

[1] Initiate the Link startup initialization sequence [2] During the different phases injectP0 the

- BAD_PHY_SYMBOL

[1] Initiate the Link startup initialization sequence [2] During the different phases injectP0 the

- BAD_PHY_SYMBOL

[1] Initiate the Link startup initialization sequence [2] During the different phases injectP0 the

- BAD_PHY_SYMBOL

[1] Initiate the Link startup initialization sequence [2] During the different phases injectP0 the

- BAD_PHY_SYMBOL

Scenario#1 - Initalize the Link to Highest gear and highest number of lanes - Do some 2 message P0 from both BFM and D

- Initalize the Link to Highest gear and highest number of lanes - Do some 2 message from P0both BFM and DUT. While t - Send the AFC TCx with Zero credits. Make sure DUT has set the DL_PeerTCxPresent should P0 be set to false- Send the A - Send the AFC TCx with Zero credits. Make sure DUT has set the DL_PeerTCxPresent should P0 be set to false- Send the A - Send the AFC TCx with Zero credits. Make sure DUT has set the DL_PeerTCxPresent should P0 be set to false- Send the A - Send the AFC TCx with Zero credits. Make sure DUT has set the DL_PeerTCxPresent should P0 be set to false- Send the A - Send the AFC TCx with Zero credits. Make sure DUT has set the DL_PeerTCxPresent should P0 be set to false- Send the A - Send the AFC TCx with Zero credits. Make sure DUT has set the DL_PeerTCxPresent should P0 be set to false- Send the A

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet P0 and there on transmit a TC1

- Causing AFCx Transmission from the DUT

P0

- Causing DUT's AFCx_REQUEST_TIMER timeout, by sending number of TCx Data Frame(s) P0 less than DUT's TCxOutAckT

- Causing DUT's AFCx_REQUEST_TIMER timeout, by sending number of TCx Data Frame(s) P0 less than DUT's TCxOutAckT

- Causing DUT's AFCx_REQUEST_TIMER timeout, by sending number of TCx Data Frame(s) P0 less than DUT's TCxOutAckT

[a] FCx_PROTECTION_TIMER Running by sent AFCx with CReq bit set to '1' - Causing DUT's P0 FCx_PROTECTION_TIMER t

[a] FCx_PROTECTION_TIMER Running by sent AFCx with CReq bit set to '1' - Causing DUT's P0 FCx_PROTECTION_TIMER t

[a] FCx_PROTECTION_TIMER Running by sent AFCx with CReq bit set to '1' - Causing DUT's P0 FCx_PROTECTION_TIMER t

[a] FCx_PROTECTION_TIMER Running by sent AFCx with CReq bit set to '1' - Causing DUT's P0 FCx_PROTECTION_TIMER t

[a] FCx_PROTECTION_TIMER Running by sent AFCx with CReq bit set to '1' - Causing DUT's P0 FCx_PROTECTION_TIMER t

- Causing DUT's TCx_REPLAY_TIMER timeout, by stopping to send or droped AFCs. This will P0lead to TCx_REPLAY_TIMER

- Causing DUT's TCx_REPLAY_TIMER timeout, by stopping to send or droped AFCs. This will P0lead to TCx_REPLAY_TIMER

- Cause scenario to trigger the PHY init and cause the PHY init Sequence failure.- This should P0 cause DUT uniprostack to - Send a Data Frame when the DUT TCx does not have any credits to accept the packet.- Send P0 Data Frame of TC which i - Send a Data Frame when the DUT TCx does not have any credits to accept the packet.- Send P0 Data Frame of TC which i - Send a Data Frame when the DUT TCx does not have any credits to accept the packet.- Send P0 Data Frame of TC which i - Send a Data Frame when the DUT TCx does not have any credits to accept the packet.- Send P0 Data Frame of TC which i

- Send a corrupt TC0 data frame- Wait for NAC from DUT- Start the retranmission of the TC0 P0 data frame and cause the

- Successive errors that lead to NAC are caused and single NAC expected. Check TC0 NAC P0 condition fixed by the TC1 co

- Successive errors that lead to NAC are caused and single NAC expected. Check TC0 NAC P0 condition fixed by the TC1 co

- Initiate the change in link properties- Link Properties change from BFM [C] Traffic is present P0 from both Tx and Rx side

- Initiate the change in link properties- Link Properties change from BFM [C] Traffic is present P0 from both Tx and Rx side

- Initiate the change in link properties- Link Properties change from BFM [C] Traffic is present P0 from both Tx and Rx side

- Initiate the change in link properties- Link Properties change from BFM [C] Traffic is present P0 from both Tx and Rx side

- Initiate the change in link properties- Link Properties change from BFM/DUT [B] No Traffic P0 from Tx (i.e. No Data Fram

- Initiate the change in link properties- Link Properties change from BFM/DUT [B] No Traffic P0 from Tx (i.e. No Data Fram

- Initiate the change in link properties- Link Properties change from BFM/DUT [B] No Traffic P0 from Tx (i.e. No Data Fram

- Initiate the change in link properties- Link Properties change from BFM/DUT [B] No Traffic P0 from Tx (i.e. No Data Fram

- Initiate the change in link properties- Link Properties change from BFM/DUT [B] No Traffic P0 from Tx (i.e. No Data Fram

- Initiate the change in link properties- Link Properties change from BFM/DUT [B] No Traffic P0 from Tx (i.e. No Data Fram

- Initiate the change in link properties- Link Properties change from BFM [C] Traffic is present P0 from both Tx and Rx side

- Initiate the change in link properties- Link Properties change from BFM [C] Traffic is present P0 from both Tx and Rx side

- Initiate the change in link properties- Link Properties change from BFM [C] Traffic is present P0 from both Tx and Rx side

- Initiate the change in link properties- Link Properties change from BFM [C] Traffic is present P0 from both Tx and Rx side

- Initiate the change in link properties- Link Properties change from BFM/DUT [A] No Traffic P0 from Tx and Rx (i.e. No Da

- Initiate the change in link properties- Link Properties change from BFM/DUT [A] No Traffic P0 from Tx and Rx (i.e. No Da Ability to issue this randomly.- Cause Warm reset and check if the DL statistics are retained. P0 Ability to issue this randomly.- Cause Warm reset and check if the DL statistics are retained. P0 - Drop sending some number of AFCs for the correctly received frames. As credits are self P0 healing DUT should be able

- Drop sending some number of AFCs for the correctly received frames. As credits are self P0 healing DUT should be able - Send Duplicate AFCx, i.e. Send more than one Acknowledgement back2back of Correctly P0 Received L2 Data FrameUse - Send Duplicate AFCx, i.e. Send more than one Acknowledgement back2back of Correctly P0 Received L2 Data FrameUse

- Send Duplicate AFCx, i.e. Send more than one Acknowledgement back2back of Correctly P0 Received L2 Data FrameUse - Send Duplicate AFCx, i.e. Send more than one Acknowledgement back2back of Correctly P0 Received L2 Data FrameUse - Send Duplicate AFCx, i.e. Send more than one Acknowledgement back2back of Correctly P0 Received L2 Data FrameUse

- Transmit TCx Data Frame from BFM according to DUT's TCxOutAckThreshold i.e. if DUT's P0TCxOutAckThreshold is set t

- Transmit TCx Data Frame from BFM according to DUT's TCxOutAckThreshold i.e. if DUT's P0TCxOutAckThreshold is set t

- Transmit TCx Data Frame from BFM according to DUT's TCxOutAckThreshold i.e. if DUT's P0TCxOutAckThreshold is set t

- Dont send the AFC For TC1 till the FCx_PROTECTION_TIMER times out- Send TC1 AFC within P0 timeout but dont send th

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response - Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption P0 ScenarioExpected Response

- Idea is tc0 data frame is preempted by tc1 data frame and tc1 data frame is again preempted P0 by control frame and on

- Idea is tc0 data frame is preempted by tc1 data frame and tc1 data frame is again preempted P0 by control frame and on

- Transmit Receives N randomized transfer between 1 to DL_MTU and ACKs are randmoly P0 grouped up to 16 packets an

- Transmit and Receives N randomized transfer between 1 to DL_MTU and ACKs are randmoly P0 grouped up to 16 packe

- Transmit and Receives N randomized transfer between 1 to DL_MTU and ACKs are randmoly P0 grouped up to 16 packe

- Receives N transactors(packets/frames) with random data payload size between 1 to DL_MTU P0 and ACKs immediately

- Receives N transactors(packets/frames) with random data payload size between 1 to DL_MTU P0 and ACKs immediately

- Receives N transactors(packets/frames) with random data payload size between 1 to DL_MTU P0 and ACKs immediately

- Transmits and Receives N transactors(packets/frames) with random data payload size between P0 1 to DL_MTU and ACK

- Transmits and Receives N transactors(packets/frames) with random data payload size between P0 1 to DL_MTU and ACK

- Transmits and Receives N transactors(packets/frames) with random data payload size between P0 1 to DL_MTU and ACK

- Transmits and Receives N transactors(packets/frames) with random data payload size between P0 1 to DL_MTU and ACK

- Transmits and Receives N transactors(packets/frames) with random data payload size between P0 1 to DL_MTU and ACK

- Transmits and Receives N transactors(packets/frames) with random data payload size between P0 1 to DL_MTU and ACK - Transmits N transactors(packets/frames) with random data payload size between 1 to DL_MTUStimulus: P0 BFM TX tran - Transmits N transactors(packets/frames) with random data payload size between 1 to DL_MTUStimulus: P0 BFM TX tran - Transmits N transactors(packets/frames) with random data payload size between 1 to DL_MTUStimulus: P0 BFM TX tran - Injecting any applicable random error on L2 TransactorsStimulus: BFM TX will do random P0error injectionResponse: - Injecting any applicable random error on L2 TransactorsStimulus: BFM TX will do random P0error injectionResponse:

- Idea here is to simulate scenario where the BFM experiences the FCx_PROTECTION_TIMERP0 Instead of starting with th - Reception of PA_ERROR_ind, NAC is expected from the DUT User Interface:- NAExpected P0 Response from DUT:- NAC - PHY init due to NAC frame with RReq bit set - PHY init due to FCx_PROTECTION_TIMER P0 expiry - PHY init due to TCx_ - Corrupt Reserved Bits- Now, At DUT Rx side Reserved bits will be ignored- So, DUT Rx will P0just ignore these corrupted - Corrupt Reserved Bits- Now, At DUT Rx side Reserved bits will be ignored- So, DUT Rx will P0just ignore these corrupted - Corrupt Reserved Bits- Now, At DUT Rx side Reserved bits will be ignored- So, DUT Rx will P0just ignore these corrupted - Corrupt Reserved Bits- Now, At DUT Rx side Reserved bits will be ignored- So, DUT Rx will P0just ignore these corrupted

- Sending AFC frame of those frame, which started replaying - i.e. Pause AFC transmission P0 at BFM untill DUT end start

- Sending AFC frame of those frame, which started replaying - i.e. Pause AFC transmission P0 at BFM untill DUT end start

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected P0 from the DUT User In

- Transmit COF symbol for different TC than it supposed to - e.g. SOF symbol with TC=0, DATA, P0 COF symbol with TC=1U

- Transmit COF symbol for different TC than it supposed to - e.g. SOF symbol with TC=0, DATA, P0 COF symbol with TC=1U

- Transmit COF symbol for different TC than it supposed to - e.g. SOF symbol with TC=0, DATA, P0 COF symbol with TC=1U

- Transmit COF symbol for different TC than it supposed to - e.g. SOF symbol with TC=0, DATA, P0 COF symbol with TC=1U

- There arent any pre-emption.- TC0 data frame is in progress and COF is received. - TC1 data P0 frame is in progress and C

- There arent any pre-emption.- TC0 data frame is in progress and COF is received. - TC1 data P0 frame is in progress and C

- There arent any pre-emption.- TC0 data frame is in progress and COF is received. - TC1 data P0 frame is in progress and C

- There arent any pre-emption.- TC0 data frame is in progress and COF is received. - TC1 data P0 frame is in progress and C - AFC and NAC with corrupted CRC-16User Interface:- NAExpected Response from DUT:- Drop P0 that Frame and transmit - AFC and NAC with corrupted CRC-16User Interface:- NAExpected Response from DUT:- Drop P0 that Frame and transmit - AFC and NAC with corrupted CRC-16User Interface:- NAExpected Response from DUT:- Drop P0 that Frame and transmit - AFC and NAC with corrupted CRC-16User Interface:- NAExpected Response from DUT:- Drop P0 that Frame and transmit - AFC and NAC with corrupted CRC-16User Interface:- NAExpected Response from DUT:- Drop P0 that Frame and transmit - AFC and NAC with corrupted CRC-16User Interface:- NAExpected Response from DUT:- Drop P0 that Frame and transmit - AFC and NAC with corrupted CRC-16User Interface:- NAExpected Response from DUT:- Drop P0 that Frame and transmit

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value P0 except 8'b00000001Expected

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved. User Interface:P0 Choose between an

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.User Interface:P0 User can choose any one

- Corrupt Reserved Bits of SOF/COF Control Symbol- Now, At DUT Rx side Reserved bits will P0 be ignored- So, DUT Rx will

- Corrupt Reserved Bits of SOF/COF Control Symbol- Now, At DUT Rx side Reserved bits will P0 be ignored- So, DUT Rx will

- Corrupt Reserved Bits of SOF/COF Control Symbol- Now, At DUT Rx side Reserved bits will P0 be ignored- So, DUT Rx will

- Corrupt Reserved Bits of SOF/COF Control Symbol- Now, At DUT Rx side Reserved bits will P0 be ignored- So, DUT Rx will

- Corrupt Reserved Bits of SOF/COF Control Symbol- Now, At DUT Rx side Reserved bits will P0 be ignored- So, DUT Rx will

- Corrupt Reserved Bits of SOF/COF Control Symbol- Now, At DUT Rx side Reserved bits will P0 be ignored- So, DUT Rx will

- Corrupt Reserved Bits of SOF/COF Control Symbol- Now, At DUT Rx side Reserved bits will P0 be ignored- So, DUT Rx will

- Corrupt Reserved Bits of SOF/COF Control Symbol- Now, At DUT Rx side Reserved bits will P0 be ignored- So, DUT Rx will

- Transmits data frame whose size is greater than the DL_SYMBOL_MTU User Interface:- NAExpected P0 Response from D

- Transmits data frame whose size is greater than the DL_SYMBOL_MTU User Interface:- NAExpected P0 Response from D

- Transmits data frame whose size is greater than the DL_SYMBOL_MTU User Interface:- NAExpected P0 Response from D

- Transmits data frame whose size is greater than the DL_SYMBOL_MTU User Interface:- NAExpected P0 Response from D - Transmits data frame with corrupt CRC and expects a NAC response from the DUTUser Interface:P0 NAExpected Respon - Transmits data frame with corrupt CRC and expects a NAC response from the DUTUser Interface:P0 NAExpected Respon - Transmits data frame with corrupt CRC and expects a NAC response from the DUTUser Interface:P0 NAExpected Respon - Transmits data frame with corrupt CRC and expects a NAC response from the DUTUser Interface:P0 NAExpected Respon - Transmits data frame with corrupt CRC and expects a NAC response from the DUTUser Interface:P0 NAExpected Respon - Transmits data frame with corrupt CRC and expects a NAC response from the DUTUser Interface:P0 NAExpected Respon

- Transmits data frame with the the Sequence number that is already ACKedUser Interface:P0 NAExpected Response from

- Transmits data frame with the the Sequence number that is already ACKedUser Interface:P0 NAExpected Response from

- Transmits data frame with the the Sequence number that is already ACKedUser Interface:P0 NAExpected Response from

- Transmits data frame with the the Sequence number that is already ACKedUser Interface:P0 NAExpected Response from

- Transmits data frame with a random incorrect Sequence number and expects a NAC response P0 from DUTUser Interfac

- Transmits data frame with a random incorrect Sequence number and expects a NAC response P0 from DUTUser Interfac

- Transmits data frame with a random incorrect Sequence number and expects a NAC response P0 from DUTUser Interfac

- Transmits data frame with a random incorrect Sequence number and expects a NAC response P0 from DUTUser Interfac

- Transmits data frame with a random incorrect Sequence number and expects a NAC response P0 from DUTUser Interfac

- Drop COF control symbol of resuming L2 frameUser Interface:- NAExpected Response from P0 DUT:- NAC transmissionRe

- Drop COF control symbol of resuming L2 frameUser Interface:- NAExpected Response from P0 DUT:- NAC transmissionRe

- Drop COF control symbol of resuming L2 frameUser Interface:- NAExpected Response from P0 DUT:- NAC transmissionRe

- Drop COF control symbol of resuming L2 frameUser Interface:- NAExpected Response from P0 DUT:- NAC transmissionRe

- Transmit some symbols out of total symbols of L2 Data Frame - e.g. EOF_EVEN/EOF_ODD P0 without CRC symbol, NAC i

- Transmit some symbols out of total symbols of L2 Data Frame - e.g. EOF_EVEN/EOF_ODD P0 without CRC symbol, NAC i

- Transmit some symbols out of total symbols of L2 Data Frame - e.g. EOF_EVEN/EOF_ODD P0 without CRC symbol, NAC i

- Transmit some symbols out of total symbols of L2 Data Frame - e.g. EOF_EVEN/EOF_ODD P0 without CRC symbol, NAC i

- Transmit some symbols out of total symbols of L2 Data Frame - e.g. EOF_EVEN/EOF_ODD P0 without CRC symbol, NAC i

- Transmit some symbols out of total symbols of L2 Data Frame - e.g. EOF_EVEN/EOF_ODD P0 without CRC symbol, NAC i - AFCx symbol without the last two data symbols, NAC expected from the DUTUser Interface:P0 AFCx Frame without last - AFCx symbol without the last two data symbols, NAC expected from the DUTUser Interface:P0 AFCx Frame without last - AFCx symbol without the last two data symbols, NAC expected from the DUTUser Interface:P0 AFCx Frame without last - AFCx symbol without the last two data symbols, NAC expected from the DUTUser Interface:P0 AFCx Frame without last - NAC symbol without the last data symbol, NAC expected from the DUTUser Interface:- NAExpected P0 Response from DU - NAC symbol without the last data symbol, NAC expected from the DUTUser Interface:- NAExpected P0 Response from DU

- Send NAC when there are nooutstanding frames to be acked.User Interface:- NAExpected P0 Response from DUT:- Trans

- Send NAC when there are nooutstanding frames to be acked.User Interface:- NAExpected P0 Response from DUT:- Trans

- Send the NAC randmomly when there are outstadnding Frames to be acknowledged.User P0 Interface:- NAExpected Res

- Send the NAC randmomly when there are outstadnding Frames to be acknowledged.User P0 Interface:- NAExpected Res

- BFM transmits NAC randomly after receiving random data frames less than 16 and thenP0 ACK the Data frames reques

- BFM transmits NAC randomly after receiving random data frames less than 16 and thenP0 ACK the Data frames reques

- BFM transmits NAC randomly after receiving random data frames less than 16 and thenP0 ACK the Data frames reques

- BFM transmits NAC randomly after receiving random data frames less than 16 and thenP0 ACK the Data frames reques - Corrupt Reserved Bits- Now, At DUT Rx side Reserved bits will be ignored- So, DUT Rx will P0just ignore these corrupted

- Send SOF instead COF control symbol while resuming L2 frameUser Interface:- NAExpected P0 Response from DUT:- NAC

- Send SOF instead COF control symbol while resuming L2 frameUser Interface:- NAExpected P0 Response from DUT:- NAC

- Send SOF instead COF control symbol while resuming L2 frameUser Interface:- NAExpected P0 Response from DUT:- NAC

- Send SOF instead COF control symbol while resuming L2 frameUser Interface:- NAExpected P0 Response from DUT:- NAC

- Pre-Emption happen between same TCx - TCO SOF sent when the TC0 data frame is in progress. P0 - TC1 SOF sent whe

- Pre-Emption happen between same TCx - TCO SOF sent when the TC0 data frame is in progress. P0 - TC1 SOF sent whe

- Pre-Emption happen between same TCx - TCO SOF sent when the TC0 data frame is in progress. P0 - TC1 SOF sent whe

- Pre-Emption happen between same TCx - TCO SOF sent when the TC0 data frame is in progress. P0 - TC1 SOF sent whe

- TC0 SOF sent when the TC1 data frame is in progress. User Interface:- NAExpected Response P0 from DUT:- Drop both Fr

- TC0 SOF sent when the TC1 data frame is in progress. User Interface:- NAExpected Response P0 from DUT:- Drop both Fr

- TC0 SOF sent when the TC1 data frame is in progress. User Interface:- NAExpected Response P0 from DUT:- Drop both Fr

- Transmit TCx Data Frame with data payload of non integral mutilple of 32 bytesExpected P0 Response from DUT:- DUT ha

- Transmit TCx Data Frame with data payload of non integral mutilple of 32 bytesExpected P0 Response from DUT:- DUT ha

- Transmit TCx Data Frame with data payload of non integral mutilple of 32 bytesExpected P0 Response from DUT:- DUT ha

- Transmit TCx Data Frame with data payload of non integral mutilple of 32 bytesExpected P0 Response from DUT:- DUT ha

- Transmit TCx Data Frame with data payload of non integral mutilple of 32 bytesExpected P0 Response from DUT:- DUT ha

- Transmit TCx Data Frame with data payload of non integral mutilple of 32 bytesExpected P0 Response from DUT:- DUT ha - Send the AFC with CReq bit set and the AFC response should be received by the DUT.User P0 Interface:- NAExpected Res - Send the AFC with CReq bit set and the AFC response should be received by the DUT.User P0 Interface:- NAExpected Res - Send the AFC with CReq bit set and the AFC response should be received by the DUT.User P0 Interface:- NAExpected Res - Send the AFC with CReq bit set and the AFC response should be received by the DUT.User P0 Interface:- NAExpected Res - unexpected framing Sequence - data symbol received between frames - Back2Back Control P0 Symbols (SOF,AFC,EOF,CO - unexpected framing Sequence - data symbol received between frames - Back2Back Control P0 Symbols (SOF,AFC,EOF,CO - unexpected framing Sequence - data symbol received between frames - Back2Back Control P0 Symbols (SOF,AFC,EOF,CO - unexpected framing Sequence - data symbol received between frames - Back2Back Control P0 Symbols (SOF,AFC,EOF,CO

- A SOF symbol during an ongoing Frame of the same TC is permitted when a replay starts, P0but only when the Frame i

- A SOF symbol during an ongoing Frame of the same TC is permitted when a replay starts, P0but only when the Frame i

- Causing TC1 Credit blocking and meanwhile TC0 has enough Credits to transmit TC0 Data P0FramesStimulus: BFM Confi

- Causing TC1 FSN blocking and meanwhile TC0 Data Frames can make progressStimulus:P0 DUT Config have ACK Groupin Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over P0 TC0 Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over P0 TC0 Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over P0 both the TC0 and TC1.

Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over P0 TC0

Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over P0 TC0

Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over P0 TC0

Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over P0 TC0

Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over P0 both the TC0 and TC1 wit

Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over P0 both the TC0 and TC1 wit

Send long header packet to DUT and it should discard it when its not supporting the longP0 headers. And check for the LH Transmit Packet to DUT with the DeviceID not supported by the DUT. DUT is expected to discard P0 the Packet and report Transmit Packet to DUT with the DeviceID not supported by the DUT. DUT is expected to discard P0 the Packet and report Transmit Packet to DUT with the DeviceID not supported by the DUT. DUT is expected to discard P0 the Packet and report

Transmit Packet to DUT with the DeviceID not supported by the DUT. DUT is expected to discard P0 the Packet and report 1. Test verifies the connection management by connecting cports from both the sides, and P0 do one data transfer and v Tranasmits a msg on cport of status indication of NO_PEER_TC. RESPONSE: result code shall P0 be NO_PEER_TC

Tranasmits a msg with multiple msg fragment with t_tx_eom is not set for msg fragment P0 of zero size. RESPONSE: FRAG

Tranasmits fc req in continious cycle, get the t_tx_result code = CREDIT EXCEED on INTERFACE P0 and t_credit_accepted =

Disable the E2E flow control. Tranasmits N randomized segments (T_PDUs) between 1 to P0implementation defined arb

Disable the E2E flow control. Tranasmits N randomized segments (T_PDUs) between 1 to P0implementation defined arb

Disable the E2E flow control. Tranasmits N randomized segments (T_PDUs) between 1 to P0implementation defined arb

Disable the E2E flow control. Tranasmits N randomized segments (T_PDUs) between 1 to P0implementation defined arb

Random connect and disocnnect is enabled. DUT Cports will be connected to random CPort P0 and TCx of the BFM Ran

Random connect and disocnnect is enabled. DUT Cports will be connected to random CPort P0 and TCx of the BFM Ran

Random connect and disocnnect is enabled. DUT Cports will be connected to random CPort P0 and TCx of the BFM Ran

Random connect and disocnnect is enabled. DUT Cports will be connected to random CPort P0 and TCx of the BFM Ran

Tranasmits and receive 1 randomized message (T_SDUs) with sequential data payload of P0 fixed size from DUT.Stimulus

Tranasmits and receive 1 randomized message (T_SDUs) with sequential data payload of P0 fixed size from DUT.Stimulus

Transmit a segment with the correct size, correct TC with the incorrect DestCPortID, it will P0 be discarded by DUT.Stimu

Transmit a segment with the correct size, correct TC with the incorrect DestCPortID, it will P0 be discarded by DUT.Stimu Transmit a segment with the correct size but with the incorrct TCStimulus: - Test app tx P0 message (T_SDUs) to BFM. Transmit a segment with the correct size but with the incorrct TCStimulus: - Test app tx P0 message (T_SDUs) to BFM. -

Send the Segment without any payload and EOM set. Send a new segment followed by P0 it. Things should function nor

Send the Segment without any payload and EOM set. Send a new segment followed by P0 it. Things should function nor

Send the Segment without any payload and EOM set. Send a new segment followed by P0 it. Things should function nor

Establish the connection with the CPortID greater than 31. Transmit and receive the Segments. P0 DeviceIDOffset will be

Establish the connection with the CPortID greater than 31. Transmit and receive the Segments. P0 DeviceIDOffset will be

Transmit the segment with the FCT set in segments with payload and without payload. P0 DUT is expected to drop the s

Transmit the segment with the FCT set in segments with payload and without payload. P0 DUT is expected to drop the s Transmit the segment with the L4s=0 from BFM and DUT is expected to discrad and send P0 the notification.Stimulus: Transmit the segment with the L4s=0 from BFM and DUT is expected to discrad and send P0 the notification.Stimulus:

Transmit a correct data segment with FCT=0 when DUT is not in the CONNECTED state P0 Transmit a correct data segme

Transmit a correct data segment with FCT=0 when DUT is not in the CONNECTED state P0 Transmit a correct data segme

Transmit the zero sized segment with the EOM set to false.Stimulus: - Test app tx message P0 (T_SDUs) with zero size to

Transmit the zero sized segment with the EOM set to false.Stimulus: - Test app tx message P0 (T_SDUs) with zero size to

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary P0 length defined by (T_M

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary P0 length defined by (T_M

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary P0 length defined by (T_M

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary P0 length defined by (T_M

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary P0 length defined by (T_M

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary P0 length defined by (T_M

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary P0 length defined by (T_M

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary P0 length defined by (T_M

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary P0 length defined by (T_M

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary P0 length defined by (T_M

Transmit a segment with the size greater than T_MTU. The DUT must discard it.Stimulus: P0- Test app tx message (T_SD

Transmit a segment with the size greater than T_MTU. The DUT must discard it.Stimulus: P0- Test app tx message (T_SD

Transmit a segment with the less than T_MTU with out EOM bit to set The DUT must discard P0 it.Stimulus: - Test app tx

Transmit a segment with the less than T_MTU with out EOM bit to set The DUT must discard P0 it.Stimulus: - Test app tx

Corrupt the CportID.Take the specific error percentage from the command line for corrupting P0 CportID and randomly in

Corrupt the CportID.Take the specific error percentage from the command line for corrupting P0 CportID and randomly in

Corrupt the CportID.Take the specific error percentage from the command line for corrupting P0 CportID and randomly in

Corrupt the CportID.Take the specific error percentage from the command line for corrupting P0 CportID and randomly in Corrupt the TC.Take the specific error percentage from the command line for corrupting P0 TC and randomly inject the er Corrupt the TC.Take the specific error percentage from the command line for corrupting P0 TC and randomly inject the er Corrupt the TC.Take the specific error percentage from the command line for corrupting P0 TC and randomly inject the er Corrupt the TC.Take the specific error percentage from the command line for corrupting P0 TC and randomly inject the er Corrupt the EOM.Take the specific error percentage from the command line and randomly P0 inject the error into the seg Corrupt the EOM.Take the specific error percentage from the command line and randomly P0 inject the error into the seg Corrupt the EOM.Take the specific error percentage from the command line and randomly P0 inject the error into the seg Corrupt the EOM.Take the specific error percentage from the command line and randomly P0 inject the error into the seg Corrupt the FC.Take the specific error percentage from the command line and randomly P0 inject the error into the segm Corrupt the FC.Take the specific error percentage from the command line and randomly P0 inject the error into the segm Corrupt HDR .Take the specific error percentage from the command line and randomly inject P0 the error into the segme Corrupt HDR .Take the specific error percentage from the command line and randomly inject P0 the error into the segme Corrupt HDR .Take the specific error percentage from the command line and randomly inject P0 the error into the segme Corrupt HDR .Take the specific error percentage from the command line and randomly inject P0 the error into the segme Corrupt the DATA PAYLOAD SIZE.Take the specific error percentage from the command line P0 for corrupting msg data pay Corrupt the DATA PAYLOAD SIZE.Take the specific error percentage from the command line P0 for corrupting msg data pay Corrupt the DATA PAYLOAD SIZE.Take the specific error percentage from the command line P0 for corrupting msg data pay Corrupt the DATA PAYLOAD SIZE.Take the specific error percentage from the command line P0 for corrupting msg data pay

Take the specific error percentage from the command line and randomly inject the errorP0 into the segment on the basi

Take the specific error percentage from the command line and randomly inject the errorP0 into the segment on the basi

Take the layer error percentage from the command line and randomly inject the error into P0 the segment on the basis o

Take the layer error percentage from the command line and randomly inject the error into P0 the segment on the basis o

Take the specific layer percentage from the command line and randomly inject the errorP0 into the segment on the basi

Take the specific error percentage from the command line and randomly inject the errorP0 into the segment on the basi

Take the specific error percentage from the command line and randomly inject the errorP0 into the segment on the basi

Take the specific error percentage from the command line and randomly inject the errorP0 into the segment on the basi

Stimulus: Response: Stimulus: Response:

P0 P0

Consume part of the credits advertised. Then send an segment with the size greater than P0the credits available at DU

Consume part of the credits advertised. Then send an segment with the size greater than P0the credits available at DU

Consume part of the credits advertised. Then send an segment with the size greater than P0the credits available at DUT

Consume part of the credits advertised. Then send an segment with the size greater than P0the credits available at DUT

Consume all the credits advertised. Then send an segment when the zero credits are available P0 to DUT.Segment will b

Consume all the credits advertised. Then send an segment when the zero credits are available P0 to DUT.Segment will b

Consume all the credits advertised by app at RX side. Then send an segment when the zero P0 credits are available to DU

Consume all the credits advertised by app at RX side. Then send an segment when the zero P0 credits are available to DU Test verifies the error codes with the test features like no error, fragment corrupt, invalidP0 message size and unexpected Programs the following parameters and checks that the recieved data is as per the requirementP0 T_TstSrcOn- T_TstSrcM Programs the following parameters and checks that the recieved data is as per the requirementP0 T_TstSrcOn- T_TstSrcM

Programs the following parameters and checks that the recieved data is as per the requirementP0 T_TstSrcOn- T_TstSrcM

Programs the following parameters and checks that the recieved data is as per the requirementP0 T_TstSrcOn- T_TstSrcM

Programs the following parameters and checks that the recieved data is as per the requirementP0 T_TstSrcOn- T_TstSrcM

Programs the following parameters and checks that the recieved data is as per the requirementP0 T_TstSrcOn- T_TstSrcM Only applicable for the DUT [0] Do the Register Write/Read operations in RTL for all UniPro P0 Registers

Addr Valid ra

[1] Read and store the attributes expected to be restored before hibernate entry [2] Initiate P0 hibernate entry. Wait fo

Start a custom dme write and, then, a read sequence that writes/reads one of the registers(ATTID_DL_TC0TXFCThresho P0

[1] Initialize the DUT with random power mode [2] Inject some errors from BFM to change P0 the error counters and erro

Only applicable for the DUT [0] Do the Register Write/Read operations in RTL for all UniPro P0 Registers Addr Valid ra DME LM_SET_* / LM_GET_* functionsStimulus: Do the Register Write/Read operations P0 by using PA_LM_SET.req & Start user DUT INIT sequence(unipro_user_dut_init_sequence) by overriding the spec_attrb P0 DUT INIT(unipro_dut_init_

Start user CPORT CONNECT sequence(unipro_user_cport_connect_seq) by overriding the P0 spec_attrb CPORT CONNECT

Start a custom dme write and, then, a read sequence that writes/reads one of the registers(ATTID_DL_TC0TXFCThresho P0

STATUS
NYET NYET NYET

NYET

NYET

NYET NYET NYET NYET

NYET

NYET NYET NYET NYET NYET NYET NYET

NYET

NYET

NYET

NYET

NYET

NYET

NYET

NYET

NYET NYET

NYET NYET

NYET NYET

NYET

NYET

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LAYER
L1P5

SECTION
L1P5 PHY testing

TEST
2 custom power mode change test

L1P5

L1P5 Error Injection - M-PHY related Cases

3b4b_Error 5b6b_Error and RD_Error from BFM Tx side

L1P5

L1P5 e_rr_or Injection Initialization Sequences

All Phase : Corrupted TRG_UPRx from BFM for all Phase

L1P5

L1P5 Reset Scenarios (LINERESET & Warm Reset)

BFM LINE-RESET with PACP_PWR_Req & PACP_REQUEST_TIMER timeout attempt#2(LINERESET)

L1P5

L1P5 INIT Sceanarios

BFM not starting the LINKSTARTUP till the DUT timeout

L1P5

L1P5 PHY testing

CJTPAT and CRPAT packets corruption from BFM side

L1P5

L1P5 Error Injection - Framing Errors

Deskew pattern in the middle of Data frame

L1P5

L1P5 Reset Scenarios (LINERESET & Warm Reset)

DME L1P5 Initialisation Sequence DUT Abort

L1P5

L1P5 Reset Scenarios (LINERESET & Warm Reset)

DUT LINE-RESET with PACP_PWR_Req & PACP_REQUEST_TIMER timeout attempt#2(LINERESET)

L1P5

L1P5 Low Power Scenarios

DUT Power Mode Change Errors - (PWR_BUSYPWR_ERROR_CAP-PWR_OK)

L1P5

L1P5 Low Power Scenarios

DUT Power Mode Change Errors - Concurrency Resolution

L1P5

L1P5 Low Power Scenarios

DUT Power Mode Change Errors - Concurrency Resolution(DEV_ID)

L1P5

L1P5 PHY testing

DUT reject Local invalid power request

L1P5

L1P5 Reset Scenarios (LINERESET & Warm Reset)

Endpoint reset from BFM (TRG_EPR)

L1P5

L1P5 Reset Scenarios (LINERESET & Warm Reset)

Endpoint reset from DUT (TRG_EPR)

L1P5

L1P5 Error Injection - Framing Errors

Errored frame Transfers - EOB Corruption

L1P5

L1P5 Error Injection - Framing Errors

Errored frame Transfers - FILLER Corruption(UNEXPECTED_PHY_ESC_SYMBOL insertion)

L1P5

L1P5 Error Injection - Framing Errors

Errored frame Transfers - SOB Corruption

L1P5

L1P5 Error Injection - Framing Errors

Errored frame Transfers - SOB Corruption During LinkStartup sequence

L1P5

L1P5 Error Injection - M-PHY related Cases

Frame Transfers with Res_Error Error

L1P5

L1P5 e_rr_or Injection Initialization Sequences

Initialisation Sequence Abort due to DUT power mode updates to HIBERN8 or OFFMODE

L1P5

L1P5 INIT Sceanarios

L1p5 Initialisation Sequence start and Lock and Unlock the BFM INIT phases with the valid random delays

L1P5

L1P5 INIT Sceanarios

L1p5 Initialisation Sequence start on DUT and BFM simultaneously

L1P5

L1P5 INIT Sceanarios

L1p5 Link Startup Sequence start on BFM end after power on reset

L1P5

L1P5 INIT Sceanarios

L1p5 Link Startup Sequence start on DUT end after power on reset

L1P5

L1P5 Error Injection - Framing Errors

Lane to Lane skew exceeding more than two PA symbols

L1P5

L1P5 Reset Scenarios (LINERESET & Warm Reset)

LINE-RESET with PA_INIT.req from BFMs DL

L1P5

L1P5 Reset Scenarios (LINERESET & Warm Reset)

LINE-RESET with PA_INIT.req from DUTs DL

L1P5

L1P5 DME Access

LM_PEER_SET_* & LM_PEER_GET_* PEER_COMMUNICATION_FAILURE

L1P5

L1P5 DME Access

LM_PEER_SET_* & LM_PEER_GET_* ConfigResultCode other than SUCCESS

L1P5

L1P5 DME Access

LM_PEER_SET_* & LM_PEER_GET_* Transfers from BFM and DUT ConfigResultCode SUCCESS

L1P5

L1P5 Low Power Scenarios

LS -> HS -> LS request from BFM and DUT

L1P5

L1P5 Error Injection - PACP Frame fields/Sequences

New PACP frame Transmission before finishing current PACP frame

L1P5

L1P5 Normal frame transfers

Normal frame Transfers with DIFFERENT MODE AND GEAR

L1P5

L1P5 Normal frame transfers

Normal frame transmit on different Lanes

L1P5

L1P5 PHY testing

Not changing PA_POWERMODE bit for long duration of time and having data traffic inbetween

L1P5

L1P5 INIT Sceanarios

PA_INIT Sequence Re-initiated from DUT-DL control

L1P5

L1P5 Low Power Scenarios

PA_LM_HIBERNATE_ENTER/EXIT from BFM/DUT

L1P5

L1P5 Error Injection - PACP Frame fields/Sequences

PACP frame Transmission with CRC Errors

L1P5

L1P5 Error Injection - PACP Frame fields/Sequences

PACP frame Transmission with EscParam_PA error

L1P5

L1P5 e_rr_or Injection Initialization Sequences

PACP_CAP frame corruption with non PACP_CAP frame

L1P5

L1P5 Error Injection - PACP Frame fields/Sequences

PACP_CAP_ind frame Transmission with field corruption

L1P5

L1P5 Error Injection - PACP Frame fields/Sequences

PACP_GET/SET_cnf frame Transmission with ConfigResultCode other than SUCCESS from BFM

L1P5

L1P5 Error Injection - PACP Frame fields/Sequences

PACP_PWR_cnf PWR_BUSY/PWR_ERROR_CAP from BFM

L1P5

L1P5 e_rr_or Injection Initialization Sequences

Phase 0 : Corrupted TRG_UPR0 followed by correct TRG_UPRO from BFM

L1P5

L1P5 e_rr_or Injection Initialization Sequences

Phase 0 : Corrupted TRG_UPR0 till PA_LINKSTARTUP_TIMER timeout

L1P5

L1P5 e_rr_or Injection Initialization Sequences

Phase 0b : Corrupted TRG_UPR0 from BFM

L1P5

L1P5 e_rr_or Injection Initialization Sequences

Phase 1 : Corrupted TRG_UPR1 followed by correct TRG_UPR1 from BFM

L1P5

L1P5 e_rr_or Injection Initialization Sequences

Phase 1 : Corrupted TRG_UPR1 till PA_LINKSTARTUP_TIMER timeout

L1P5

L1P5 e_rr_or Injection Initialization Sequences

Phase 2 : Corrupted TRG_UPR1 from BFM

L1P5

L1P5 e_rr_or Injection Initialization Sequences

Phase 3 : Corrupted TRG_UPR2 followed by correct TRG_UPR2 from BFM

L1P5

L1P5 e_rr_or Injection Initialization Sequences

Phase 3 : Corrupted TRG_UPR2 till PA_LINKSTARTUP_TIMER timeout

L1P5

L1P5 e_rr_or Injection Initialization Sequences

Phase 4 : Corrupted TRG_UPR2 from BFM

L1P5

L1P5 Low Power Scenarios

Power Mode Change Errors PACP_REQUEST_TIMER Timeout - attempt#3 (PWR_FATAL_ERROR)

L1P5

L1P5 Low Power Scenarios

Power Mode Change Errors - Invalid configuration detection

L1P5

L1P5 Low Power Scenarios

Power Mode Change Errors PA_PACPReqEoBTimeout

L1P5

L1P5 Low Power Scenarios

Power Mode Change Errors PACP_REQUEST_TIMER Timeout attempt#1

L1P5

L1P5 Low Power Scenarios

Power Mode Change PA_PWRModeUserData testing

L1P5

L1P5 Error Injection - Framing Errors

Random data before Deskew pattern before the Start of burst

L1P5

L1P5 Low Power Scenarios

Random Hibernate entry and exit request from BFM or DUT

L1P5

L1P5 Low Power Scenarios

Random Power Mode Change request from BFM or DUT

L1P5

L1P5 e_rr_or Injection Initialization Sequences

Skip the Phases optional in the Link Startup Sequence

L1P5

L1P5 PHY testing

Test mode initiated from BFM

L1P5

L1P5 INIT Sceanarios

TRG_UPR0 from BFM during Link Init phase 1 2 3 4

L1P5

L1P5 INIT Sceanarios

Various Symbol errors during the init sequence

L1P5

L1P5 INIT Sceanarios

WARM_RESET during Data transfer to BFM

L1P5

L1P5 INIT Sceanarios

WARM_RESET during Data transfer to DUT

L2

L2 Init Hib and misc

AFC with ZERO credits during L2 Init

L2

L2 Normal transfer

Basic Normal Preemption case

L2

L2 Normal transfer

Cause AFCx Transmission

L2

L2 Error Injection

Cause DUT's AFCx_REQUEST_TIMER timeout

L2

L2 Error Injection

Cause DUT's FCx_PROTECTION_TIMER timeout

L2

L2 Error Injection

Cause DUT's TCx_REPLAY_TIMER timeout

L2

L2 Init Hib and misc

Cause PHY initialization Sequence failure

L2

L2 Error Injection

Cause RX Buffer Overflow at DUT

L2

L2 Error Injection

Cause the replayed lower priority frames preempted by higher priority non-replayed frames

L2

L2 Error Injection

Cause two random successive errors and check single NAC reception

L2

L2 Error Injection

Change Link Properties when the one normal data frame tx is in prorgress

L2

L2 Error Injection

Change Link Properties when the only local AFCx_REQUEST_TIMER is Running

L2

L2 Error Injection

Change link properties when the preemption is in progress

L2

L2 Error Injection

Change Link Properties when there is no traffic on link

L2

L2 Error Injection

Drop sending AFC for correctly received frame

L2

L2 Error Injection

Duplicate AFCx

L2

L2 Normal transfer

DUT's Grouped Acknowledgment Mechanism

L2

L2 Init Hib and misc

FCx_PROTECTION_TIMER timeout during L2 Init

L2

L2 Error Injection

Illegal Preemption case

L2

L2 Init Hib and misc

Multilevel preemption and COF TC get courrupt (TC1 become TC0)

L2

L2 Normal transfer

Normal concurrent frame transmission and reception with ACK grouping and random delay on TC0 and TC1

L2

L2 Normal transfer

Normal concurrent frame transmission and reception with ACK grouping and random delay on TC0 or TC1

L2

L2 Normal transfer

Normal frame reception without ACK grouping

L2

L2 Normal transfer

Normal frame transmission and reception without grouping and delay between ACKs

L2

L2 Normal transfer

Normal frame transmit

L2

L2 Error Injection

Random Error Injection at L2 Layer

L2

L2 Error Injection

Send AFC Frame Corrupted Reserved bits

L2

L2 Error Injection

Send AFCx for data frame being Retransmitted

L2

L2 Error Injection

Send COF EOF_EVEN or EOF_ODD when no data frame was started

L2

L2 Error Injection

Send COF symbol continuing a Data frame of a different TC

L2

L2 Error Injection

Send COF without any prior pre-emption

L2

L2 Error Injection

Send Control frame corrupted CRC-16

L2

L2 Error Injection

Send Control Symbols with Corrupt ESC_DL

L2

L2 Error Injection

Send Control Symbols with Reserved TCx values

L2

L2 Error Injection

Send Control Symbols with the Reserved control symbols type

L2

L2 Error Injection

Send Data Frame Corrupted Reserved bits

L2

L2 Error Injection

Send Data frame crossing DL_SYMBOL_MTU

L2

L2 Error Injection

Send Data frame with corrupt CRC-16

L2

L2 Error Injection

Send Data frame with the Sequence number thats previously ACKed

L2

L2 Error Injection

Send Data frame with the wrong Sequence number

L2

L2 Error Injection

Send EOF_EVEN or EOF_ODD or data symbol when a Data frame is pre empted

L2

L2 Error Injection

Send EOF_EVEN/EOF_ODD without CRC symbol

L2

L2 Error Injection

Send Incomplete AFC symbol

L2

L2 Error Injection

Send Incomplete NAC symbol

L2

L2 Error Injection

Send NAC and cause Retransmission from DUT (No Outstanding Frames to be Acked)

L2

L2 Error Injection

Send NAC and cause Retransmission from DUT (Outstanding Frames Remaining to be Acked)

L2

L2 Error Injection

Send NAC during data frame Transmission/Retransmission

L2

L2 Error Injection

Send NAC Frame Corrupted Reserved bits

L2

L2 Error Injection

Send SOF when a Preempted Data frame is Resume

L2

L2 Error Injection

Send SOF when data frame of same TCx is in progress / Pre-emption between happen Same Priority Frame

L2

L2 Error Injection

Send TC0 data frame pre-empting the TC1 data frame / Higher Priority Frame Pre-Empted by Lower one

L2

L2 Normal transfer

Send TCx Data Frame with Payload size of non integral multiple of 32

L2

L2 Error Injection

Send the AFC with CReq bit set

L2

L2 Error Injection

Send unexpected framing Sequence

L2

L2 Error Injection

SOF during data frame of same TC is permitted with pre-emption and replay

L2

L2 Normal transfer

TC1 Data Frame Credit blocked and TC0 Data Frame making progress

L2

L2 Normal transfer

TC1 Data Frame FSN blocked due to maximum outstanding and TC0 Data Frame making progress

L3

L3 Normal transfer

Normal Long Packet Transmit and Receive TC0

L3

L3 Normal transfer

Normal Long Packet Transmit and Receive TC0 and TC1

L3

L3 Normal transfer

Normal Long/Short Packet Transmit and Receive TC0 with different Device ID and Device ID valid

L3

L3 Normal transfer

Normal short header traffic along with the long header traffic with the TC0/1

L3

L3 Normal transfer

Transmit Long Header Packet and check support in DUT

L3

L3 Error injection

Transmit packet with the bad DeviceID encoding

L4

CPort Connection mangement

Message to disconnected Cport

L4

CPort Connection mangement

MESSAGE transmit on cport of status indication of NO_PEER_TC.

L4

CPort Connection mangement

Normal FC Req of Random Credits in continious cycles till t_tx_result = CREDIT EXCEED asserted.

L4

L4 Normal transfer

Normal Segments transmitting and receiving from default CPortID on TC0 with E2E FC disabled

L4

L4 Normal transfer

Normal Segments transmitting and receiving from default CPortID on TC0 with E2E FC disabled

L4

L4 Normal transfer

Normal Segments transmitting and receiving on random CPorts

L4

L4 Normal transfer

Normal single message (T_SDU) transmitting and receiving from default CPortID on TC0

L4

L4 Error injection

Send Incorrect Protocol Control Information DestCPortID

L4

L4 Error injection

Send Incorrect Protocol Control Information - TC

L4

L4 Normal transfer

Send zero sized segment with EOM set to TRUE

L4

L4 Normal transfer

Tranmsit and receive segments with CPortID greater than 31

L4

L4 Error injection

Tranmsit FCT when the E2E FC is disabled

L4

L4 Error injection

Tranmsit segment with the L4s=0

L4

L4 Error injection

Transmit different types of segments when DUT T_ConnectionState is not in CONNECTED

L4

L4 Error injection

Transmit Zero sized segment without EOM being set

L4

L4 Normal transfer

Transmitting and receiving segments (T_PDU) of random size from default CPortID on TC0 from DUT

L4

L4 Normal transfer

Transmitting and receiving segments (T_PDU) of random size from default CPortID on TC0 from DUT

L4

L4 Normal transfer

Transmitting segments (T_PDU) of random size from default CPortID on TC0 from BFM

L4

L4 Normal transfer

Transmitting segments (T_PDU) of random size from default CPortID on TC0 from DUT

L4

L4 Error injection

Trasmit a segment greater than the T_MTU

L4

L4 Error injection

Trasmit a segment with less than T_MTU with out EOM bit to set

L4

L4 Error injection

Tx segment Destination CportID corruption

L4

L4 Error injection

Tx segment Destination TC corruption

L4

L4 Error injection

Tx segment EOM corruption

L4

L4 Error injection

Tx segment FCT corruption

L4

L4 Error injection

Tx segment HDR corruption

L4

L4 Error injection

Tx segment Payload size corruption

L4

L4 Error injection

Tx segment PERCENTAGE ERROR CASE with E2EFC = 0 and multiple specific error injections

L4

L4 Error injection

Tx segment PERCENTAGE ERROR CASE with E2EFC = 1 and enabling all the L4 error injection

L4

L4 Error injection

Tx segment PERCENTAGE ERROR CASE with E2EFC = 1 and multiple specific error injections

L4

L4 Error injection

Tx segment Rx_BUFFER_OVERFLOW corruption

L4

L4 Error injection

Tx segment when E2EFC1 ENABLE and CSV feature is enable

L4

L4 Error injection

Tx segment when the less than needed credits are available with E2EFC set to 0 - Rx Overflow

L4

L4 Error injection

Tx segment when the less than needed credits are available with E2EFC set to 1 - Rx Overflow

L4

L4 Error injection

Tx segment when the zero credits are available with E2EFC set to 1 - Rx Overflow

L4

L4 Error injection

Tx segment when the zero RX BUffer are available with E2EFC0 and CSD feature is enable

L4

L4 Test mode

UniPro Test mode - Error injection

L4

L4 Test mode

UniPro Test mode - FULL DUPLEX

L4

L4 Test mode

UniPro Test mode - HALF_DUPLEX_TxBFM

L4

L4 Test mode

UniPro Test mode - HALF_DUPLEX_TxDUT

DME

HIBERNATE and Attributes

After Hibernate exit make sure retained attributes are restored

DME

ATTRIBUTE READ and WRITE tests

Custom Read/Write RAL sequence

DME

DME Interface Error Injection

DUT LM_SET_* / LM_GET_* - Power on value and Write/Read check

DME

DME Interface Error Injection

LM_SET_* / LM_GET_* Error Transfers

DME

Overriding the RAL sequnces

Overriding the CPORT CONNECT RAL sequence

DME

Overriding the RAL sequnces

Overriding the DUT Init RAL sequnce

DESCRIPTION
arguments provided in below Stimulus section

Stimulus:

First power request; +PWR_REQ_TX_MODE/PWR_REQ_RX_MODE={1,2,4,5}; //1 FAST_MODE, 2-SLOW_MODE , 4-FAST_AUTO_MODE , 5SLOW_AUTO_MODE +PWR_REQ_TX_GEAR/PWR_REQ_RX_GEAR={1,2,3,4,5,6,7 for LS mode and 1,2,3 for HS mode}; +PWR_REQ_TX_LANE/PWR_REQ_RX_LANE={0,1,2,3 - 0 means 4}; +PWR_HS_SERIES={A,B}; +DEFAULT_PWR_REQ={BFM,DUT}; //POWER REQ TARGET - BFM or DUT

Second power request;

[0] Enable the 3b4b_Error, 5b6b_Error, and RD_Error in the m-phy BFM Tx side [1] Send a message from the BFM which is will be corrupted randomly with the one of the above error [2] This will cause the DUT's RxSymbolError to get asserted [3] DUT L1.5 will pass the PA_ERROR.ind to L2 with the PAErrorCode set to BAD_PHY_SYMBOL [4] DUT L2 is expected to generate PA_LANE_ALIGN request and send NAC with RReq bit set to 0 [5] After credit exchange sequence the message will be retrasmitted this time without any errors

- Start the initialization sequence from both DUT, BFM - Transmit upto 10 INVALID_TRG_UPRx_TRIGGERS for DUT's phase 0/0b/1/2/3/4/ for less than PA_LINKSTARTUP_TIMER timeout - Initialization sequence is expected to complete normally

Refer LINE - 1190 , 1191 & 1192

Rx Error injection where the PACP_PWR_cnf from DUT is dropped

Cover hibenrate and non-hibernate cases [1] From BFM initiate the PWR Mode change request [2] Drop PACP_PWR_cnf from the DUT on BFM Rx side. [3] From BFM retransmit the same PACP PWR req agin - Retransmission attempt#1 [4] Drop PACP_PWR_cnf from the DUT on BFM Rx side. [5] From BFM signal the LINE-RESET [5] From BFM retransmit the same PACP PWR req agin - Retransmission attempt#2 - With LINE-RESET flag SET [6] Check the that DUT Issues the LINE-RESET from the L1.5 and send the - Initiate PA Link Statrtup sequence from DUT - Wait for DUT to timer timedout - Again, Initiate the PA Link Startup sequence from BFM and DUT simultaneously - Check for Link Initialization to complete - Do some couple of full duplex messages

1. BFM initiates the test mode 2. Error is injected sometimes in the CJTPAT and CRPAT packets sent via PACP_TEST_DATA 3. Check the DUT's PA_PACP_FrameCount and PA_PACP_ErrorCount are compared with the expected values

Scenario#1: Single lane - Start off with random HS, LS Mode and single lane - From BFM Start the data frame transmission - Insert a deskew pattern in the middle of the data frame from BFM - Deskew pattern is dropped by the DUT PA - After deskew pattern rest of the symbols receive correctly by DUT DL - The data frame is acked by the DATA

Scenario#2:Multi Lane > 1 Lane - Start off with random HS, LS Mode and max lanes supported - From BFM Start the data frame transmission - Insert a deskew pattern in the middle of the data frame from BFM on random < total number of lanes

[1] Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. [2] A UniPro Link Startup Sequence is aborted by the following condition - Assertion of the warm reset to the DUT from application [3] Initiate the DUT initialization sequence again [4] DUT should re-initiate the initialization sequence [5] Send and receive 2 messages from both BFM and DUT

- In PHASE5 : Report to the DME using PA_LM_LINKSTARTUP.cnf_L that the Link Startup Sequence succeeded. Exit the Link Startup Sequence and enter SlowAuto_Mode. So it is not possible to abort in this Phase

Cold reset abort does not make sense. It will work anyway.

Refer LINE - 1190 , 1191 & 1192

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request [2] Donot send PACP_PWR_cnf from the BFM. Wait for the timeout using Rx Error injection to drop request [3] From BFM check that DUT has retransmitted the same PACP PWR req agin - Retransmission attempt#1 [4] Block PACP_PWR_cnf from the BFM. Wait for the timeout to occur at the DUT [5] From BFM check that DUT signals LINE-RESET [5] From BFM check that DUT has retransmitted the same PACP PWR req agin - Retransmission attempt#2 - With LINE-RESET flag SET [6] Issue the LINE-RESET from the L1.5 and send the PACP_PWR_cnf with status set to PWR_OK

//PWR_BUSY [1]Issue a valid PWR Mode change Request to DUT - Writing the PA_PWRMode completed [2] Figure out a way to synchronize the last few symbols of PACP PWR Request from BFM reaching DUT on completion of the writing to the PA_PWRMode from DME interface [3] DUT shall reject the peer request and send PACP_PWR_cnf with PWR_BUSY status [4] Make sure local power mode request change completes successfully.

//PWR_ERROR_CAP [5] Issue a PWR Mode change Request from BFM to DUT,with capabability error injected. [6] DUT must send PACP_PWR_CNF with status set to PWR_ERROR_CAP

Cover hibenrate and non-hibernate cases Scenario#1: DUT rejecting the local request [1] Send a valid PACP PWR Request from BFM to DUT [2] After completing the transmission from BFM - Initiate the Power mode change at DUT - Writing the PA_PWRMode. [3] DUT shall reject the local request by providing the PWR_BUSY indication to PA_LM_SET [4] Verify the BFM receives the Successful PACP_PWR_cnf [5] Transmit two messages

Scenario#2: DUT rejecting the peer request [1] Issue a valid PWR Mode change Request to DUT - Writing the PA_PWRMode completed

Cover hibenrate and non-hibernate cases Scenario#1: Local req reject when a remote req is received when local req is being processed (i)BFM=True=x DUT=False=80 (ii)BFM=False DUT=False (iii)BFM=True=x, DUT=True=y & x<y

Scenario#2: Remote req rejected when local req is being processed: 1. BFM= False=80 DUT=True=y 2. BFM=False DUT=False 3. BFM=True=x, DUT=True=y & x>=y

[1] Test gives EPR from the BFM [2] Test verifies the end point reset is indicated at the DUT side. [3] This verifies the PACP EPR frame sent and receive correctly

[1] Test gives EPR from the DUT [2] Test verifies the end point reset is indicated at the BFM side [3] This verifies the PACP EPR frame sent and receive correctly

Inject EOB_CORR for the PACP / DL Frames Compliance: Scenario #1 : Data and control bit corruption(INJ_DFRAME_EOB_CORR MK2_xx DNC is not corrupted) [1] Transmit a data frame from the BFM ensuring it creates burst [2] EOB corrupt the burst leading to Control bits corruption [3] DUT L2 Rx will get those additional symbols and sends a NAC frame [4] BFM checks the NAC frame reception [5] Retransmit the data frame correctly

Scenario #2 : Data and Control bit correct and Symbol corruption (INJ_DFRAME_EOB_DNC_CORR - MK2_xx DNC is corrupted) [1] Transmit a data frame from the BFM ensuring it creates burst [2] EOB corrupt the burst leading to Symbol error [3] DUT L2 Rx will not know about it and PA will drop these symbols

Scenario#1 : Corrupted fillers in the middle of DL Data frame [1] Transmit a DL data frame from the BFM [2] In the middle of data frame from BFM insert the [a] corrupted Fillers with Data and Control bit corruption [b] corrupted Fillers with Data and Control correct but with Symbol corruption [3] Invalid filler symbols are received by the DUT DL [4] BFM is expected to receive the NAC from DUT [5] BFM will retransmit the Data frame. This time dont inject FILLER error and it should complete normally

Scenario#2 : Corrupted fillers in the middle of PACP frame

Inject SOB_CORR for the PACP / DL Frames.

Compliance: MK0_xx DNC not corrupted(INJ_DFRAME_SOB_CORR) [1] SOB for DL Data packet corrupted from BFM Tx side [2] DUT L2 Rx will not be able to get to the DL frame [3] Triggers the TCx_REPLAY_TIMER at the BFM side [4] Retransmit the data frame correctly

MK0_xx DNC corrupted (INJ_DFRAME_SOB_DNC_CORR) [1] SOB for DL Data packet corrupted from BFM Tx side [2] DUT M-PHY Rx will assert symbol error signal. [3] DUT L1P5 RX will send PA_ERROR_ind to its L2 and L2 will schedule NAC for it.

Inject SOB_CORR(MK0_xx) for INIT SYMBOLS .

Compliance: DURING TX_INIT_PHASE_0: [1] SOB for INIT_SYMBOLS are corrupted from BFM Tx side starting from PHASE0 [2] DUT L1P5 Rx will drop all init symbols headed by Corrupted SOB. [3] BFM Tx will move to PHASE1(as it has received valid TRG_UPR0 symbols) and starts tranmsitting TRG_UPR1 but DUT will be in PHASE 0 waiting for reception of TRG_UPR0. [4] LINK_STARTUP_TIMER_TIMEOUT at DUT side. [5] Test will issue new linkstartup request and successfull linkstartup sequence is done

DURING TX_INIT_PHASE_0B: [1] SOB for INIT_SYMBOLS are corrupted from BFM Tx side starting

[1] Send a message from the BFM [2] From BFM Tx insert a {MARKER3, MAKER4, MARKER5} [3] DUT L1.5 will pass the PA_ERROR.ind to L1.5 with the PAErrorCode set to UNMAPPED_PHY_ESC_SYMBOL [4] DUT L2 is expected to generate PA_LANE_ALIGN request and send NAC with RReq bit set to 0 [5] After credit exchange sequence the message will be retrasmitted this time without any errors

TODO: Reserved symbol error can be detected both by L1.5 and M-PHY. When M-PHY receives any of the K28.0, K28,2, K28.4, K28.7 (Table 4 Control symbols M-PHY spec) they are considered as Reserved. RxSymbolErr : From M-PHY it does not distinguish between the 3b4b_Error, 5b6b_Error, and

- Either BFM/DUT starts the Initialising sequence of L1p5 by PA_LM_LINKSTARTUP.req. - A UniPro Link Startup Sequence is aborted by the following condition - From test setting DUT power mode to Hibernate_Mode/Off_Mode during a particular State/Phase. - Wait for random delay - From test setting DUT power mode to non Hibernate_Mode/Off mode - DUT should re-initiate the initialization sequence - Send and receive 2 messages from both BFM and DUT - In PHASE5 : Report to the DME using PA_LM_LINKSTARTUP.cnf_L that the Link Startup Sequence succeeded. Exit the Link Startup Sequence and enter SlowAuto_Mode. So it is not possible to abort in this Phase

- Initiaite the PA Link Startup sequence from the DUT and BFM simultaneously or either end - Using Lock Unlock feature, Insert random delays between the phases such that sum of delays is < 100ms(-10%) = 90ms - Check for the Link Initialization to complete - Transmit 2 messages each from the BFM and DUT. Wait for it to complete

- Initiaite the PA Link Startup sequence from the DUT and BFM simultaneously - Wait for the initialization to complete - ransmit 2 messages each from the BFM and DUT. Wait for it to complete

- On power up donot program the DUT L1.5 to start the initialization - Wait for a period less than Link Startup timer timeout value - Program the DUT to start the L1.5 initialization - Wait for the initialization to complete - Transmit 2 messages each from the BFM and DUT. Wait for the transfers to complete

- On power up don't program the BFM L1.5 to start the initialization - Wait for a period less than Link Startup timer timeout value - Program the BFM to start the L1.5 initialization - Wait for the initialization to complete - Transmit 2 messages each from the BFM and DUT. Wait for it to complete

Scenario#1 : DL Frame - Start off with random HS, LS Mode and max number of lanes supported - Transmit a data frame as follows - Start off with Deskew pattern on the Logical Lane 0 followed by that start transmitting symbols that belong to Lane 0 - Send the Deskew pattern on the Logical Lane 1 to MAX_LANES after 3 PA symbols - these 3 symbols on Lane 1 can be random PA symbols other than Deskew pattern - Send the data frame normally on all the active the lanes along with Lane 0 - On Lane0 the data frames symbols will complete 3 symbols early. Send 3 fillers - This scenario leads to deskew FIFO overflow in the DUT

Refer LINE - 1190 , 1191 & 1192 Scenario: [1] Configure the TC0_REPLAY_TIMER in L2 of DUT with a small value through Command line. [2] Do some 2 message from both BFM and DUT. Block AFCs from BFM [3] DUT should initiate a PA_INIT.req because of TC0_REPLAY_TIMER timeout. [5] After the BFM transmits confirmation to the PA_INIT PWR_REQ frame, re-Configure the TC0_REPLAY_TIMER in L2 of DUT with a large (noraml) value and unblock AFC in BFM [6] Wait for the BFM L1P5 to receive a PA_INIT request and transmit the corresponding PA_INIT PWR_REQ. [7] Drop the CNF sent by the DUT in response to this PWR_REQ FRAME. [8] Wait for line-reset from the BFM, and the subsequent retransmission of the PWR_REQ frame. [7] After the BFM receives the Confirmation frame from the DUT, send 2 messages from both BFM and DUT. Wait for them to complete

Refer LINE - 1190 , 1191 & 1192 Scenario: [1] Configure the TC0_REPLAY_TIMER in L2 of DUT with a small value through Command line. [2] Do some 2 message from both BFM and DUT. Block AFCs from BFM [3] DUT should initiate a PA_INIT.req because of TC0_REPLAY_TIMER timeout. [4] Block the PWR_CNF frame from the BFM and Check for line-reset from DUT [5] Re-Configure the TC0_REPLAY_TIMER in L2 of DUT with a large (noraml) value and unblock AFC in BFM [6] Wait for the L1P5 initialisation to happen. [7] Do some 2 message from both BFM and DUT. Wait for it to complete

[1] Issue PA_LM_PEER_SET/GET.req(selected randomly) with the Attr_ID set to PA_SleepNoConfigTime from DUT [2] Block the confirmation that is to be sent by BFM [3] DUT is expected to retransmit the PACP_PEER_SET req - Retransmission attempt#1 [4] Block the confirmation at the BFM [5] DUT is expected to retransmit the PACP_PEER_SET req - Retransmission attempt#2 [6] Continue to Block the confirmation at the BFM [7] DUT shall abort the transfer and provide indication with PEER_COMMUNICATION_FAILURE //TODO [8] Do one successful PA_LM_PEER_SET/GET.req(selected randomly) to PA_SleepNoConfigTime from DUT

Scenario#1: INVALID_MIB_ATTRIBUTE [1] Issue PA_LM_PEER_SET.req from BFM to an invalid attribute id (Ex: 0x1559) - < Start || > End [2] Make sure that DUT sends a PACP_SET_CNF with ConfigResultCode set to INVALID_MIB_ATTRIBUTE [3] Issue PA_LM_PEER_GET.req from BFM to an invalid attribute id (Ex: 0x1559) - < Start || > End [4] Make sure that DUT sends a PACP_GET_CNF with ConfigResultCode set to INVALID_MIB_ATTRIBUTE

Scenario#2: INVALID_MIB_ATTRIBUTE_VALUE [2] Issue PA_LM_PEER_SET.req from BFM to PA_SleepNoConfigTime with value greater than the allowed limit [3] Make sure that DUT sends a PACP_SET_CNF with ConfigResultCode set to INVALID_MIB_ATTRIBUTE_VALUE

Scenario#1: Initiated from BFM [1] Issue PA_LM_PEER_SET.req with the Attr_ID set to PA_SleepNoConfigTime from BFM [2] Make sure the DUT updates the same and check that PA_LM_PEER_SET.ind is indicated [3] Confirm the same by issuing the DME_RD at DUT to check the attribute is updated //TODO [4] Issue PA_LM_PEER_GET.req with the Attr_ID set to PA_SleepNoConfigTime from BFM and check data returned in the confirmation matches what was programmed initially

Scenario#2: Initiated from DUT [1] Issue PA_LM_PEER_SET.req with the Attr_ID set to PA_SleepNoConfigTime from DUT [2] Update the l1p5 config parameter and wait for the peer_get event [3] Issue PA_LM_PEER_GET.req with the Attr_ID set to PA_SleepNoConfigTime from DUT and check data

Power mode change by BFM from default LS to HS and again from HS to LS on different number of lanes [1] Power mode change from default LS to HS is made as a default cmd_type in uniport_cport_command_seq, [2] Full duplex do 2 messages [3] Again power mode change from HS to LS is made by separate sequence in this test [4] Full duplex do 2 messages

4 combinations of DUT/BFM initiating the 2 power mode requests are covered in this test.

Expectation: both BFM and DUT must change their mode successfully

This is like PACP frame pre-emption. Its not valid and pre-empted frame is discarded and never resumed. Spec is not clear if the pre-empted frame is executed but assuming it will be.

[0] Do couple of full duplex messages [1] Create scenario leading to PACP_PWR_Req/GET/SET/EPR request generation [2] After random bytes of this PACP frame have been transmitted start PACP_GET_req - Make sure first PACP frame is not completely transmitted [3] Make sure DUT respods to PACP_GET_req and discard the previous one [4] Check for the PACP Error count to make sure PA has detected it [5] Do couple of full duplex messages

Frames are transferred on Different no. of LANE's with different MODE and GEAR

Stimulus: +PWR_REQ_TX_MODE=1 +PWR_REQ_TX_GEAR=1 +DEFAULT_PWR_REQ=BFM/DUT/BOTH

Common Cmd line Args :: // +BFM_RMMI_MODE=HS +BFM_RMMI_GEAR=G2 +DUT_RMMI_MODE=HS +DUT_RMMI_GEAR=G2

Data Frames are transferred on Different no. of LANE's with GEAR set to G2. Totally 16 different no.of lane combinations to execute. Number of messages = 5 and Number of FC requests = 1 Stimulus: After Link Initialization send Data from BFM & DUT.

+BFM_TX_AVAILABLE_LANES=1, 2, 3, 4 // ( Valid Values ) +DUT_TX_AVAILABLE_LANES=1, 2, 3, 4 // ( Valid Values ) ( by Default 4 Lanes will be active)

+BFM_TX_AVAILABLE_LANES=1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4 +DUT_TX_AVAILABLE_LANES=2, 3, 4, 1, 3, 4, 1, 2, 4, 1, 2, 3

-Writing the gear,lane,speed pwr_mode Attribute -Do some message tranfser in between -Then write the PA_PWRmode -Initiate the pwr request sequence from DUT

Scenario#1 - Do some 2 message from both BFM and DUT. Wait for it to complete - Send NAC frame with the RReq bit set to 1 from BFM - Using the L1.5 events make sure that DUT has re-initiated the L1.5 initialization process - Do some 2 message from both BFM and DUT. Wait for it to complete

Scenario#2 - Do some 2 message from both BFM and DUT. Wait for it to complete - Cause the DUT to send AFCx with CReq bit set - During the initial credit exchange sequence - Data transfer (Requires two times FCx_PROTECTION_TIMER timeout)

- Send 2 data frames both from both BFM and DUT - Initiate HIBRNATE ENTRY command with target set to BFM or DUT - Make sure the Ongoing Data is sent and then a PACP_PWR_req frame is sent with the TxMode & RxMode set to Hibernate (0x3). - Check DUT and BFM has entered the Hibenrate (Side band signals??)

- Initiate HIBRNATE EXIT command with target set to BFM or DUT - (Signaled by toggling RMMI signal directly - dut_hibern8_exit) - Wait for the DUT or BFM to exit the Hibernate state by RMMI bfm_hibern8_exit - Send 2 data frames both from both BFM and DUT

Compliance test: Request corruption [0] Do couple of full duplex messages [1] Issue a Power mode change request from BFM side [2] Corrupt the PACP Power request with the CRC error [3] DUT is expected to silently drop the PACP PWR request [4] Wait for the PACP_REQUEST_TIMER timeout at the BFM side [5] Retransmit the PACP PWR Req frame without any error [6] Power mode change request is expected complete normally [7] Do couple of full duplex messages

Compliance test: Confirmation corruption [0] Do couple of full duplex messages [1] Issue a Power mode change request from DUT side

Stimulus: [1] Initiate a Power mode change request from BFM [2] Corruput the PACP frames with EscParam_PA other than PACP_BEGIN, TRG_UPR0, TRG_UPR1, TRG_UPR2 or TRG_EPR from the BFM [3] DUT L1.5 will pass the PA_ERROR.ind primitive having the PAErrorCode set to BAD_PA_PARAM [4] Check that DUT PACP Error count is updated [5] DUT DL is expected to PA_LANE_ALIGN.req to DUT L1.5 [6] NAC with RReq set to 0 is expected from DUT. Complete the L2 Credit exchange sequence. [7] Do a couple of full duplex messages

TODO: Does the PACP_REQUEST_TIMER expected to stop on receiving the Deskew pattern or after

- From BFM send - Non PACP_CAP.ind frame after Phase_5 of the Link Initialisation. - Wait for the random delay less than Initialization timer timeout - DUT Link Initialization should : ( Depends on the DUT implementation ) - Wait for the PACP_CAP frame is rcvd and complete the initialization and ignores the non PACP_CAP frames received. - Send the correct PACP_CAP frame from BFM - Send and receive 2 messages from both BFM and DUT

PACP_CAP_ind : Corruptable fields t_sleep_no_config - [3:0] max_pwm max_hs - [2:0] - [1:0]

t_stall_no_config - [7:0] version_info - [15:0]

flags_cap_ind_frame - [1:0] t_save_config CRC - [7:0]

[1] After the phase 5 of the init send the corrupted PACP_CAP_ind frame from BFM [2] DUT LINK_STARTUP_TIMER is exepcted to expire waiting for the correct PACP_CAP_ind frame

[1] Issue a PA_LM_PEER_GET/SET.req from the DUT [2] Send the PACP_GET/SET_cnf from BFM containing randomly any of the following ConfigResultCode - INVALID_MIB_ATTRIBUTE - INVALID_MIB_ATTRIBUTE_VALUE - READ_ONLY_MIB_ATTRIBUTE - WRITE_ONLY_MIB_ATTRIBUTE - BAD_INDEX - LOCKED_MIB_ATTRIBUTE - PEER_COMMUNICATION_FAILURE - BUSY [3] Check that DUT PA_LM_PEER_GET/SET.cnf with same ConfigResultCode is indicated

Cover hibenrate and non-hibernate cases [1] Initiate Power mode change request from DUT [2] Send the PACP_PWR_cnf randomly with one of the following to the DUT - PWR_BUSY - PWR_ERROR_CAP [3] Check for the DUT indication PA_LM_PWR_MODE_CHANGED.ind PowerChangeResultCode as received in the PACP_PWR_cnf [4] Do couple of full duplex messages transfers at previous configuration

- Start the initialization sequence from both DUT, BFM - From BFM - in Phase 0 for less than Initialization timer timeout - Send INVALID_TRG_UPR0_TRIGGERS - DUT should remain in - RxPhase_0b and it will indicate fail if transmitted beyond Initialization timer timeout - BFM after transmitting N corrupt TRG_UPR0, switch to sending the correct lane numbers - Initialization should complete normally

- Start the initialization sequence from both DUT, BFM - From BFM send in Phase 0 till PA_LINKSTARTUP_TIMER timeout - INVALID_TRG_UPR0_TRIGGERS - DUT should terminate the initialization after the Initialization timeout and send indication of STARTUP.cnf with status set to FALSE - Restart the init from DUT and make sure the Init completes normally

- Start the initialization sequence from both DUT, BFM - Wait for the BFM to receive TRG_UPR0 and move to phase 0b - Transmit 50 INVALID_TRG_UPR0_TRIGGERS for DUT's phase 0b/1 for less than PA_LINKSTARTUP_TIMER timeout - Subsequently start off with the TRG_UPR1 from BFM and follow the rest of init correctly - Initialization sequence is expected to complete normally

- Start the initialization sequence from both DUT, BFM - From BFM - in Phase 1 for less than Initialization timer timeout - INVALID_TRG_UPR1_TRIGGERS - DUT should remain in - RxPhase_1 and it will indicate fail if transmitted beyond Initialization timer timeout - BFM after transmitting N corrupt TRG_UPR1, switch to sending the correct TRG_UPR1 - Initialization sequence is expected to complete normally

- Start the initialization sequence from both DUT, BFM - From BFM n Phase 1 keep sending the following till PA_LINKSTARTUP_TIMER timeout - INVALID_TRG_UPR1_TRIGGERS - DUT should terminate the initialization after the Initialization timeout and send indication of STARTUP.cnf with status set to FALSE - Restart the init from DUT and make sure the Init completes normally

- Start the initialization sequence from both DUT, BFM - Wait for the BFM to receive TRG_UPR1 and move to phase 0b - Transmit 50 INVALID_TRG_UPR1_TRIGGERS for DUT's phase 2 for less than PA_LINKSTARTUP_TIMER timeout - Subsequently start off with the TRG_UPR2 from BFM and follow the rest of init correctly - Initialization sequence is expected to complete normally

- Start the initialization sequence from both DUT, BFM - From BFM - in Phase 3 for less than Initialization timer timeout - INVALID_TRG_UPR2_TRIGGERS - DUT should remain in - RxPhase_3 and it will indicate fail if transmitted beyond Initialization timer timeout - BFM after transmitting N corrupt TRG_UPR2, switch to sending the correct TRG_UPR2 - Initialization sequence is expected to complete normally

- Start the initialization sequence from both DUT, BFM - From BFM n Phase 3 keep sending the following till PA_LINKSTARTUP_TIMER timeout - INVALID_TRG_UPR2_TRIGGERS - DUT should terminate the initialization after the Initialization timeout and send indication of STARTUP.cnf with status set to FALSE - Restart the init from DUT and make sure the Init completes normally

- Start the initialization sequence from both DUT, BFM - Wait for the BFM to receive TRG_UPR2 and move to phase 4 - Transmit 50 INVALID_TRG_UPR2_TRIGGERS for DUT's phase 4 for less than PA_LINKSTARTUP_TIMER timeout - Subsequently send couple of TRG_UPR2 from BFM and follow the rest of init correctly - Initialization sequence is expected to complete normally

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request [2] Donot send PACP_PWR_cnf from the BFM. Wait for the timeout. [3] From BFM check that DUT has retransmitted the same PACP PWR req agin - Retransmission attempt#1 [4] Block PACP_PWR_cnf from the BFM. Wait for the timeout. [5] From BFM check that DUT signals LINE-RESET [5] From BFM check that DUT has retransmitted the same PACP PWR req agin - Retransmission attempt#2 - With LINE-RESET flag SET [7] Two cases here: - Block PACP_PWR_cnf from the BFM. Wait for the timeout. - Send the confirmation with STATUS set to other than PWR_OK status [6] DUT DME should see a PA_LM_PWR_MODE_CHANGED.ind

[1] Send the PACP frames with invalid configurations from BFM side - Randomize the invalid values for all the fields - tx_mode, rx_mode, tx_lane, rx_lane, tx_gear, rx_gear, dev_id [2] DUT is expected to send the PACP_PWR_cnf with Status set to PWR_ERROR_CAP [3] Do couple of full duplex messages [4] Do successful random power mode change [5] Do couple of full duplex messages

TODO: Need to figure out a way to cover the PWR_FATL_ERROR case

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request [2] Send PACP_PWR_cnf from the BFM but dont end the burst of the PACP_PWR_cnf - Keep sending fillers till PA_PACPReqEoBTimeout [3] DUT DME should see a PA_LM_PWR_MODE_CHANGED.ind (PWR_FATAL_ERROR) [4] End the burst of the PACP_PWR_cnf from the BFM [5] From DUT initiate the PWR Mode change request again [6] Send the PACP_PWR_cnf from BFM and end the burst normally [7] Do couple of full duplex messages

Cover hibenrate and non-hibernate cases [1] From DUT initiate the PWR Mode change request [2] Donot send PACP_PWR_cnf from the BFM. Wait for the timeout. [3] From BFM check that DUT has retransmitted the same PACP PWR req agin - Retransmission attempt#1 [4] Send the PACP_PWR_cnf from BFM with PWR_OK status this time [5] Do couple of full duplex messages with new power mode settings if its not hibernate case

For both DUT initiated and BFM Initiated hibernate requests check the normal cases with the User data

- Start off with random HS, LS Mode and random number of lanes supported - From BFM Start M-PHY burst by asserting TxBurst - Dont send the SOB from BFM - Send N Random symbols other than SOB from BFM - DUT is expected to drop these till SOB is received - From BFM send the correct SOB and send the data frame - DUT is expected to ACK the data frame

Random hibernate entry and exit requests from BFM or DUT generated with background data traffic. Number of Hibernate entry and exit requests generated is based on cmd count specified by user via cmd line argumenet

Before issuing the Hibernate entry data traffic is stopped and both DUT/BFM idle is ensured using IDLE indication from Scoreboard, BFM and DUT.

Random power mode change requests generated with background data traffic. Number of power mode requests generated is based on cmd count specified by user via cmd line argumenet

Before issuing the Power mode change request data traffic is stopped and both DUT/BFM idle is ensured using IDLE indication from Scoreboard, BFM and DUT.

Expectation: both BFM and DUT must change their mode/gear/lane successfully

Skip the phases and verify the DUT is still responding for the Link Startup The DUT will be receiving all the TRG UPR symbols even though the phases were skipped. So Link Startup should be success Phase0b is the special case(need to confirm whether to verify this or not)

- Cover the cases of starting before phase 0 - Starting after phase 0 and before phase 5 - Different lane configurations

- Start the Link Startup sequence from BFM. - Complete the Phase 1/2/3/4 and start sending TRG_UPRO again from BFM - DUT will not detect the TRG_UPR0 again as per (5.4.2.8 PA_LM_LINKSTARTUP.cnf_L) - DUT will indicate failure of the Link init via DME - Initiate the Link startup again and Complete the Link init successfully - Transfer couple of full duplex message

[1] Initiate the Link startup initialization sequence [2] During the different phases inject the - BAD_PHY_SYMBOL - 3b4b_Error, 5b6b_Error, and RD_Error - Res_error - UNMAPPED_PHY_ESC_SYMBOL - UNEXPECTED_PHY_ESC_SYMBOL - BAD_PA_PARAM [compliance_pa_init_phase0b_trg_upr0_e_rr_and_recovery_uvm.log] [3] DUT is expected to ignore them and wait for the right triggers to arrive [4] DUT is expected the complete the init sequence normally

Scenario#1 - Initalize the Link to Highest gear and highest number of lanes - Do some 2 message from both BFM and DUT. While the message transfer is in progress - Initiate DME_RESET_req(WARM reset) to BFM , after all layers have reseted and DME_RESET_cnf_L, is received , the link is in LINK DOWN state. - Issue DME_LINKSTARTUP_req to BFM, by which l1p5_linkstartup sequence is initiated. - Remote LAYER(DUT) which is in LINK UP state, after detecting TRG_UPR0, indicates to DME via PA_LM_LINKSTARTUP_ind and DME issues DME_LINKLOST_ind. - Remote End Point Application issues DME_RESET_req(WARM reset) and after all layers have reseted and DME_RESET_cnf_L, is received , the link is in LINK DOWN state.

- Initalize the Link to Highest gear and highest number of lanes - Do some 2 message from both BFM and DUT. While the message transfer is in progress - Initiate DME_RESET_req(WARM reset) to DUT , after all layers have reseted and DME_RESET_cnf_L, is received , the link is in LINK DOWN state. - Issue DME_LINKSTARTUP_req to DUT, by which l1p5_linkstartup sequence is initiated. - Remote LAYER(BFM) which is in LINK UP state, after detecting TRG_UPR0, indicates to DME via PA_LM_LINKSTARTUP_ind and DME issues DME_LINKLOST_ind. - Remote End Point Application issues DME_RESET_req(WARM reset) and after all layers have reseted and DME_RESET_cnf_L, is received , the link is in LINK DOWN state. - Remote End Point Application issues DME_LINKSTARTUP_req, by which l1p5_linkstartup sequence is initiated. - Wait for Linkstartup completion. - Send the AFC TCx with Zero credits. Make sure DUT has set the DL_PeerTCxPresent should be set to false - Send the AFC TCx with the greater than or equal to 10 and check that the DL_PeerTCxPresent should be set to true

- Enable DL_TxPreemptionCap for both the DUT and the BFM - Transmit a TC0 data packet and there on transmit a TC1 data packet while the TC0 is still in progress. - BFM will pre-empt the TC0 frame with TC1 and there on resume the TC0 frame

Stimulus: BFM TX Starts Transmission of Lower Priority Frame and after some frame symbol transmission Higher Priority Frame will be scheduled Response: DUT RX Receives Higher Priority Frame first and then the Lower one DUT TX schedules response(if any) of the Higher Priority frame first and then for the Lower one

- Causing AFCx Transmission from the DUT

- Causing DUT's AFCx_REQUEST_TIMER timeout, by sending number of TCx Data Frame(s) less than DUT's TCxOutAckThreshold value. - This will lead to AFCx_REQUEST_TIMER timeout and DUT sending Promoted AFCx.

Expected Response from DUT: - DUT must wait until it receives as many TCx Data Frames as specified in the TCxOutAckThreshold attribute, before sending AFCx - DUT's AFCx_REQUEST_TIMER must expire as it won't receive the required number of TCx Data Frames - On AFCx_REQUEST_TIMER Expiration DUT must send Promoted AFCx with the latest information.

[a] FCx_PROTECTION_TIMER Running by sent AFCx with CReq bit set to '1' - Causing DUT's FCx_PROTECTION_TIMER timeout, by stopping to send or droped AFC which transmitted because of AFC(CReq=1) Received from BFM. This will lead to FCx_PROTECTION_TIMER timeout

- DUT is expected to do PHY initialization triggered by DL layer - If PA_INIT.cnf_L received with PAReservedLinkInitialized set to FALSE - DL layer sent a NAC frame with RReq bit set to '1' - DL layer sent a AFC frame with CReq bit set to '1' - If PA_INIT.cnf_L received with PAReservedLinkInitialized set to TRUE - DL layer sent a NAC frame with RReq bit set to '0' - DL layer sent a AFC frame with CReq bit set to '1'

- Causing DUT's TCx_REPLAY_TIMER timeout, by stopping to send or droped AFCs. This will lead to TCx_REPLAY_TIMER timeout and DUT replaying unacknowlwdge frames - Help to checkout DUT is replaying unacknowledge frames or not

- Dont respond to AFCx frame for the correct data frame received. This will lead to TCx_REPLAY_TIMER timeout. AFC is first received from DUT after this timeout.

- DUT is expected to do PHY initialization triggered by DL layer and then DL layer sent a NAC frame with RReq bit set retransmission shall be processed according to the arbitration scheme

User Interface: - NA

- Cause scenario to trigger the PHY init and cause the PHY init Sequence failure. - This should cause DUT uniprostack to get the application involved

- Send a Data Frame when the DUT TCx does not have any credits to accept the packet. - Send Data Frame of TC which is not supported or implemented by PEER

User Interface: - NA

Expected Response from DUT: - DUT must transmit NAC

Response from BFM: -

Spec Address:

- Send a corrupt TC0 data frame - Wait for NAC from DUT - Start the retranmission of the TC0 data frame and cause the pre-emption of the replayed TC0 data frame with the non-replayed TC1 data frame

User Interface: - NA

Expected Response from DUT: - DUT mustn't Transmit NAC

Response from BFM: -

- Successive errors that lead to NAC are caused and single NAC expected. Check TC0 NAC condition fixed by the TC1 correct data frame or control frame transmission and vice versa. - Injecting Errors on Consecutive L2 Frames

User Interface: - NA

Expected Response from DUT: - Drop the Frames and Send a Single NAC frame

Response from BFM: - Checks it Receives Single NAC

- Initiate the change in link properties - Link Properties change from BFM [C] Traffic is present from both Tx and Rx side - PA Layer will trigger PA_DL_PAUSE.ind - All DL Layer timers shall be stopped - DL Layer may complete transmission of the current Frame. - DL Layer shall transmit pending, promoted AFC or NAC Frames before issuing PA_DL_PAUSE.rsp_L - After receiving PA_DL_RESUME.ind, BFM will able to resume from where it paused - DUT shall able to accept those remaining frame symbols - Note: PA_DL_PAUSE.rsp_L is randomly generated - PA_DL_PAUSE.rsp_L generated immediately after ProAFCx Transmission is completed(If exists)

- Initiate the change in link properties - Link Properties change from BFM/DUT [B] No Traffic from Tx (i.e. No Data Frame Transmission is in progress, but AFCx_REQUEST_TIMER is Running) - PA Layer will trigger PA_DL_PAUSE.ind - All DL Layer timers shall be stopped - DL Layer nothing to transmit any Data Frames, But at DL Layer unacked rx data frame exist so DL shall transmit pending Promoted AFC before issuing PA_DL_PAUSE.rsp_L

User Interface: - NA

Expected Response from DUT:

- Initiate the change in link properties - Link Properties change from BFM [C] Traffic is present from both Tx and Rx side - PA Layer will trigger PA_DL_PAUSE.ind - All DL Layer timers shall be stopped - DL Layer may complete transmission of the current Frame. - DL Layer shall transmit pending, promoted AFC or NAC Frames before issuing PA_DL_PAUSE.rsp_L - After receiving PA_DL_RESUME.ind, BFM will able to resume from where it paused - DUT shall able to accept those remaining frame symbols - Note: PA_DL_PAUSE.rsp_L is randomly generated - PA_DL_PAUSE.rsp_L generated immediately after ProAFCx Transmission is completed(If exists)

- Initiate the change in link properties - Link Properties change from BFM/DUT [A] No Traffic from Tx and Rx (i.e. No Data Frame Transmission is in progress, and No AFCx_REQUEST_TIMER is Running) - PA Layer will trigger PA_DL_PAUSE.ind - All DL Layer timers shall be stopped - DL Layer nothing to have transmit, so DL shall immediately generate a PA_DL_PAUSE.rsp_L as there are no pending, promoted AFC or NAC Frames

User Interface: - NA

Expected Response from DUT: - Link Properties change from DUT

- Drop sending some number of AFCs for the correctly received frames. As credits are self healing DUT should be able to continue with the updated credits.

- During the Initial Credit exchange - To cause the Replay timer timeout - To cause the Credit blocking - DUT has sent AFC + CReq bit and leading to PA.init

Info: - Intermediate AFC dropped just results in subsequent AFCs getting treated as Grouped AFCs - Last AFC getting dropped will cause the TCx_REPLAY_TIMER timeout. There is already a test case to take care of it - Cause DUT's TCx_REPLAY_TIMER timeout Case

- Send Duplicate AFCx, i.e. Send more than one Acknowledgement back2back of Correctly Received L2 Data Frame

User Interface: - NA

Expected Response from DUT: - DUT should just be able to drop them. - Take Flow Control Information and Drop Acknowledge Information

Response from BFM: -

- Transmit TCx Data Frame from BFM according to DUT's TCxOutAckThreshold i.e. if DUT's TCxOutAckThreshold is set to 5 then BFM will transmit 6 TCx Data Frames and DUT will transmit AFCx as it receives these 6 TCx Data Frames - DUT's AFCx_REQUEST_TIMER shall not expire

Expected Response from DUT: - DUT will trasmit AFCx as receives upto TCxOutAckThreshold+1 TCx Data Frames - AFCx_REQUEST_TIMER shall not expire

- DUTs dl_tcx_rx_init_creditval and dl_afcx_credit_threshold are set to max to ensure AFC is not Tx due to credits exhaustion

- Dont send the AFC For TC1 till the FCx_PROTECTION_TIMER times out - Send TC1 AFC within timeout but dont send the AFC For TC0 till the FCx_PROTECTION_TIMER times out - Expected response from DUT NAC with RReq bit set should be received followed by AFCx with

- Enable the DL_TxPreemptionCap on both DUT and BFM side - Creating Illegal Preemption Scenario

Expected Response from DUT: - Drop Frame and transmit NAC

Stimulus: BFM TX will do illegal preemption Response: DUT RX should drop the frame and DUT TX will transmit NAC

- Idea is tc0 data frame is preempted by tc1 data frame and tc1 data frame is again preempted by control frame and on resume of tc1 data frame tc of tc1 cof got corrupted to TC0 -- Expected DUT response : Drop corrupted frame and send NAC

- Transmit Receives N randomized transfer between 1 to DL_MTU and ACKs are randmoly grouped up to 16 packets and random delay inserted between the ACKs. - Random delay between the packets. - Both TC0 and TC1 traffic is enabled together. It should lead to arbitrations and pre-emptions.

Stimulus: BFM TX and DUT TX send N transactors of TC1 and TC0 traffic class concurrently Response: BFM RX Receives N transactors and schedules AFC for them. ACK grouping is enabled for both TC0 and TC1 Traffic Classes

- Transmit and Receives N randomized transfer between 1 to DL_MTU and ACKs are randmoly grouped up to 16 packets and random delay inserted between the ACKs. - Random delay between the packets.

Stimulus: BFM TX and DUT TX send N transactors of TC1 and TC0 traffic class concurrently Response: BFM RX Receives N transactors and schedules AFC for them. ACK grouping is enabled either for TC0 or for TC1

- Receives N transactors(packets/frames) with random data payload size between 1 to DL_MTU and ACKs immediately if they are correct

Stimulus: BFM RX Receives N randomized transfer from the DUT TX Response: BFM TX sends AFCs as soon as the BFM RX receives the Data frames

- Transmits and Receives N transactors(packets/frames) with random data payload size between 1 to DL_MTU and ACKs immediately if they are correct

Response: BFM RX Receives N transactors from the DUT TX and Parallely BFM TX Tranmsit N transactors Stimulus: BFM TX sends AFCs (before AFCx_REQUEST_TIMER expires) after BFM RX receives transactors

- Transmits N transactors(packets/frames) with random data payload size between 1 to DL_MTU

Stimulus: BFM TX transmits a data frame Expected Response: BFM RX should receive an ACK before the TCx_Replay_Timer expires

- Injecting any applicable random error on L2 Transactors

Stimulus: BFM TX will do random error injection Response:

- Corrupt Reserved Bits - Now, At DUT Rx side Reserved bits will be ignored - So, DUT Rx will just ignore these corrupted bits and Dont schedule NAC Frame

User Interface: - NA

Expected Response from DUT: - Ignored those corrupted reserved bits - Dont schedule NAC Frame - Accept a AFC Frame

Response from BFM:

- Sending AFC frame of those frame, which started replaying - i.e. Pause AFC transmission at BFM untill DUT end started to RTX of Unacknowledge Frames

User Interface: - NA

Expected Response from DUT: - The DUT's TCx_REPLAY_TIMER must timeout, after which it must transmit a NAC with RReq bit set - Then, the DUT must transmit an AFC of TC1 followed by the Unacknowledged TC1 Data Frames - Later, an AFC of TC0 must be transmitted followed by Unacknowledged TC0 Data Frames - Flow control information should be updated by the DUT.

- Transmission of COF, EOF_EVEN or EOF_ODD when no data frame was started, NAC is expected from the DUT

User Interface: - Instead of SOF ctrl symbol - transmit COF ctrl symbol - transmit EOF_ODD ctrl symbol - transmit EOF_EVEN ctrl symbol

Expected Response from DUT: - Drop Rx Frame and transmit NAC

Response from BFM: - Re-Transmission of that frame, but, this time, without injecting any error

- Transmit COF symbol for different TC than it supposed to - e.g. SOF symbol with TC=0, DATA, COF symbol with TC=1

User Interface: - Choose other TCx than Original TC

Expected Response from DUT: - Drop Frame and transmit NAC

Response from BFM: - Re-Transmission of that frame, but this time with no any error injection

Spec Address: - SPEC_V_1_4 : 6.6.11, Para 2057

- There arent any pre-emption. - TC0 data frame is in progress and COF is received. - TC1 data frame is in progress and COF is received.

User Interface: - NA

Expected Response from DUT: - Drop the Frame and transmit NAC

Response from BFM: - Re-Transmission of that frame, but this time with no any error injection

Spec Address:

- AFC and NAC with corrupted CRC-16

User Interface: - NA

Expected Response from DUT: - Drop that Frame and transmit NAC

Response from BFM: - Re-Transmission of that frame, but this time with no any error injection

Spec Address: - SPEC_V_1_4 : 6.6.11, Para 2045

- Transmits the Control symbol with the Corrupt ESC_DL Indentifier. - Encoded with value except 8'b00000001

Expected Response from DUT: - Drop that Frame at L1P5 Layer and DUT L1P5 Layer trigger PA_ERROR to L2 and DUT L2 will transmit NAC

Response from BFM: - As Receiption of NAC frame, BFM will re-send that frame followed by AFC Frame

Spec Address: - SPEC_V_1_4 : 6.5.2

- Transmits the Control symbol with the TC encoding of 10, 11 which are reserved.

User Interface: - Choose between any Reserved Type TC

Expected Response from DUT: - Drop that Frame and transmit NAC

Response from BFM: - Re-Transmission of that frame, but this time with no any TC error injection

Spec Address: - SPEC_V_1_4 : 6.6.11, Para 2059

- Transmits the Control Symbol with the RSVD Control Symbol Type encoding.

User Interface: - User can choose any one Reserved Control Symbol Type

Expected Response from DUT: - Drop that Frame and transmit NAC

Response from BFM: - After Reception of NAC frame, BFM will re-send that frame followed by an AFC Frame, but this time without injecting any error

Spec Address:

- Corrupt Reserved Bits of SOF/COF Control Symbol - Now, At DUT Rx side Reserved bits will be ignored - So, DUT Rx will just ignore these corrupted bits and Dont schedule NAC Frame - DUT will schedule AFC Frame

User Interface: - NA

Expected Response from DUT: - Ignored those corrupted reserved bits - Dont schedule NAC Frame - Accept a Data Frame and schedule corresponding AFC Frame

- Transmits data frame whose size is greater than the DL_SYMBOL_MTU

User Interface: - NA

Expected Response from DUT: - Drop that Frame and transmit NAC

Response from BFM: - Re-Transmission of that frame, but this time without injecting any error

Spec Address: - SPEC_V_1_4 : 6.6.11, Para 2047

- Transmits data frame with corrupt CRC and expects a NAC response from the DUT

User Interface: - NA

Expected Response from DUT: - Drop the Frame and transmit NAC

Response from BFM: - Re-Transmission of the frame, but this time without injecting any error

Spec Address: - SPEC_V_1_4 : 6.6.11, Para 2045

- Transmits data frame with the the Sequence number that is already ACKed

User Interface: - NA

Expected Response from DUT: - Just Drop that Frame - As DUT's FSN Manager consider this frame as Re-Transimitted Frame, and Drop this frame - But, ACK will be schedule for this Data Frame - Credit will not be updated

- Consider as AFC droped by DUT

- Transmits data frame with a random incorrect Sequence number and expects a NAC response from DUT

User Interface: - NA

Expected Response from DUT: - Drop that Frame and transmit NAC

Response from BFM: - Re-Transmission of that frame, but this time without injecting any error

Spec Address: - SPEC_V_1_4 : 6.6.11, Para 2048

- Drop COF control symbol of resuming L2 frame

User Interface: - NA

Expected Response from DUT: - NAC transmission

Response from BFM: - Re-Transmission of that frame, but, this time, without injecting any error

Spec Address: - SPEC_V_1_4 : 6.6.11, Para 2058

- Transmit some symbols out of total symbols of L2 Data Frame - e.g. EOF_EVEN/EOF_ODD without CRC symbol, NAC is expected from the DUT

User Interface: - Gives No. of Symbols to be transmit

Expected Response from DUT: - Drop Rx Incomplete Frame and transmit NAC

Response from BFM: - Re-Transmission of that frame, but, this time, without injecting any error

Spec Address:

- AFCx symbol without the last two data symbols, NAC expected from the DUT

User Interface: - AFCx Frame without last two data symbols (FSN_CRD Data Symbol, CRC Data Symbol) - AFCx Frame without last one data symbol (CRC Data Symbol)

Expected Response from DUT: - Timer Timeout happen and NAC will be scheduled for that (TCx_REPLAY_TIMER at DUT and AFCx_REQUEST_TIMER at BFM) - Drop Rx Incomplete Frame

Response from BFM: -

- NAC symbol without the last data symbol, NAC expected from the DUT

User Interface: - NA

Expected Response from DUT: - DUT must Drop the received Incomplete Frame and transmit NAC

Response from BFM: -

Spec Address: - SPEC_V_1_4 : 6.6.11, Para 2050

- Send NAC when there are nooutstanding frames to be acked.

User Interface: - NA

Expected Response from DUT: - Transmit AFC Frames

Response from BFM: - None

Spec Address: - SPEC_V_1_4 : 6.6.8.2, Para 1949

- Send the NAC randmomly when there are outstadnding Frames to be acknowledged.

User Interface: - NA

Expected Response from DUT: - Transmit AFC Frames and all Unacknowledge Data Frames for all TCs according to priority scheme

Response from BFM: - None

Spec Address: - SPEC_V_1_4 : 6.6.8.2, Para 1949

- BFM transmits NAC randomly after receiving random data frames less than 16 and then ACK the Data frames requested for the retransmisson. DUT is expected to complete retransmission.

- Sending NAC frame instead of AFCs Frame during Normal Transmission, - Then send some AFCs for Replayed Data Frame and Again randomly send NAC during RTX is in Progress

User Interface: - NA

Expected Response from DUT: - DUT must correctly re-transmit the unacknowledged Frame

- Corrupt Reserved Bits - Now, At DUT Rx side Reserved bits will be ignored - So, DUT Rx will just ignore these corrupted bits and Dont schedule NAC Frame

User Interface: - NA

Expected Response from DUT: - Ignored those corrupted reserved bits - Dont schedule NAC Frame - Accept a NAC Frame

- Send SOF instead COF control symbol while resuming L2 frame

User Interface: - NA

Expected Response from DUT: - NAC transmission

Response from BFM: - Re-Transmission of that frame, but, this time, without injecting any error

Spec Address: - SPEC_V_1_41: 6.6.11

- Pre-Emption happen between same TCx - TCO SOF sent when the TC0 data frame is in progress. - TC1 SOF sent when the TC1 data frame is in progress. - e.g. - when no preemption has occurred for the started Frame - SOF symbol with TC=0/1, DATA, SOF symbol with TC=0/1

- when an earlier preemption has completed and the ongoing TC0 Data Frame is no longer preempted - SOF symbol with TC=0/1, DATA, AFC symbol, DATA, DATA, COF symbol with TC=0/1, DATA, SOF symbol with TC=0/1

User Interface: - NA

- TC0 SOF sent when the TC1 data frame is in progress.

User Interface: - NA

Expected Response from DUT: - Drop both Frames and transmit NAC

Response from BFM: - Re-Transmission of that frame, but this time without injecting any error

Spec Address: - SPEC_V_1_4 : 6.6.11, Para 2055 - Transmit TCx Data Frame with data payload of non integral mutilple of 32 bytes

Expected Response from DUT: - DUT has to update respective TC Partial Credits

- Send the AFC with CReq bit set and the AFC response should be received by the DUT.

User Interface: - NA

Expected Response from DUT: - DUT must advertise its Credit Info - Andto this case shall be transmission of AFCx with priority promoted, even when DL_PeerTCxPresent is FALSE

Response from BFM: -

Spec Address:

- unexpected framing Sequence - data symbol received between frames - Back2Back Control Symbols (SOF,AFC,EOF,COF,NAC)

User Interface: - NA

Expected Response from DUT: - DUT must drop the Frame and transmit NAC

Response from BFM: - Re-Transmission of that frame, but, this time, without injecting any error

Spec Address:

- A SOF symbol during an ongoing Frame of the same TC is permitted when a replay starts, but only when the Frame is preempted, as a replay always generates an AFC Frame before any replayed Data Frame. For example, the symbol sequence (SOF symbol with TC=0, DATA, AFC symbol, DATA, DATA, SOF symbol with TC=0) is valid and does not generate a NAC Frame, since the second SOF symbol with TC=0 represents the beginning of a replayed Data Frame.

User Interface: - NA

Expected Response from DUT: - DUT mustn't send a NAC, it should send an AFC instead - It must accept the Replayed Data Frame

- Causing TC1 Credit blocking and meanwhile TC0 has enough Credits to transmit TC0 Data Frames

Stimulus: BFM Config has lesser TC1 Credits than TC0, So, BFM TX might tranmsit TC0 Data Frames first and then TC1 Data Frames Response: DUT TX responds with AFCs after DUT RX receives the Data Frames

- Causing TC1 FSN blocking and meanwhile TC0 Data Frames can make progress

Stimulus: DUT Config have ACK Grouping facility for TC1 and single ACKing for TC0 Response: DUT TX Responds with AFCs when DUT RX receives Data Frames

Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over TC0

Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over both the TC0 and TC1.

Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over TC0

Tranasmits and receive N randomized packet between 1 to N_MTU of Long Packet type over both the TC0 and TC1 with both the short and long header packet types.

Send long header packet to DUT and it should discard it when its not supporting the long headers. And check for the LHDR_TRAP_PACKET_DROPPING indication passeed via the LME

Transmit Packet to DUT with the DeviceID not supported by the DUT. DUT is expected to discard the Packet and report to its LME.

1. Test verifies the connection management by connecting cports from both the sides, and do one data transfer and verifies the connection status and data integrity. 2. Test verifies the status and result codes after disconnecting the already paired cport pair. 3. Test verifies the connection management of the disconnected cport with other cport and do one data transfer and verifies the connection status and data integrity.

Tranasmits a msg on cport of status indication of NO_PEER_TC. RESPONSE: result code shall be NO_PEER_TC

Tranasmits fc req in continious cycle, get the t_tx_result code = CREDIT EXCEED on INTERFACE and t_credit_accepted = deducted credit (the credit which is accepted by cport) RESPONSE: result code shall be CREDIT EXCEED

Disable the E2E flow control. Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary length defined by (T_MaxSegmentSize) from BFM and DUT.

Stimulus: - Test app tx message (T_SDUs) with random data of random size to DUT and BFM.

Response: - RX - DUT receive the segments,compose the segments and form the message. - DUT shall generat T_CO_DATA.ind( MessageFragment, EOM, SOM, FragmentStatus ). - FragmentStatus = FRAGMENT_CORRECT

Disable the E2E flow control. Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary length defined by (T_MaxSegmentSize) from BFM and DUT.

Stimulus: - Test app tx message (T_SDUs) with random data of random size to DUT and BFM.

Response: - RX - DUT receive the segments,compose the segments and form the message. - DUT shall generat T_CO_DATA.ind( MessageFragment, EOM, SOM, FragmentStatus ). - FragmentStatus = FRAGMENT_CORRECT

Random connect and disocnnect is enabled. DUT Cports will be connected to random CPort and TCx of the BFM Random sized Messages and FLOWCONTROL request will be generated for both the DUT and BFM

Stimulus: - Test app tx message (T_SDUs) with random data of random size to DUT and BFM for random cports

Response: - RX - DUT receive the segments,compose the segments and form the message for each cport. - DUT shall generat T_CO_DATA.ind( MessageFragment, EOM, SOM, FragmentStatus ).

Tranasmits and receive 1 randomized message (T_SDUs) with sequential data payload of fixed size from DUT.

Stimulus: - Test app tx message (T_SDUs) with sequential data of fixed size, to DUT and BFM.

Response: - RX - DUT receive the segments,compose the segments and form the message. - DUT shall generat T_CO_DATA.ind( MessageFragment, EOM, SOM, FragmentStatus ). - FragmentStatus = FRAGMENT_CORRECT - TX - DUT decompose the message (T_SDUs) into segments (T_PDU) and

Transmit a segment with the correct size, correct TC with the incorrect DestCPortID, it will be discarded by DUT.

Stimulus: - Test app tx message (T_SDUs) to BFM. - Inject the error and corrupt the DestCPortID.

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ). - L4DiscardReasonCode = UNKNOWN_CPORTID

Transmit a segment with the correct size but with the incorrct TC

Stimulus: - Test app tx message (T_SDUs) to BFM. - Inject the error and change the TC of that cport

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ). - L4DiscardReasonCode = BAD_TC

Send the Segment without any payload and EOM set. Send a new segment followed by it. Things should function normally.

Stimulus: - Test app tx message (T_SDUs) with zero size to BFM.

Response: - RX - DUT receive the segments,compose the segments and form the message for each cport. - DUT shall generat T_CO_DATA.ind( MessageFragment, EOM, SOM, FragmentStatus ). - FragmentStatus = FRAGMENT_CORRECT

Establish the connection with the CPortID greater than 31. Transmit and receive the Segments. DeviceIDOffset will be used.

Stimulus: - Test app tx message (T_SDUs) with random data of random size to DUT and BFM for cports having cportid greater than 31

Response: - RX - DUT receive the segments,compose the segments and form the message for each cport. - DUT shall generat T_CO_DATA.ind( MessageFragment, EOM, SOM, FragmentStatus ). - FragmentStatus = FRAGMENT_CORRECT

Transmit the segment with the FCT set in segments with payload and without payload. DUT is expected to drop the segment or ignore the FCTs

Stimulus: - Test app tx message (T_SDUs) with zero size to BFM. - Inject the error and set the fct true

Response: - RX - Refer to mipi_unipro_spec_l4_tl_ambiguity.txt

Transmit the segment with the L4s=0 from BFM and DUT is expected to discrad and send the notification.

Stimulus: - Test app tx message (T_SDUs) to BFM. - Inject the error and set the L4s false

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ). - L4DiscardReasonCode = UNSUPPORTED_HEADER_TYPE

Transmit a correct data segment with FCT=0 when DUT is not in the CONNECTED state Transmit a correct data segment with FCT=1 when DUT is not in the CONNECTED state Transmit a correct data segment with EOM=1 when DUT is not in the CONNECTED state All of the them should be discarded.

Stimulus: - Make the connect state idle - Test app tx message (T_SDUs) to BFM. - Test app tx FC req to BFM.

Response: - RX

Transmit the zero sized segment with the EOM set to false.

Stimulus: - Test app tx message (T_SDUs) with zero size to BFM. - Inject the error and set the eom false

Response: - RX - Refer to mipi_unipro_spec_l4_tl_ambiguity.txt

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary length defined by (T_MaxSegmentSize) from BFM and DUT.

Stimulus: - Test app tx message (T_SDUs) with random data of random size to DUT and BFM.

Response: - RX - DUT receive the segments,compose the segments and form the message. - DUT shall generat T_CO_DATA.ind( MessageFragment, EOM, SOM, FragmentStatus ). - FragmentStatus = FRAGMENT_CORRECT - TX

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary length defined by (T_MaxSegmentSize) from BFM and DUT.

Stimulus: - CSV_n enable - Test app tx message (T_SDUs) with random data of random size to DUT and BFM.

Response: - RX - DUT receive the segments,compose the segments and form the message. - DUT shall generat T_CO_DATA.ind( MessageFragment, EOM, SOM, FragmentStatus ). - FragmentStatus = FRAGMENT_CORRECT

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary length defined by (T_MaxSegmentSize) from BFM

Stimulus: - Test app tx message (T_SDUs) with random data of random size to BFM.

Response: - RX - DUT receive the segments,compose the segments and form the message. - DUT shall generat T_CO_DATA.ind( MessageFragment, EOM, SOM, FragmentStatus ). - FragmentStatus = FRAGMENT_CORRECT

Tranasmits N randomized segments (T_PDUs) between 1 to implementation defined arbitrary length defined by (T_MaxSegmentSize) from BFM

Stimulus: - Test app tx message (T_SDUs) with random data of random size to DUT.

Response: - TX - DUT decompose the message (T_SDUs) into segments (T_PDU) and send them to peer side. - Segments (T_PDUs) between 1 to implementation defined arbitrary length defined by (T_MaxSegmentSize)

Transmit a segment with the size greater than T_MTU. The DUT must discard it.

Stimulus: - Test app tx message (T_SDUs) to BFM. - Inject the error and set increase the paylaod of segment greater than TMTU

Response: - RX - Refer to mipi_unipro_spec_l4_tl_ambiguity.txt

Transmit a segment with the less than T_MTU with out EOM bit to set The DUT must discard it.

Stimulus: - Test app tx message (T_SDUs) to BFM. - Inject the error and set increase the paylaod of segment greater than TMTU

Response: - RX - Refer to mipi_unipro_spec_l4_tl_ambiguity.txt

Corrupt the CportID.Take the specific error percentage from the command line for corrupting CportID and randomly inject the error into the segment on the basis of percentage.

Stimulus: - Test app tx message (T_SDUs) of random size to BFM - Randomly injected and few specific error injection knobs set to specific values below +CORR_SEG_DEST_CPORT_ID=40

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ). - L4DiscardReasonCode = UNKNOWN_CPORTID

Corrupt the TC.Take the specific error percentage from the command line for corrupting TC and randomly inject the error into the segment on the basis of percentage.

Stimulus: - Test app tx message (T_SDUs) of random size to BFM - Randomly injected and few specific error injection knobs set to specific values below +CORR_L4_SEG_TC=40

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ). - L4DiscardReasonCode = BAD_TC

Corrupt the EOM.Take the specific error percentage from the command line and randomly inject the error into the segment on the basis of percentage.

Stimulus: - Test app tx message (T_SDUs) of random size to BFM - Randomly injected and few specific error injection knobs set to specific values below +CORR_SEG_EOM=40 Response: - RX -- Refer to mipi_unipro_spec_l4_tl_ambiguity.txt

Corrupt the FC.Take the specific error percentage from the command line and randomly inject the error into the segment on the basis of percentage.

Stimulus: - E2EFC disable - Test app tx message (T_SDUs) of random size to BFM - Randomly injected and few specific error injection knobs set to specific values below +CORR_SEG_FCT_E2EFC0=40

Response: - RX -- Refer to mipi_unipro_spec_l4_tl_ambiguity.txt

Corrupt HDR .Take the specific error percentage from the command line and randomly inject the error into the segment on the basis of percentage.

Stimulus: - E2EFC disable - Test app tx message (T_SDUs) of random size to BFM - Randomly injected and few specific error injection knobs set to specific values below +CORR_L4_HDR=40

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ).

Corrupt the DATA PAYLOAD SIZE.Take the specific error percentage from the command line for corrupting msg data payload and randomly inject the error into the segment on the basis of percentage.

Stimulus: - Test app tx message (T_SDUs) of random size to BFM - Randomly injected and few specific error injection knobs set to specific values below +CORR_L4_SEG_DATA_PAYLOAD_SIZE=40

Response: - RX -- Refer to mipi_unipro_spec_l4_tl_ambiguity.txt

Take the specific error percentage from the command line and randomly inject the error into the segment on the basis of percentage.

Stimulus: - E2EFC is disable - Test app tx message (T_SDUs) of random size to BFM - Enabling multiple error injection knobs listed below: +CORR_L4_HDR=10 +CORR_SEG_DEST_CPORT_ID=10 +CORR_L4_SEG_TC=10 +CORR_L4_SEG_DATA_PAYLOAD_SIZE=10 +CORR_SEG_EOM=10 +CORR_SEG_FCT_E2EFC0=10

Take the layer error percentage from the command line and randomly inject the error into the segment on the basis of percentage.

Stimulus: - Test app tx message (T_SDUs) of random size to BFM - +L4_ERR_INJ_PERCENTAGE=50 - This gets randomly distributed among all possible L4 errors and gets randomly injected.

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ). - L4DiscardReasonCode - According to the error detected on RX

Take the specific error percentage from the command line and randomly inject the error into the segment on the basis of percentage.

Stimulus: - Test app tx message (T_SDUs) of random size to BFM - Enabling multiple error injection knobs listed below: +CORR_L4_HDR=20 +CORR_SEG_DEST_CPORT_ID=20 +CORR_L4_SEG_TC=10 +CORR_L4_SEG_DATA_PAYLOAD_SIZE=10 +CORR_SEG_EOM=10

Response:

Take the specific error percentage from the command line and randomly inject the error into the segment on the basis of percentage.

Stimulus: - Test app tx message (T_SDUs) of random size to BFM - Randomly injected and few specific error injection knobs set to specific values below +CORR_SEG_STATE=40

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ). - L4DiscardReasonCode = E2E_CREDIT_OVERFLOW

Stimulus:

Response:

Consume part of the credits advertised. Then send an segment with the size greater than the credits available at DUT.

Stimulus: - E2EFC IS diable and CSD feature is enable - Test app tx message (T_SDUs) to BFM which consume patial credit. - Test app tx message (T_SDUs) to BFM when partial credit is available.

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ). - L4DiscardReasonCode = CONTROLLED_SEGMENT_DROPPING

Consume part of the credits advertised. Then send an segment with the size greater than the credits available at DUT. Segment will be discarded

Stimulus: - Test app tx message (T_SDUs) to BFM which consume patial credit. - Test app tx message (T_SDUs) to BFM when partial credit is available.

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ). - L4DiscardReasonCode = E2E_CREDIT_OVERFLOW

Consume all the credits advertised. Then send an segment when the zero credits are available to DUT.Segment will be discarded

Stimulus: - Test app tx message (T_SDUs) to BFM which consume all credit. - Test app tx message (T_SDUs) to BFM when zero credit available.

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ). - L4DiscardReasonCode = E2E_CREDIT_OVERFLOW

Consume all the credits advertised by app at RX side. Then send an segment when the zero credits are available to DUT.

Stimulus: - E2EFC IS diable and CSD feature is enable - Test app tx message (T_SDUs) to BFM which consume all credit. - Test app tx message (T_SDUs) to BFM when zero credit available.

Response: - RX - DUT shall generate T_LM_DISCARD.ind( CPortID, L4DiscardReasonCode ). - L4DiscardReasonCode = CONTROLLED_SEGMENT_DROPPING

Test verifies the error codes with the test features like no error, fragment corrupt, invalid message size and unexpected byte value.

Programs the following parameters and checks that the recieved data is as per the requirement - T_TstSrcOn - T_TstSrcMessageCount - 0 (infinite messages) and finite count - T_TstSrcMessageSize - 1 to 65535 - T_TstSrcPattern - Sawtooth pattern - T_TstSrcIncrements - added to value of each subsequent byte and rolls over after 255 - T_TstSrcInterMessageGap - gaps between the consecutive messages in us

Regular credits consistency checks and all other header format checks are active during the test mode as well.

Programs the following parameters and checks that the recieved data is as per the requirement - T_TstSrcOn - T_TstSrcMessageCount - 0 (infinite messages) and finite count - T_TstSrcMessageSize - 1 to 65535 - T_TstSrcPattern - Sawtooth pattern

- T_TstSrcIncrements - added to value of each subsequent byte and rolls over after 255 - T_TstSrcInterMessageGap - gaps between the consecutive messages in us

Regular credits consistency checks and all other header format checks are active during the test mode as well.

Programs the following parameters and checks that the recieved data is as per the requirement - T_TstSrcOn - T_TstSrcMessageCount - 0 (infinite messages) and finite count - T_TstSrcMessageSize - 1 to 65535 - T_TstSrcPattern - Sawtooth pattern - T_TstSrcIncrements - added to value of each subsequent byte and rolls over after 255 - T_TstSrcInterMessageGap - gaps between the consecutive messages in us

Regular credits consistency checks and all other header format checks are active during the test mode as well.

[1] Read and store the attributes expected to be restored before hibernate entry [2] Initiate hibernate entry. Wait for a random duration. Cause a hibernate exit [3] Read the attributes expected to be restored after hibernate exit and check with values stored before the hibernate entry

Required Parameters: L1.5 PA_ConnectedTxDataLanes, PA_ConnectedRxDataLanes PA_LogicalLaneMap PA_MaxRxPWMGear, PA_MaxRxHSGear PA_RemoteVerInfo PA_SleepNoConfigTime, PA_StallNoConfigTime, PA_SaveConfigTime PA_RxHSUnterminationCapability, PA_RxLSTerminationCapability Start a custom dme write and, then, a read sequence that writes/reads one of the registers(ATTID_DL_TC0TXFCThreshold).

Only applicable for the DUT [0] Do the Register Write/Read operations in RTL for all UniPro Registers Addr Valid range : 'h1500 -to- 'h4100 [1] Power on reset values are correct for all the attributes. -Attribute values are read immediately after power on and compared with the resp. reset values [2] Read/Write attribute check - Here, writes are performed on all settable UniPro attributes after which the values are read back to ensure that the values were updated.

DME LM_SET_* / LM_GET_* functions

Stimulus: Do the Register Write/Read operations by using PA_LM_SET.req & PA_LM_GET.req in RTL L1P5 Registers for the - Invalid Attribute Addr's - Invalid Wr / Rd Accesses.

Addr Valid range : 'h1500 -to- 'h15A4

L1.5: 1. Test verifies the case where an attempt to set read only Attributes shall be rejected with a READ_ONLY_MIB_ATTRIBUTE error. 2. Test verifies the case wherein an attempt to access an Attribute of an unavailable Lane shall be rejected with a BAD_INDEX error.

Start user CPORT CONNECT sequence(unipro_user_cport_connect_seq) by overriding the spec_attrb CPORT CONNECT(unipro_cport_connect_seq) sequence

Start user DUT INIT sequence(unipro_user_dut_init_sequence) by overriding the spec_attrb DUT INIT(unipro_dut_init_sequence) sequence

TESTNAME
compliance_l1p5_two_custom_power_mode_change

compliance_normal_l1p5_bad_phy_symb

compliance_pa_init_phase_err_and_recovery

directed_test_l1p5_pacp_corruption

compliance_l1p5_bfm_not_start_linkstartup_till_dut_timeout

NA

compliance_l1p5_deskew_insertion

unipro_l1p5_terminate_link_startup

directed_test_l1p5_pacp_corruption

compliance_l1p5_pacp_pwr_req_busy_err_success_response

test_l1p5_pacp_concurrency_resolution

test_l1p5_pacp_concurrency_resolution

compliance_l1p5_dut_reject_local_invalid_power_req

unipro_l1p5_pacp_ep_reset

unipro_l1p5_pacp_ep_reset

directed_test_l1p5_framing_corruption

unipro_tb_base_test

unipro_tb_base_test

compliance_pa_init_phase_err_and_abort

directed_test_l1p5_framing_corruption

unipro_l1p5_terminate_link_startup

unipro_random_lock_unlock_l1p5_init_phases

unipro_l1p5_link_startup_sequence_start_on_bfm_end_n_dut_end

unipro_l1p5_link_startup_sequence_start_on_bfm_end_n_dut_end

unipro_l1p5_link_startup_sequence_start_on_bfm_end_n_dut_end

compliance_l1p5_lane2lane_skew_gt_2_pa_symbols_pacp_frame

unipro_bfm_pa_init_line_reset

unipro_l1p5_pa_init_line_reset

directed_test_l1p5_pacp_get_set_corruption

directed_test_l1p5_pacp_get_set_corruption

unipro_l1p5_pacp_get_req

unipro_l1p5_pacp_pwr_req

compliance_l1p5_pacp_not_complete_test

unipro_tb_base_test

unipro_tb_base_test

compliance_l1p5_not_changing_pwr_mode_bit_long_duration_of_time

unipro_dut_pa_init_nac_rreq_set

unipro_l1p5_hibernate_entry_n_exit

compliance_test_l1p5_pacp_crc_corruption

test_l1p5_corr_pacp_frame_esc_param_pa

compliance_l1p5_init_pacp_cap_err_inj

test_l1p5_pacp_cap_ind_corruption

directed_test_l1p5_pacp_get_set_corruption

test_l1p5_pacp_pwr_cnf_status_corruption

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_abort

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_abort

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_recovery

compliance_pa_init_phase_err_and_abort

compliance_pa_init_phase_err_and_recovery

directed_test_l1p5_pacp_corruption

test_l1p5_invalid_pwr_mode_config_detection

test_l1p5_pacpreq_eob_timeout

directed_test_l1p5_pacp_corruption

compliance_l1p5_pwr_mode_with_user_data

compliance_l1p5_rand_symbols_before_sob

test_rand_unipro_l1p5_pwr_mode_change

test_rand_unipro_l1p5_pwr_mode_change

compliance_pa_init_phase_err_and_skip_phase

unipro_pa_phy_test

unipro_l1p5_init_bfm_init_restart_PH_test

compliance_pa_init_phase_err_and_recovery

unipro_l1p5_linkup_state_after_warm_reset

unipro_l1p5_linkup_state_after_warm_reset

test_afc_init_credit_val

test_legal_l2_preemption

test_cause_afc_transmission

test_cause_afcx_request_timer_expiration

test_cause_fcx_protection_timer_expiration

test_cause_tcx_replay_timer_expiration

test_fail_pa_init

directed_test_frame_field_corruption

test_replayed_low_priority_frame_pre_empted_by_non_replayed_high_priority_frame

directed_test_frame_field_corruption

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_change_link_properties

test_l2_layer_percentage_err_inj

test_duplicate_control_afc_frame

test_dut_grouped_acknowledgment

test_cause_fcx_protection_timer_expiration_during_l2_init

test_illegal_l2_preemption

test_multilevel_preemption_corr_cof_tc

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

test_l2_layer_percentage_err_inj

test_corr_afc_frame_rsvd_bits

test_tx_afc_fsn_when_same_fsn_data_frame_rtx

directed_test_frame_field_corruption

directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

directed_test_frame_field_corruption

directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj

directed_test_frame_field_corruption

test_l2_layer_percentage_err_inj

test_data_frame_prev_acked_fsn

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

test_control_frame_corrupt_crc

test_nac_transmission_when_outstanding_frame_rem_to_acked_specified

test_nac_transmission_when_outstanding_frame_rem_to_acked_specified

test_l2_layer_percentage_err_inj

test_corr_nac_frame_rsvd_bits

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

test_l2_layer_percentage_err_inj

test_credit_flow_control

test_compliance_tx_afc_w_creq_set

test_l2_layer_percentage_err_inj

test_pre_emption_by_replay_frame_of_same_tc

test_tc1_block_tc0_progress

test_tc1_block_tc0_progress

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

compliance_dut_long_header_drop

test_compliance_corr_device_id_enc

compliance_l4_connect_disconnect_cport

NA

NA

unipro_tb_base_test

unipro_tb_base_test

test_message_normal_with_fct_updation

unipro_single_message_single_sequence_test

directed_test_segment_field_corruption

directed_test_segment_field_corruption

test_segment_zero_size_data_eom1

unipro_tb_base_test

directed_test_segment_field_corruption

directed_test_segment_field_corruption

compliance_tx_seg_incorr_connectstate

test_segment_zero_size_data_eom_field_corruption

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

unipro_tb_base_test

directed_test_segment_field_corruption

directed_test_segment_field_corruption

test_segment_percentage_e_rr_or

test_segment_percentage_e_rr_or

test_segment_percentage_e_rr_or

test_segment_percentage_e_rr_or

test_segment_percentage_e_rr_or

test_segment_percentage_e_rr_or

test_segment_percentage_e_rr_or

test_segment_percentage_e_rr_or

test_segment_percentage_e_rr_or

test_segment_percentage_e_rr_or

test_seg_dropped_csv_enable

test_segment_RxBuffer_overflow_e2efc1_credit_grt0

test_segment_RxBuffer_overflow_e2efc1_credit_grt0

test_segment_RxBuffer_overflow_e2efc1_credit0

test_segment_RxBuffer_overflow_e2efc1_credit0

NA

test_message_test_feature

test_message_test_feature

test_message_test_feature

compliance_retained_attr_restore_after_hibern8_test

compliance_unipro_basic_attribute_write_read_test

compliance_dme_lm_set_get

compliance_normal_l1p5_lm_set_get_err

unipro_single_message_single_cport_ral_test

unipro_dut_init_user_ral_test

LOGNAMES
compliance_l1p5_two_custom_power_mode_change_uvm.log

PRIOIRITY

P0

compliance_normal_l1p5_bad_phy_symb_uvm.log

P0 compliance_pa_init_all_phase_trg_uprx_e_rr_or_and_recovery_uvm.l og

P0

compliance_l1p5_line_reset_bfm_hibernate_req_uvm.log compliance_l1p5_line_reset_bfm_pacp_pwr_req_uvm.log

P0 compliance_l1p5_bfm_not_start_linkstartup_dut_timeout_uvm.log

P0

compliance_l1p5_test_mode_initiated_by_bfm_uvm.log

P0 compliance_l1p5_deskew_insetion_multi_lane_uvm.log compliance_l1p5_deskew_insetion_single_lane_uvm.log compliance_l1p5_deskew_pattern_insetion_btwn_data_single_lane_u vm.log compliance_l1p5_insertion_of_dskew_pattern_on_multiple_lane_in_b twn_data_dl_frame_uvm.log

P0

compliance_l1p5_init_abort_phase_0_warm_reset_uvm.log compliance_l1p5_init_abort_phase_0b_warm_reset_uvm.log compliance_l1p5_init_abort_phase_1_warm_reset_uvm.log compliance_l1p5_init_abort_phase_2_warm_reset_uvm.log compliance_l1p5_init_abort_phase_3_warm_reset_uvm.log compliance_l1p5_init_abort_phase_4_warm_reset_uvm.log

P0

compliance_l1p5_line_reset_hibernate_req_uvm.log compliance_l1p5_line_reset_pacp_pwr_req_uvm.log

P0

compliance_l1p5_pacp_pwr_req_busy_err_success_response_uvm.log compliance_l1p5_pacp_pwr_req_err_busy_success_response_uvm.log

P0

compliance_l1p5_hibenate_race_dut_reject_local_req_when_remote _req_is_in_process_uvm.log compliance_l1p5_pwr_mode_n_hibernate_race_dut_reject_local_req _when_remote_req_is_in_process_uvm.log compliance_l1p5_pwr_mode_race_dut_reject_local_req_when_remot e_req_is_in_process_uvm.log

P0

compliance_l1p5_dut_reject_local_and_remote_hibernate_req_bfm_f alse_and_dut_false_uvm.log compliance_l1p5_dut_reject_local_hiberante_req_bfm_true_and_dut _true_uvm.log compliance_l1p5_dut_reject_local_hibernate_req_bfm_true_and_dut _false_uvm.log compliance_l1p5_dut_reject_local_power_req_bfm_true_and_dut_fal se_uvm.log compliance_l1p5_dut_reject_local_power_req_bfm_true_and_dut_tru e_uvm.log compliance_l1p5_dut_reject_remote_hiberante_req_bfm_false_and_ dut_true_uvm.log compliance_l1p5_dut_reject_remote_hiberante_req_bfm_true_and_d ut_true_uvm.log compliance_l1p5_dut_reject_remote_power_req_bfm_false_and_dut _true_uvm.log compliance_l1p5_dut_reject_remote_power_req_bfm_true_and_dut_ true_uvm.log compliance_l1p5_hibenate_race_bfm_req_reject_uvm.log compliance_l1p5_pwr_mode_n_hibernate_race_bfm_req_reject_uvm. log compliance_l1p5_pwr_mode_race_bfm_req_reject_uvm.log

P0 compliance_l1p5_dut_reject_local_invalid_power_req_uvm.log P0 compliance_l1p5_ep_reset_from_bfm_uvm.log

P0

compliance_l1p5_ep_reset_from_dut_uvm.log

P0 compliance_l1p5_data_eob_corr_pacp_uvm.log compliance_l1p5_data_eob_corr_uvm.log compliance_l1p5_data_eob_dnc_corr_uvm.log rand_l1p5_data_eob_dnc_corr_uvm.log

P0

compliance_l1p5_filler_corr_pacp_uvm.log compliance_l1p5_filler_corr_uvm.log compliance_l1p5_filler_dnc_corr_uvm.log rand_l1p5_filler_corr_uvm.log

P0

compliance_l1p5_data_sob_corr_dnc_uvm.log compliance_l1p5_data_sob_corr_pacp_uvm.log compliance_l1p5_data_sob_corr_uvm.log rand_l1p5_sob_dnc_corr_uvm.log

P0

compliance_l1p5_data_sob_corr_during_init_tx_phase_0B_uvm.log compliance_l1p5_data_sob_corr_during_init_tx_phase_0_uvm.log

P0

compliance_l1p5_res_err_inj_uvm.log

P0

compliance_l1p5_init_abort_phase_0_hibern_uvm.log compliance_l1p5_init_abort_phase_0b_hibern_uvm.log compliance_l1p5_init_abort_phase_1_hibern_uvm.log compliance_l1p5_init_abort_phase_2_hibern_uvm.log compliance_l1p5_init_abort_phase_3_hibern_uvm.log compliance_l1p5_init_abort_phase_4_hibern_uvm.log

P0 random_lock_unlock_l1p5_init_phases_uvm.log

P0

compliance_l1p5_init_start_dut_and_bfm_same_time_uvm.log

P0 compliance_l1p5_link_start_bfm_end_after_por_uvm.log

P0 compliance_l1p5_link_start_dut_end_after_por_uvm.log

P0

compliance_l1p5_lane2lane_skew_gt_2_pa_symbols_dl_frame_uvm.l og compliance_l1p5_lane2lane_skew_gt_2_pa_symbols_pacp_frame_uv m.log

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compliance_l1p5_bfm_line_reset_pa_init_DL_uvm.log

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compliance_l1p5_dut_line_reset_pa_init_DL_uvm.log

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compliance_l1p5_lm_peer_get_e_rr_or_peer_communication_failure _uvm.log compliance_l1p5_lm_peer_get_with_cnf_dropped_once_uvm.log compliance_l1p5_lm_peer_get_with_cnf_dropped_twice_uvm.log compliance_l1p5_lm_peer_set_e_rr_or_peer_communication_failure_ uvm.log compliance_l1p5_lm_peer_set_with_cnf_dropped_once_uvm.log compliance_l1p5_lm_peer_set_with_cnf_dropped_twice_uvm.log

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compliance_l1p5_lm_peer_get_e_rr_or_bad_index_uvm.log compliance_l1p5_lm_peer_get_e_rr_or_busy_uvm.log compliance_l1p5_lm_peer_get_e_rr_or_invalid_mib_attribute_uvm.lo g compliance_l1p5_lm_peer_get_e_rr_or_write_only_mib_attribute_uv m.log compliance_l1p5_lm_peer_set_e_rr_or_bad_index_uvm.log compliance_l1p5_lm_peer_set_e_rr_or_busy_uvm.log compliance_l1p5_lm_peer_set_e_rr_or_invalid_mib_attribute_uvm.lo g compliance_l1p5_lm_peer_set_e_rr_or_invalid_mib_attribute_value_ uvm.log compliance_l1p5_lm_peer_set_e_rr_or_locked_mib_attribute_uvm.lo g compliance_l1p5_lm_peer_set_e_rr_or_read_only_mib_attribute_uv m.log

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compliance_l1p5_lm_peer_get_bfm_uvm.log compliance_l1p5_lm_peer_get_dut_uvm.log compliance_l1p5_lm_peer_set_bfm_uvm.log compliance_l1p5_lm_peer_set_dut_uvm.log

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compliance_l1p5_pacp_req_ls_to_hs_n_to_ls_bfm_dut_uvm.log compliance_l1p5_pacp_req_ls_to_hs_n_to_ls_both_bfm_uvm.log compliance_l1p5_pacp_req_ls_to_hs_n_to_ls_both_dut_uvm.log compliance_l1p5_pacp_req_ls_to_hs_n_to_ls_dut_bfm_uvm.log

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compliance_l1p5_pacp_not_complete_uvm.log

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compliance_l1p5_data_trfr_FAST_AUTO_HS_G1_A_uvm.log compliance_l1p5_data_trfr_FAST_AUTO_HS_G1_B_quick_uvm.log compliance_l1p5_data_trfr_FAST_AUTO_HS_G1_B_uvm.log compliance_l1p5_data_trfr_FAST_AUTO_HS_G2_A_uvm.log compliance_l1p5_data_trfr_FAST_AUTO_HS_G2_B_uvm.log compliance_l1p5_data_trfr_FAST_HS_G1_B_quick_uvm.log compliance_l1p5_data_trfr_FAST_HS_G1_B_uvm.log compliance_l1p5_data_trfr_FAST_HS_G2_A_uvm.log compliance_l1p5_data_trfr_FAST_HS_G2_B_uvm.log compliance_l1p5_data_trfr_FAST_HS_G3_A_uvm.log compliance_l1p5_data_trfr_FAST_HS_G3_B_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G2_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G3_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G4_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G5_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G6_uvm.log compliance_l1p5_data_trfr_SLOW_AUTO_PWM_G7_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G2_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G3_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G4_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G5_quick_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G5_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G6_uvm.log compliance_l1p5_data_trfr_SLOW_PWM_G7_uvm.log compliance_l1p5_data_trfr_fast_HS_G1_A_uvm.log P0

compliance_l1p5_data_trfr_bfm_1_dut_1_uvm.log compliance_l1p5_data_trfr_bfm_1_dut_2_uvm.log compliance_l1p5_data_trfr_bfm_1_dut_3_uvm.log compliance_l1p5_data_trfr_bfm_1_dut_4_uvm.log compliance_l1p5_data_trfr_bfm_2_dut_1_uvm.log compliance_l1p5_data_trfr_bfm_2_dut_2_uvm.log compliance_l1p5_data_trfr_bfm_2_dut_3_uvm.log compliance_l1p5_data_trfr_bfm_2_dut_4_uvm.log compliance_l1p5_data_trfr_bfm_3_dut_1_uvm.log compliance_l1p5_data_trfr_bfm_3_dut_2_uvm.log compliance_l1p5_data_trfr_bfm_3_dut_3_uvm.log compliance_l1p5_data_trfr_bfm_3_dut_4_uvm.log compliance_l1p5_data_trfr_bfm_4_dut_1_uvm.log compliance_l1p5_data_trfr_bfm_4_dut_2_uvm.log compliance_l1p5_data_trfr_bfm_4_dut_3_uvm.log compliance_l1p5_data_trfr_bfm_4_dut_4_uvm.log compliance_l1p5_data_trfr_dut_1_connected_lane_uvm.log compliance_l1p5_data_trfr_dut_2_connected_lanes_uvm.log compliance_l1p5_data_trfr_dut_3_connected_lanes_uvm.log

P0 compliance_l1p5_not_changing_pwr_mode_bit_long_duration_of_tim e_uvm.log

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compliance_dut_pa_init_afcx_creq_set_during_initial_credit_exchang e_uvm.log compliance_dut_pa_init_nac_rrreq_set_uvm.log compliance_dut_pa_init_tcx_replay_uvm.log

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compliance_l1p5_hibern8_enter_from_bfm_exit_from_bfm_uvm.log compliance_l1p5_hibern8_enter_from_bfm_exit_from_dut_uvm.log compliance_l1p5_hibern8_enter_from_dut_exit_from_bfm_uvm.log compliance_l1p5_hibern8_enter_from_dut_exit_from_dut_uvm.log

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compliance_l1p5_pacp_crc_e_rr_or_pacp_cnf_to_dut_uvm.log compliance_l1p5_pacp_crc_e_rr_or_pacp_req_to_dut_uvm.log compliance_test_l1p5_pacp_epr_ind_crc_corruption_uvm.log compliance_test_l1p5_pacp_get_cnf_crc_corruption_uvm.log compliance_test_l1p5_pacp_get_req_crc_corruption_uvm.log compliance_test_l1p5_pacp_set_cnf_crc_corruption_uvm.log compliance_test_l1p5_pacp_set_req_crc_corruption_uvm.log rand_l1p5_pacp_crc_e_rr_or_pacp_pwr_req_to_dut_uvm.log

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compliance_corr_l1p5_pacp_escparam_uvm.log

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compliance_l1p5_init_pacp_cap_e_rr_or_uvm.log

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normal_l1p5_pacp_cap_ind_corrupt_uvm.log

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compliance_l1p5_pacp_get_cnf_corrupt_uvm.log compliance_l1p5_pacp_set_cnf_corrupt_uvm.log

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compliance_l1p5_pacp_pwr_cnf_pwr_busy_or_e_rr_or_cap_from_bf m_for_hib_req_uvm.log compliance_l1p5_pacp_pwr_cnf_pwr_busy_or_e_rr_or_cap_from_bf m_for_power_change_req_uvm.log

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compliance_pa_init_phase0_same_trg_upr0_on_more_than_one_lan e_and_recovery_uvm.log compliance_pa_init_phase0_trg_upr0_e_rr_and_recovery_uvm.log compliance_pa_init_phase0_trg_upr0_wrong_lane_num_and_recover y_uvm.log

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compliance_pa_init_phase0b_same_trg_upr0_on_more_than_one_la ne_and_recovery_uvm.log compliance_pa_init_phase0b_trg_upr0_e_rr_or_and_recovery_uvm.lo g compliance_pa_init_phase0b_trg_upr0_wrong_lane_no_and_recovery _uvm.log

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compliance_pa_init_phase1_trg_upr1_e_rr_or_and_abort_uvm.log

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compliance_pa_init_phase3_trg_upr2_e_rr_or_and_recovery_uvm.log

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compliance_pa_init_phase4_trg_upr2_e_rr_or_and_recovery_uvm.log

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compliance_l1p5_pwr_mode_invalid_uvm.log

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compliance_l1p5_pwr_mode_eob_timeout_for_hibernate_req_uvm.lo g compliance_l1p5_pwr_mode_eob_timeout_uvm.log

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compliance_l1p5_pwr_mode_with_user_data_uvm.log

P0 compliance_l1p5_random_symbols_before_sob_uvm.log

P0 rand_hibenate_entry_exit_uvm.log

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rand_mixed_pwr_mode_change_and_hibernate_entry_exit_req_quick _uvm.log rand_mixed_pwr_mode_change_and_hibernate_entry_exit_req_uvm. log rand_pwr_mode_change_req_quick_uvm.log rand_pwr_mode_change_req_uvm.log rand_pwr_mode_change_req_with_max_cap_quick_uvm.log rand_pwr_mode_change_req_with_max_cap_uvm.log

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compliance_l1p5_phy_test_mode_full_duplex_cjtpat_seq_uvm.log compliance_l1p5_phy_test_mode_full_duplex_crpat_seq_uvm.log compliance_l1p5_phy_test_mode_local_cjtpat_seq_uvm.log compliance_l1p5_phy_test_mode_local_crpat_seq_uvm.log compliance_l1p5_phy_test_mode_peer_cjtpat_seq_uvm.log compliance_l1p5_phy_test_mode_peer_crpat_seq_uvm.log

P0 compliance_l1p5_init_bfm_init_restart_PH_1_uvm.log compliance_l1p5_init_bfm_init_restart_PH_2_uvm.log compliance_l1p5_init_bfm_init_restart_PH_3_uvm.log compliance_l1p5_init_bfm_init_restart_PH_4_uvm.log

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compliance_l1p5_init_start_inject_symbol_e_rr_or_uvm.log compliance_pa_init_phase0_unexpected_phy_esc_symbol_and_recov ery_uvm.log compliance_pa_init_phase0b_unexpected_phy_esc_symbol_and_reco very_uvm.log compliance_pa_init_phase1_unexpected_phy_esc_symbol_and_recov ery_uvm.log compliance_pa_init_phase2_unexpected_phy_esc_symbol_and_recov ery_uvm.log compliance_pa_init_phase3_unexpected_phy_esc_symbol_and_recov ery_uvm.log compliance_pa_init_phase4_unexpected_phy_esc_symbol_and_recov ery_uvm.log

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compliance_bfm_pa_lm_linkstartup_req_prog_uvm.log

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compliance_dut_pa_lm_linkstartup_req_prog_uvm.log

P0 compliance_all_afc_with_nonzero_valid_credit_init_val_l2_uvm.log compliance_all_afc_with_zero_credit_init_val_l2_uvm.log compliance_tc0_afc_with_nonzero_valid_credit_init_val_l2_uvm.log compliance_tc0_afc_with_zero_credit_init_val_l2_uvm.log compliance_tc1_afc_with_nonzero_valid_credit_init_val_l2_uvm.log compliance_tc1_afc_with_zero_credit_init_val_l2_uvm.log

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compliance_basic_dut_rx_preemption_tc0_data_frame_by_nac_fram e_l4_uvm.log compliance_basic_dut_rx_preemption_tc0_data_frame_by_promoted _tc0_afc_frame_l4_uvm.log compliance_basic_dut_rx_preemption_tc0_data_frame_by_promoted _tc1_afc_frame_l4_uvm.log compliance_basic_dut_rx_preemption_tc0_data_frame_by_tc0_afc_fr ame_l4_uvm.log compliance_basic_dut_rx_preemption_tc0_data_frame_by_tc1_afc_fr ame_l4_uvm.log compliance_basic_dut_rx_preemption_tc0_data_frame_by_tc1_data_ frame_l4_uvm.log compliance_basic_dut_rx_preemption_tc1_data_frame_by_nac_fram e_l4_uvm.log compliance_basic_dut_rx_preemption_tc1_data_frame_by_promoted _tc0_afc_frame_l4_uvm.log compliance_basic_dut_rx_preemption_tc1_data_frame_by_promoted _tc1_afc_frame_l4_uvm.log compliance_basic_dut_rx_preemption_tc1_data_frame_by_tc1_afc_fr ame_l4_uvm.log compliance_basic_dut_tx_preemption_tc0_data_frame_by_nac_fram e_l4_uvm.log compliance_basic_dut_tx_preemption_tc0_data_frame_by_promoted _tc0_afc_frame_l4_uvm.log compliance_basic_dut_tx_preemption_tc0_data_frame_by_promoted _tc1_afc_frame_l4_uvm.log compliance_basic_dut_tx_preemption_tc0_data_frame_by_tc0_afc_fr compliance_cause_afcx_transmission_by_credit_diff_gt_threshold_l4_ uvm.log

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compliance_afc0_afc1_request_timer_l4_uvm.log compliance_afc0_request_timer_l4_uvm.log compliance_afc1_request_timer_l4_uvm.log

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compliance_multiple_time_fc0_protection_timer_timeout_l4_uvm.log compliance_multiple_time_fc1_protection_timer_timeout_l4_uvm.log compliance_single_time_fc0_protection_timer_timeout_l4_uvm.log compliance_single_time_fc1_fc0_protection_timer_timeout_l4_uvm.l og compliance_single_time_fc1_protection_timer_timeout_l4_uvm.log

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compliance_tc0_replay_timer_timeout_l4_uvm.log compliance_tc1_replay_timer_timeout_l4_uvm.log

P0 compliance_phy_init_failure_l2_uvm.log

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compliance_dut_rx_overflow_by_corrupting_tc0_sof_l4_uvm.log compliance_dut_rx_overflow_by_corrupting_tc1_sof_l4_uvm.log rand_dut_rx_overflow_with_ack_grouping_l4_uvm.log rand_dut_rx_overflow_wo_ack_grouping_l4_uvm.log

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compliance_replayed_low_priority_frame_pre_empted_by_non_repla yed_high_priority_frame_l4_uvm.log

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compliance_successive_e_rr_on_tc0_data_frames_single_nac_l4_uvm .log compliance_successive_e_rr_on_tc1_data_frames_single_nac_l4_uvm .log

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compliance_changing_bfm_link_prop_during_one_data_frame_in_pro gress_w_afcx_req_timer_running_l4_uvm.log compliance_changing_bfm_link_prop_during_one_data_frame_in_pro gress_w_no_afcx_req_timer_running_l4_uvm.log compliance_changing_dut_link_prop_during_one_data_frame_in_pro gress_w_afcx_req_timer_running_l4_uvm.log compliance_changing_dut_link_prop_during_one_data_frame_in_pro gress_w_no_afcx_req_timer_running_l4_uvm.log

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compliance_changing_bfm_link_prop_during_afc0_afc1_req_timers_r unning_l4_uvm.log compliance_changing_bfm_link_prop_during_afc0_req_timer_running _l4_uvm.log compliance_changing_bfm_link_prop_during_afc1_req_timer_running _l4_uvm.log compliance_changing_dut_link_prop_during_afc0_afc1_req_timers_r unning_l4_uvm.log compliance_changing_dut_link_prop_during_afc0_req_timer_running _l4_uvm.log compliance_changing_dut_link_prop_during_afc1_req_timer_running _l4_uvm.log

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compliance_changing_bfm_link_prop_during_preemption_in_progres s_w_afcx_req_timer_running_l4_uvm.log compliance_changing_bfm_link_prop_during_preemption_in_progres s_w_no_afcx_req_timer_running_l4_uvm.log compliance_changing_dut_link_prop_during_preemption_in_progress _w_afcx_req_timer_running_l4_uvm.log compliance_changing_dut_link_prop_during_preemption_in_progress _w_no_afcx_req_timer_running_l4_uvm.log

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compliance_changing_bfm_link_prop_during_no_pending_frames_l4_ uvm.log compliance_changing_dut_link_prop_during_no_pending_frames_l4_ uvm.log

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rand_drop_afc_rx_data_frame_with_ack_grouping_l4_uvm.log rand_drop_afc_rx_data_frame_wo_ack_grouping_l4_uvm.log

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compliance_duplicate_afc0_l4_uvm.log compliance_duplicate_afc1_l4_uvm.log rand_afc_frame_duplication_corrupt_with_ack_grouping_l4_quick_uv m.log rand_afc_frame_duplication_corrupt_with_ack_grouping_l4_uvm.log rand_afc_frame_duplication_corrupt_wo_ack_grouping_l4_uvm.log

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compliance_dut_tc0_ack_grouping_mechanism_l4_uvm.log compliance_dut_tc0_tc1_ack_grouping_mechanism_l4_uvm.log compliance_dut_tc1_ack_grouping_mechanism_l4_uvm.log

P0 compliance_fcx_protection_timer_timeout_init_l2_uvm.log

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compliance_illegal_preemption_nac_frame_by_nac_frame_l4_uvm.lo g compliance_illegal_preemption_nac_frame_by_tc0_afc_frame_l4_uv m.log compliance_illegal_preemption_nac_frame_by_tc0_data_frame_l4_uv m.log compliance_illegal_preemption_nac_frame_by_tc1_afc_frame_l4_uv m.log compliance_illegal_preemption_nac_frame_by_tc1_data_frame_l4_uv m.log compliance_illegal_preemption_tc0_afc_frame_by_nac_frame_l4_uv m.log compliance_illegal_preemption_tc0_afc_frame_by_tc0_afc_frame_l4_ uvm.log compliance_illegal_preemption_tc0_afc_frame_by_tc0_data_frame_l4 _uvm.log compliance_illegal_preemption_tc0_afc_frame_by_tc1_afc_frame_l4_ uvm.log compliance_illegal_preemption_tc0_afc_frame_by_tc1_data_frame_l4 _uvm.log compliance_illegal_preemption_tc0_data_frame_by_tc0_data_frame_ l4_uvm.log compliance_illegal_preemption_tc1_afc_frame_by_nac_frame_l4_uv m.log compliance_illegal_preemption_tc1_afc_frame_by_tc0_afc_frame_l4_ uvm.log compliance_illegal_preemption_tc1_afc_frame_by_tc0_data_frame_l4 compliance_multilevel_preemption_corrupt_tc0_cof_l4_uvm.log compliance_multilevel_preemption_corrupt_tc1_cof_l4_uvm.log

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rand_real_normal_frame_tx_rx_tc0_tc1_ack_grouping_l4_uvm.log

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rand_full_msg_normal_frame_tx_rx_tc0_ack_grouping_l4_uvm.log rand_full_msg_normal_frame_tx_rx_tc1_ack_grouping_l4_uvm.log

P0 rand_basic_normal_msg_rx_tc0_tc1_uvm.log rand_basic_normal_msg_rx_tc0_uvm.log rand_basic_normal_msg_rx_tc1_uvm.log

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rand_basic_normal_msg_tx_rx_tc0_tc1_with_preemption_wo_ack_gr ouping_uvm.log rand_basic_normal_msg_tx_rx_tc0_tc1_wo_preemption_wo_ack_gro uping_uvm.log rand_basic_normal_msg_tx_rx_tc0_with_preemption_wo_ack_groupi ng_uvm.log rand_basic_normal_msg_tx_rx_tc0_wo_preemption_wo_ack_groupin g_uvm.log rand_basic_normal_msg_tx_rx_tc1_with_preemption_wo_ack_groupi ng_uvm.log rand_basic_normal_msg_tx_rx_tc1_wo_preemption_wo_ack_groupin g_uvm.log

P0 rand_basic_normal_msg_tx_tc0_tc1_uvm.log rand_basic_normal_msg_tx_tc0_uvm.log rand_basic_normal_msg_tx_tc1_uvm.log

P0 rand_e_r_r_injection_at_l2_layer_with_ack_grouping_l4_uvm.log rand_e_r_r_injection_at_l2_layer_wo_ack_grouping_l4_uvm.log

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compliance_afc0_frame_corrupt_rsvd_bits_l4_uvm.log compliance_afc1_frame_corrupt_rsvd_bits_l4_uvm.log rand_afc_frame_corrupt_rsvd_bits_with_ack_grouping_l4_uvm.log rand_afc_frame_corrupt_rsvd_bits_wo_ack_grouping_l4_uvm.log

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compliance_afc0_data_frame_rtx_in_progress_l4_uvm.log compliance_afc1_data_frame_rtx_in_progress_l4_uvm.log

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compliance_tx_cof_cs_before_tc0_data_frame_started_l4_uvm.log compliance_tx_cof_cs_before_tc1_data_frame_started_l4_uvm.log compliance_tx_eof_even_cs_before_tc0_data_frame_started_l4_uvm. log compliance_tx_eof_even_cs_before_tc1_data_frame_started_l4_uvm. log compliance_tx_eof_odd_cs_before_tc0_data_frame_started_l4_uvm.l og compliance_tx_eof_odd_cs_before_tc1_data_frame_started_l4_uvm.l og rand_tx_cof_cs_before_data_frame_started_with_ack_grouping_l4_u vm.log rand_tx_cof_cs_before_data_frame_started_wo_ack_grouping_l4_qui ck_uvm.log rand_tx_cof_cs_before_data_frame_started_wo_ack_grouping_l4_uv m.log rand_tx_eof_even_cs_before_data_frame_started_with_ack_grouping _l4_uvm.log rand_tx_eof_even_cs_before_data_frame_started_wo_ack_grouping_ l4_uvm.log rand_tx_eof_odd_cs_before_data_frame_started_with_ack_grouping _l4_uvm.log rand_tx_eof_odd_cs_before_data_frame_started_wo_ack_grouping_l 4_uvm.log P0

compliance_cof_of_tc0_data_frame_continue_diff_tc_l4_uvm.log compliance_cof_of_tc1_data_frame_continue_diff_tc_l4_uvm.log rand_cof_continue_diff_tc_with_ack_grouping_l4_uvm.log rand_cof_continue_diff_tc_wo_ack_grouping_l4_uvm.log

P0

compliance_cof_wo_pre_emption_on_tc0_data_frame_l4_uvm.log compliance_cof_wo_pre_emption_on_tc1_data_frame_l4_uvm.log rand_cof_wo_pre_emption_with_ack_grouping_l4_uvm.log rand_cof_wo_pre_emption_wo_ack_grouping_l4_uvm.log

P0

compliance_afc0_crc_corrupt_l4_uvm.log compliance_afc1_crc_corrupt_l4_uvm.log compliance_nac_crc_corrupt_l4_uvm.log rand_ctrl_afc_frame_crc_corrupt_with_ack_grouping_l4_uvm.log rand_ctrl_afc_frame_crc_corrupt_wo_ack_grouping_l4_uvm.log rand_ctrl_nac_frame_crc_corrupt_with_ack_grouping_l4_uvm.log rand_ctrl_nac_frame_crc_corrupt_wo_ack_grouping_l4_uvm.log

P0

compliance_l2_afc_ctrl_sym_identifier_corrupt_l4_uvm.log compliance_l2_cof_ctrl_sym_identifier_corrupt_l4_uvm.log compliance_l2_eof_even_ctrl_sym_identifier_corrupt_l4_uvm.log compliance_l2_eof_odd_ctrl_sym_identifier_corrupt_l4_uvm.log compliance_l2_nac_ctrl_sym_identifier_corrupt_l4_uvm.log compliance_l2_sof_ctrl_sym_identifier_corrupt_l4_uvm.log rand_l2_afc_ctrl_sym_identifier_corrupt_with_ack_grouping_l4_uvm.l og rand_l2_afc_ctrl_sym_identifier_corrupt_wo_ack_grouping_l4_uvm.lo g rand_l2_cof_ctrl_sym_identifier_corrupt_with_ack_grouping_l4_uvm.l og rand_l2_cof_ctrl_sym_identifier_corrupt_wo_ack_grouping_l4_uvm.lo g rand_l2_eof_even_ctrl_sym_identifier_corrupt_with_ack_grouping_l4 _uvm.log rand_l2_eof_even_ctrl_sym_identifier_corrupt_wo_ack_grouping_l4_ uvm.log rand_l2_eof_odd_ctrl_sym_identifier_corrupt_with_ack_grouping_l4_ uvm.log rand_l2_eof_odd_ctrl_sym_identifier_corrupt_wo_ack_grouping_l4_u vm.log rand_l2_nac_ctrl_sym_identifier_corrupt_with_ack_grouping_l4_uvm. log rand_l2_nac_ctrl_sym_identifier_corrupt_wo_ack_grouping_l4_uvm.l og rand_l2_sof_ctrl_sym_identifier_corrupt_with_ack_grouping_l4_uvm.l

P0

compliance_afc_tc0_corrupt_to_rsvd_tcx_l4_uvm.log compliance_afc_tc1_corrupt_to_rsvd_tcx_l4_uvm.log compliance_cof_tc0_corrupt_to_rsvd_tcx_l4_uvm.log compliance_cof_tc1_corrupt_to_rsvd_tcx_l4_uvm.log compliance_sof_tc0_corrupt_to_rsvd_tcx_l4_uvm.log compliance_sof_tc1_corrupt_to_rsvd_tcx_l4_uvm.log rand_afc_tc_corrupt_to_rsvd_tcx_with_ack_grouping_l4_uvm.log rand_afc_tc_corrupt_to_rsvd_tcx_wo_ack_grouping_l4_uvm.log rand_cof_tc_corrupt_to_rsvd_tcx_with_ack_grouping_l4_uvm.log rand_cof_tc_corrupt_to_rsvd_tcx_wo_ack_grouping_l4_uvm.log rand_sof_tc_corrupt_to_rsvd_tcx_with_ack_grouping_l4_uvm.log rand_sof_tc_corrupt_to_rsvd_tcx_wo_ack_grouping_l4_uvm.log

P0

compliance_afc0_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log compliance_afc1_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log compliance_tc0_cof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log compliance_tc0_eof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log compliance_tc0_sof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log compliance_tc1_cof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log compliance_tc1_eof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log compliance_tc1_sof_corrupt_to_rsvd_ctrl_sym_type_l4_uvm.log rand_afc_corrupt_to_rsvd_ctrl_sym_type_with_ack_grouping_l4_uvm .log rand_afc_corrupt_to_rsvd_ctrl_sym_type_wo_ack_grouping_l4_uvm.l og rand_cof_corrupt_to_rsvd_ctrl_sym_type_with_ack_grouping_l4_quic k_uvm.log rand_cof_corrupt_to_rsvd_ctrl_sym_type_with_ack_grouping_l4_uvm .log rand_cof_corrupt_to_rsvd_ctrl_sym_type_wo_ack_grouping_l4_uvm.l og rand_eof_corrupt_to_rsvd_ctrl_sym_type_with_ack_grouping_l4_uvm .log rand_eof_corrupt_to_rsvd_ctrl_sym_type_wo_ack_grouping_l4_uvm.l og rand_sof_corrupt_to_rsvd_ctrl_sym_type_with_ack_grouping_l4_uvm .log rand_sof_corrupt_to_rsvd_ctrl_sym_type_wo_ack_grouping_l4_quick _uvm.log rand_sof_corrupt_to_rsvd_ctrl_sym_type_wo_ack_grouping_l4_uvm.l

P0

compliance_tc0_cof_ctrl_sym_corrupt_rsvd_bits_l4_uvm.log compliance_tc0_data_frame_corrupt_rsvd_bits_l4_uvm.log compliance_tc1_cof_ctrl_sym_corrupt_rsvd_bits_l4_uvm.log compliance_tc1_data_frame_corrupt_rsvd_bits_l4_uvm.log rand_cof_ctrl_sym_corrupt_rsvd_bits_with_ack_grouping_l4_uvm.log rand_cof_ctrl_sym_corrupt_rsvd_bits_wo_ack_grouping_l4_uvm.log rand_data_frame_corrupt_rsvd_bits_with_ack_grouping_l4_uvm.log rand_data_frame_corrupt_rsvd_bits_wo_ack_grouping_l4_uvm.log

P0

compliance_tc0_data_frame_payload_corrupt_gt_dl_mtu_l4_uvm.log compliance_tc1_data_frame_payload_corrupt_gt_dl_mtu_l4_uvm.log rand_data_frame_payload_corrupt_gt_dl_mtu_with_ack_grouping_l4 _uvm.log rand_data_frame_payload_corrupt_gt_dl_mtu_wo_ack_grouping_l4_ uvm.log

P0

compliance_tc0_data_frame_crc_corrupt_l4_uvm.log compliance_tc1_data_frame_crc_corrupt_l4_uvm.log rand_data_frame_crc_corrupt_with_ack_grouping_l4_quick_uvm.log rand_data_frame_crc_corrupt_with_ack_grouping_l4_uvm.log rand_data_frame_crc_corrupt_wo_ack_grouping_l4_quick_uvm.log rand_data_frame_crc_corrupt_wo_ack_grouping_l4_uvm.log

P0

compliance_tc0_data_frame_fsn_corrupt_to_prev_acked_l4_uvm.log compliance_tc1_data_frame_fsn_corrupt_to_prev_acked_l4_uvm.log rand_data_frame_fsn_corrupt_to_prev_acked_with_ack_grouping_l4_ uvm.log rand_data_frame_fsn_corrupt_to_prev_acked_wo_ack_grouping_l4_u vm.log

P0

compliance_tc0_data_frame_fsn_corrupt_l4_uvm.log compliance_tc1_data_frame_fsn_corrupt_l4_uvm.log rand_data_frame_fsn_corrupt_with_ack_grouping_l4_uvm.log rand_data_frame_fsn_corrupt_wo_ack_grouping_l4_quick_uvm.log rand_data_frame_fsn_corrupt_wo_ack_grouping_l4_uvm.log

P0

compliance_cof_droped_of_resumed_tc0_data_frame_l4_uvm.log compliance_cof_droped_of_resumed_tc1_data_frame_l4_uvm.log rand_cof_droped_of_resumed_frame_with_ack_grouping_l4_uvm.log rand_cof_droped_of_resumed_frame_wo_ack_grouping_l4_uvm.log

P0

compliance_tx_incomplete_tc0_data_frame_wo_crc_l4_uvm.log compliance_tx_incomplete_tc1_data_frame_wo_crc_l4_uvm.log rand_tx_incomplete_data_frame_wo_crc_with_ack_grouping_l4_uvm. log rand_tx_incomplete_data_frame_wo_crc_wo_ack_grouping_l4_uvm.l og rand_tx_incomplete_tc1_data_frame_wo_crc_with_ack_grouping_l4_ uvm.log rand_tx_incomplete_tc1_data_frame_wo_crc_wo_ack_grouping_l4_u vm.log

P0

compliance_tx_incomplete_afc0_l4_uvm.log compliance_tx_incomplete_afc1_l4_uvm.log rand_tx_incomplete_afc_frame_with_ack_grouping_l4_uvm.log rand_tx_incomplete_afc_frame_wo_ack_grouping_l4_uvm.log

P0

compliance_tx_incomplete_nac_w_tc0_traffic_l4_uvm.log compliance_tx_incomplete_nac_w_tc1_traffic_l4_uvm.log

P0

compliance_tx_nac_no_outstanding_tc0_data_frame_rem_to_acked_l 4_uvm.log compliance_tx_nac_no_outstanding_tc1_data_frame_rem_to_acked_l 4_uvm.log

P0

compliance_tx_nac_outstanding_tc0_data_frame_rem_to_acked_l4_u vm.log compliance_tx_nac_outstanding_tc1_data_frame_rem_to_acked_l4_u vm.log

P0

compliance_tx_nac_in_tc0_ntx_rtx_in_progress_l4_uvm.log compliance_tx_nac_in_tc1_ntx_rtx_in_progress_l4_uvm.log rand_randomly_nac_transmission_with_ack_grouping_l4_uvm.log rand_randomly_nac_transmission_wo_ack_grouping_l4_uvm.log

P0

compliance_nac_frame_corrupt_rsvd_bits_l4_uvm.log

P0

compliance_sof_instead_of_cof_of_resumed_tc0_data_frame_l4_uvm .log compliance_sof_instead_of_cof_of_resumed_tc1_data_frame_l4_uvm .log rand_sof_instead_of_cof_of_resumed_data_frame_w_ack_grouping_l 4_uvm.log rand_sof_instead_of_cof_of_resumed_data_frame_wo_ack_grouping _l4_uvm.log

P0

compliance_pre_emption_bet_same_priority_tx_tc0_data_frame_l4_ uvm.log compliance_pre_emption_bet_same_priority_tx_tc1_data_frame_l4_ uvm.log rand_pre_emption_bet_same_priority_tx_data_frame_with_ack_grou ping_l4_uvm.log rand_pre_emption_bet_same_priority_tx_data_frame_wo_ack_groupi ng_l4_uvm.log

P0

compliance_lower_priority_frame_pre_empting_higher_priority_fram e_l4_uvm.log rand_lower_priority_frame_pre_empting_higher_priority_frame_with _ack_grouping_l4_uvm.log rand_lower_priority_frame_pre_empting_higher_priority_frame_wo_ ack_grouping_l4_uvm.log

P0 compliance_dut_rx_tc0_data_frame_w_size_of_non_multiple_32byte s_l4_uvm.log compliance_dut_rx_tc0_tc1_data_frame_w_size_of_non_multiple_32 bytes_l4_uvm.log compliance_dut_rx_tc1_data_frame_w_size_of_non_multiple_32byte s_l4_uvm.log compliance_dut_tx_tc0_data_frame_w_size_of_non_multiple_32byte s_l4_uvm.log compliance_dut_tx_tc0_tc1_data_frame_w_size_of_non_multiple_32 bytes_l4_uvm.log compliance_dut_tx_tc1_data_frame_w_size_of_non_multiple_32byte s_l4_uvm.log P0

compliance_tx_afc0_w_creq_set_l4_uvm.log compliance_tx_afc1_w_creq_set_l4_uvm.log rand_tx_afc_w_creq_set_with_ack_grouping_l4_uvm.log rand_tx_afc_w_creq_set_wo_ack_grouping_l4_uvm.log

P0

compliance_unexpected_framing_on_tc0_frame_l4_uvm.log compliance_unexpected_framing_on_tc1_frame_l4_uvm.log rand_unexpected_framing_w_group_ack_l4_uvm.log rand_unexpected_framing_wo_group_ack_l4_uvm.log

P0

compliance_pre_empt_replay_tc0_data_frame_no_nac_l4_uvm.log compliance_pre_empt_replay_tc1_data_frame_no_nac_l4_uvm.log

P0

rand_tc1_credit_blocked_and_tc0_making_progress_l4_uvm.log

P0 rand_tc1_fsn_blocked_and_tc0_making_progress_l4_uvm.log

P0

rand_long_pkt_tx_rx_tc0_l3_uvm.log rand_long_pkt_tx_rx_tc1_l3_uvm.log

P0 rand_long_pkt_tx_rx_tcx_l3_uvm.log

P0 rand_long_tc0_short_mix_tcx_with_user_device_id48_l3_uvm.log rand_long_tc0_short_mix_tcx_with_user_device_id84_l3_uvm.log rand_long_tc1_short_mix_tcx_with_user_device_id_max_l3_uvm.log rand_long_tcx_short_mix_tcx_with_user_device_id_min_l3_uvm.log

P0 rand_long_short_mix_tc0_l3_uvm.log rand_long_short_mix_tcx_l3_uvm.log

P0 compliance_dut_long_header_drop_l3_uvm.log

P0

compliance_tx_corr_deviceid_enc_id_true_l3_uvm.log rand_test_pkt_specific_e_rr_percentage_case_deviceid_enc_uvm.log

P0 compliance_msg_on_disconnected_cport_l4_uvm.log

P0 normal_message_tx_CportStatus_NoPeerTc_uvm.log

P0

normal_fc_tx_in_contious_cycles_uvm.log

P0 rand_normal_segment_tx_rx_tc0_e2efc0_l4_uvm.log

P0

rand_normal_segment_tx_rx_tc0_e2efc0_csv_n0_l4_uvm.log

P0

rand_normal_message_tx_rx_rand_l4_uvm.log rand_normal_message_with_fct_tx_rx_tc0_l4_uvm.log

P0

compliance_normal_single_message_single_sequence_tx_rx_tc0_l4_u vm.log

P0

compliance_tx_seg_DestCportId_0_l4_uvm.log

P0

compliance_tx_seg_corr_tc_l4_uvm.log

P0

compliance_zero_seg_eom1_l4_uvm.log compliance_zero_seg_tc1_eom1_l4_uvm.log

P0

compliance_normal_segment_tx_rx_cport_gt_31_l4_uvm.log

P0

compliance_fct_updates_e2efc0_l4_uvm.log

P0

compliance_tx_seg_l4s_0_l4_uvm.log

P0

compliance_tx_seg_incorr_connectstate_l4_uvm.log

P0

compliance_zero_seg_eom_false_l4_uvm.log

P0

rand_normal_message_tx_rx_tc0_l4_uvm.log rand_normal_message_tx_rx_tc1_latency_e2efc0_l4_uvm.log rand_normal_message_tx_rx_tc1_latency_e2efc1_l4_uvm.log

P0

rand_normal_message_tx_rx_tc0_e2efc1_csv_n0_l4_uvm.log

P0

rand_normal_message_tx_tc0_l4_uvm.log

P0

rand_normal_message_rx_tc0_l4_uvm.log

P0

compliance_tx_seg_gt_tmtu_l4_uvm.log

P0 compliance_tx_seg_less_tmtu_eom0_l4_uvm.log

P0

rand_test_seg_DestCportId_e_rr_inj_e2efc0_uvm.log rand_test_seg_DestCportId_e_rr_inj_e2efc1_uvm.log

P0

rand_test_seg_TC_e_rr_inj_e2efc0_uvm.log rand_test_seg_TC_e_rr_inj_e2efc1_uvm.log

P0

rand_test_EOM_e_rr_inj_e2efc0_uvm.log rand_test_EOM_e_rr_inj_e2efc1_uvm.log

P0

rand_test_FCT_e_rr_inj_e2efc0_uvm.log

P0

rand_test_HDR_e_rr_inj_e2efc0_uvm.log rand_test_HDR_e_rr_inj_e2efc1_uvm.log

P0

rand_test_seg_payload_size_e_rr_inj_e2efc0_uvm.log rand_test_seg_payload_size_e_rr_inj_e2efc1_uvm.log

P0

rand_test_seg_specific_e_rr_percentage_case_e2efc0_uvm.log

P0

rand_test_seg_layer_percentage_e_rr_case_e2efc1_uvm.log rand_test_seg_specific_and_layer_percentage_e_rr_case_e2efc1_uvm .log

P0

rand_test_seg_specific_e_rr_percentage_case_e2efc1_uvm.log

P0

rand_test_Rx_BUFFER_OVERFLOW_e_rr_inj_e2efc1_uvm.log

P0 compliance_dut_csv0_e2efc0_csd0_seg_drop_l4_uvm.log compliance_dut_csv_e2efc1_seg_drop_l4_uvm.log

P0

compliance_dut_csd_e2efc0_l4_Rx_buffer_grt0_uvm.log

P0

compliance_dut_rx_overflow_e2efc1_credit_grt0_uvm.log

P0

compliance_dut_rx_overflow_e2efc1_l4_credit0_uvm.log

P0

compliance_dut_csd_e2efc0_l4_rx_buffer0_uvm.log

P0 compliance_testmode_e_rr_or_inj_uvm.log

P0

compliance_testmode_dut_tstsrc_full_duplex_l4_uvm.log

P0

compliance_testmode_dut_tstsrc_half_duplex_txbfm_l4_uvm.log

P0

compliance_testmode_dut_tstsrc_half_duplex_txdut_l4_uvm.log

P0

compliance_retained_attr_restore_after_hibern8_uvm.log

P0 compliance_unipro_basic_attribute_write_read_test_dme_mode_uv m.log compliance_unipro_basic_attribute_write_read_test_reg_mode_uvm.l og P0

compliance_lm_set_get_read_write_chk_uvm.log compliance_lm_set_get_reset_values_chk_uvm.log

P0 compliance_normal_l1p5_lm_set_get_err_uvm.log

P0

compliance_cport_connect_sequence_dme_uvm.log

P0 compliance_dut_init_sequence_dme_uvm.log

P0

STATUS

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PRIOIRITY

(All)

Count of STATUS Column Labels Row Labels NYET DME L1P5 L2 L3 L4 Grand Total

9 217 287 14 92 619

Grand Total 9 217 287 14 92 619

Testplan is organized hierarchially as :

[1] UniPro Layers [2] Multiple sections within each layer [3] Multiple tests within each section [4] Multiple command lines within each test

Two different views of the test plan are provided in worksh using the command line LOGNAME column.

Worksheet
TestPlan_CmdLines TestPlan_Tests

VerificationScore

ganized hierarchially as :

s ions within each layer s within each section mmand lines within each test

ews of the test plan are provided in worksheets described below. They can be co-related and line LOGNAME column.

Description
Every row of this sheet contains a unique command line. Command line is a unique variation of the test. Every row of this sheet contains a unique test. A test can have multiple variations as different command lines. Pivot table for the TestPlan_CmdLines sheet contents. Summarizes the VerificationScore after the STATUS column in the TestPlan_CmdLines is updated.