Serra, M., Dervisoglu, B.I.

Testing
The Electrical Engineering Handbook
Ed. Richard C. Dorf
Boca Raton: CRC Press LLC, 2000
2000 by CRC Press LLC
S5
TesfIng
85.1 Digital IC Testing
Taxonomy of Testing Fault Models Test Pattein Geneiation
Output Response Analysis
85.2 Design foi Test
The Testability Pioblem Design foi Testability Futuie foi Design
foi Test
85.1 Digita! IC Testing
Mcoe|o Serro
In this section we give an oveiview of digital testing techniques with appiopiiate iefeience to mateiial containing
all details of the methodology and algoiithms. Fiist, we piesent a geneial intioduction of teiminology and a
taxonomy of testing methods. Next, we piesent a defnition of fault models, and fnally we discuss the main
appioaches foi test pattein geneiation and data compaction, iespectively.
Taxunumy ul Testing
The evaluation of the ieliability and quality of a digital IC is commonly called esng, yet it compiises distinct
phases that aie mostly kept sepaiate both in the ieseaich community and in industiial piactice.
1. Verftaon is the initial phase in which the fist piototype chips aie tested" to ensuie that they match
theii functional specifcation, that is, to veiify the coiiectness of the design. Veiifcation checks that all
design iules aie adheied to, fiom layout to electiical paiameteis; moie geneially, this type of functional
testing checks that the ciicuit: (a) implements what it is supposed to do anJ (b) does not do what it is
not supposed to do. Both conditions aie necessaiy. This type of evaluation is done at the design stage
and uses a vaiiety of techniques, including logic veiifcation with the use of haidwaie desciiption
languages, full functional simulation, and geneiation of functional test vectois. We do not discuss
veiifcation techniques heie.
2. Tesng coiiectly iefeis to the phase when one must ensuie that only defect-fiee pioduction chips aie
packaged and shipped and detect faults aiising fiom manufactuiing and/oi weai-out. Testing methods
must (a) be fast enough to be applied to laige amounts of chips duiing pioduction, (b) take into
consideiation whethei the industiy conceined has access to laige expensive exteinal testei machines,
and (c) considei whethei the implementation of built-in self-test (BIST) pioves to be advantageous. In
BIST, the ciicuit is designed to include its own self-testing extia ciicuitiy and thus can signal diiectly,
duiing testing, its possible failuie status. Of couise, this involves a ceitain amount of oveihead in aiea,
and tiade-offs must be consideied. The development of appiopiiate testing algoiithms and theii tool
suppoit can iequiie a laige amount of engineeiing effoit, but one must note that it may need to be done
only once pei design. The speed of application of the algoiithm (applied to many copies of the chips)
can be of moie impoitance.
NIcaeIa Serra
Inverry of Vcroro
BuIenf I. IervIsogIu
Hev|errPoc|ord Comony
2000 by CRC Press LLC
3. Paramert esng is done to ensuie that components meet design specifcation foi delays, voltages, powei,
etc. Lately much attention has been given to 1
DDq
testing, a paiametiic technique foi CMOS testing. I
DDq
testing monitois the cuiient I
DD
that a ciicuit diaws when it is in a quiescent state. It is used to detect
faults such as biidging faults, tiansistoi stuck-open faults, oi gate oxide leaks, which inciease the noimally
low I
DD
Jacomino et al., 1989].
The density of ciicuitiy continues to inciease, while the numbei of I/O pins iemains small. This causes a
seiious escalation of complexity, and testing is becoming one of the majoi costs to industiy (estimated up to
30%). ICs should be tested befoie and aftei packaging, aftei mounting on a boaid, and peiiodically duiing
opeiation. Diffeient methods may be necessaiy foi each case. Thus by testing we imply the means by which
some qualities oi attiibutes aie deteimined to be fault-fiee oi faulty. The main puipose of testing is the detection
of malfunctions (Go/NoGo test), and only subsequently one may be inteiested in the actual location of the
malfunction; this is called [au| Jagnoss oi [au| |otaon.
Most testing techniques aie designed to be applied to combinational ciicuits only. While this may appeai a
stiong iestiiction, in piactice it is a iealistic assumption based on the idea of designing a sequential ciicuit by
paititioning the memoiy elements fiom the contiol functionality such that the ciicuit can be ieconfguied as
combinational at testing time. This geneial appioach is one of the methods in Jesgn [or esa||y (DFT) (see
Section 85.2). DFT encompasses any design stiategy aimed at enhancing the testability of a ciicuit. In paiticulai,
scan design is the best-known implementation foi sepaiating the latches fiom the combinational gates such
that some of the latches can also be ieconfguied and used as eithei testei units oi as input geneiatoi units
(essential foi built-in testing).
Figuie 85.1(a) shows the geneial division foi algoiithms in testing. Tes aern generaon implies a faii
amount of woik in geneiating an appiopiiate subset of all input combinations, such that a desiied peicentage
of faults is activated and obseived at the outputs. Ouu resonse ana|yss encompasses methods which captuie
only the output stieam, with appiopiiate tiansfoimations, with the assumption that the ciicuit is stimulated
by eithei an exhaustive oi a iandom set of input combinations. Both methodologies aie intioduced below.
Moieovei a fuithei division can be seen between on-|ne and o[[-|ne methods see Fig. 85.1(b)]. In the foimei,
each output woid fiom the ciicuit is tested duiing noimal opeiation. In the lattei, the ciicuit must suspend
noimal opeiation and entei a test mode," at which time the appiopiiate method of testing is applied. While
off-line testing can be executed eithei thiough exteinal testing (a testei machine exteinal to the ciicuitiy) oi
thiough the use of BIST, on-line testing (also called tonturren t|et|ng) usually implies that the ciicuit contains
some coding scheme which has been pieviously embedded in the design of the ciicuitiy.
If many defects aie piesent duiing the manufactuiing piocess, the manufactuiing yield is loweied, and testing
becomes of paiamount impoitance. Some estimation can be given about the ielationship between manufac-
tuiing yield, effectiveness of testing and defect level iemaining aftei test Williams, 1986]. Let Y denote the
yield, wheie Y is some value between 1 (100% defect-fiee pioduction) and 0 (all ciicuits faulty aftei testing).
FIGURE 85.1 Taxonomy of testing methods. (a) Test pattein geneiation; (b) on-line and off-line methods.
2000 by CRC Press LLC
Let FC be the fault coverage, calculated as the peicentage of detected faults ovei the total numbei of detectable
modeled faults (see below foi fault models). The value of FC ianges fiom 1 (all possible faults detected) to 0
(no testing done). We aie inteiested in the fnal defect level (DL), aftei test, defned as the piobability of shipping
a defective pioduct. It has been shown that tests with high fault coveiage (foi ceitain fault models, see below)
also have high defect coveiage. The empiiical equation is
DL (1 - Y
1F C
) 100%
Plotting this equation gives inteiesting and piactical iesults. Table 85.1 shows only a
few examples of some piactical values of Y and FC. The main conclusion to be diawn
is that a veiy high fault coveiage must be achieved to obtain any acceptable defect
level value, and manufactuiing yield must be continually impioved to maintain ieli-
ability of shipped pioducts.
Fau!t Mude!s
At the defect level, an enoimous numbei of diffeient failuies could be piesent, and it is totally infeasible to
analyze them as such. Thus failuies aie giouped togethei with iegaids to theii logical fault effect on the
functionality of the ciicuit, and this leads to the constiuction of logical fault models as the basis foi testing
algoiithms Abiamovici et al., 1992]. Moie piecisely, a [au| denotes the physical failuie mechanism, the [au|
e[[et denotes the logical effect of a fault on a signal-caiiying net, and an error is defned as the condition (oi
state) of a system containing a fault (deviation fiom coiiect state). Faults can be fuithei divided into classes,
as shown in Fig. 85.2. Heie we discuss only ermanen faults, that is, faults in existence long enough to be
obseived at test time, as opposed to emorary faults (tiansient oi inteimittent), which appeai and disappeai
in shoit inteivals of time, oi Je|ay faults, which affect the opeiating speed of the ciicuit. Moieovei we do not
discuss sequential faults, which cause a combinational ciicuit to behave like a sequential one, as they aie mainly
iestiicted to ceitain technologies (e.g., CMOS).
The most commonly used fault model is that of a stuck-at fault, which is modeled by having a line segment
stuck at logic 0 oi 1 (stuck-at 1 oi stuck-at 0). One may considei single oi multiple stuck-at faults and Fig. 85.3
shows an example foi a simple ciicuit. The fault-fiee function is shown as F, while the faulty functions, undei
FIGURE 85.2 Fault chaiacteiistics.
FIGURE 85.3 Single stuck-at fault example.
TABLE 85.1 Examples
of Defect Levels
Y FC DL
0.15 0.90 0.18
0.25 0.00 0.75
0.25 0.90 0.15
2000 by CRC Press LLC
the occuiience of the single stuck-at faults of eithei line 1 stuck-at 0 (1/0) oi of line 2 stuck-at 1 (2/1), aie
shown as F*.
BrJgng [au|s occui when two oi moie lines aie shoited togethei. Theie aie two main pioblems in the
analysis of biidging faults: (1) the theoietical numbei of possible such faults is extiemely high and (2) the
opeiational effect is of a wiied logic AND oi OR, depending on technology, and it can even have diffeient
effects in complex CMOS gates.
CMOS sut|-oen faults have been examined iecently, as they cannot be modeled fiom the moie classical
fault models and aie iestiicted to the CMOS technology. They occui when the path thiough one of the -channel
oi one of the n-channel tiansistois becomes an open ciicuit. The main diffculty in detecting this type of fault
is that it changes the combinational behavioi of a cell into a sequential one. Thus the logical effect is to ietain,
on a given line, the pievious value, intioducing a memoiy state. To detect such a fault, one must apply two
stimuli: the fist to set a line at a ceitain value and the second to tiy and change that value. This, of couise,
incieases the complexity of fault detection.
Test Pattern Generatiun
Test pattern geneiation is the piocess of geneiating a (minimal) set of input patteins to stimulate the inputs
of a ciicuit such that detectable faults can be exeicised (if piesent) Abiamovici et al., 1992]. The piocess can
be divided in two distinct phases: (1) deiivation of a test and (2) application of a test. Foi (1), one must fist
select appiopiiate models foi the ciicuit (gate oi tiansistoi level) and foi faults; one must constiuct the test
such that the output signal fiom a faulty ciicuit is diffeient fiom that of a good ciicuit. This can be computa-
tionally veiy expensive, but one must iemembei that the piocess is done only once at the end of the design
stage. The geneiation of a test set can be obtained eithei by manual methods, by algoiithmic methods (with
oi without heuiistics), oi by pseudo-iandom methods. On the othei hand, foi (2), a test is subsequently applied
many times to each IC and thus must be effcient both in space (stoiage iequiiements foi the patteins) and in
time. Often such a set is not minimal, as neai minimality may be suffcient. The main consideiations in
evaluating a test set aie the time to constiuct a minimal test set; the size of the test pattein geneiatoi, i.e., the
softwaie oi haidwaie module used to stimulate the ciicuit undei test; the size of the test set itself; the time to
load the test patteins; and the equipment iequiied (if exteinal) oi the BIST oveihead.
Most algoiithmic test pattein geneiatois aie based on the concept of sensitized paths. Given a line in a ciicuit,
one wants to fnd a sens:eJ path to take a possible eiioi all the way to an obseivable output. Foi example,
to sensitize a path that goes thiough one input of an AND gate, one must set all othei inputs of the gate to
logic 1 to peimit the sensitized signal to caiiy thiough. Figuie 85.4 summaiizes the undeilying piinciples of
tiying to constiuct a test set. Each column shows the expected output foi each input combination of a NAND
gate. Columns 3 to 8 show the output undei the piesence of a stuck-at fault as pei label. The output bits that
peimit detection of the coiiesponding fault aie shown in a squaie, and thus at the bottom the minimal test
set is listed, compiising the minimal numbei of distinct patteins necessaiy to detect all single stuck-at faults.
FIGURE 85.4 Test set example.
2000 by CRC Press LLC
The best-known algoiithms aie the D-algoiithm (piecuisoi to all), PODEM, and FAN Abiamovici, 1992].
Thiee steps can be identifed in most automatic test pattein geneiation (ATPG) piogiams: (1) listing the signals
on the inputs of a gate contiolling the line on which a fault should be detected, (2) deteimining the piimaiy
input conditions necessaiy to obtain these signals (back piopagation) and sensitizing the path to the piimaiy
outputs such that the signals and fault can be obseived, and (3) iepeating this pioceduie until all detectable
faults in a given fault set have been coveied. PODEM and FAN intioduce poweiful heuiistics to speed the thiee
steps by aiding in the sequential selection of faults to be examined and by cutting the amount of back and
foiwaid piopagation necessaiy.
Notwithstanding heuiistics, algoiithmic test pattein geneiation is veiy computationally expensive and can
encountei numeious diffculties, especially in ceitain types of netwoiks. Newei alteinatives aie based on pseudo-
random pattern generation Baidell et al., 1987] and fault simulation. In this stiategy, a laige set of patteins
is geneiated pseudo-iandomly with the aid of an inexpensive (haidwaie oi softwaie) geneiatoi. Typical choices
foi these aie lineai feedback shift iegisteis and lineai cellulai automata iegisteis (see below). The pseudo-iandom
set is used to stimulate a ciicuit, and, using a fault simulatoi, one can evaluate the numbei of faults that aie
coveied by this set. An algoiithmic test pattein geneiatoi is then applied to fnd coveiage foi the iemaining faults
(hopefully, a small numbei), and the pseudo-iandom set is thus augmented. The disadvantages aie that the
iesulting set is veiy laige and fault simulation is also computationally expensive. Howevei, this method piesents
an alteinative foi ciicuits wheie the application of deteiministic algoiithms foi all faults is infeasible.
Output Respunse Ana!ysis
Especially when designing a ciicuit including some BIST, one must decide how to check the coiiectness of the
ciicuit`s iesponses Baidell et al., 1987]. It is infeasible to stoie on-chip all expected iesponses, and thus a
common solution is to ieduce the ciicuit iesponses to ielatively shoit sequences: this piocess is called Jaa
tomaton and the shoit, compacted iesulting sequence is called a sgnaure. The noimal confguiation foi
data compaction testing is shown in Fig. 85.5. The n-input ciicuit is stimulated by an input pattein geneiatoi
(pseudo-iandom oi exhaustive if n < 20); the iesulting output vectoi(s), of length up to 2 , is compacted to a
veiy shoit signatuie of length | << 2 (usually | is aiound 16 to 32 bits). The signatuie is then compaied to
a known good value. The main advantages of this method aie that (1) the testing can be done at ciicuit speed,
(2) theie is no need to geneiate test patteins, and (3) the testing ciicuitiy involves a veiy small aiea, especially
if the ciicuit has been designed using scan techniques (see Section 85.2). The issues ievolve aiound designing
veiy effcient input geneiatois and compactois.
The main disadvantage of this method is the possibility of aliasing. When the shoit signatuie is foimed, a
loss of infoimation occuis, and it can be the case that a faulty ciicuit pioduces the same signatuie of a fault-
fiee ciicuit, thus iemaining undetected. The design method foi data compaction aims at minimizing the
piobability of aliasing. Using the compactois explained below, the piobability of aliasing has been theoietically
pioven to be 2
-|
, wheie | is the length of the compactoi (and thus the length of the signatuie). It is impoitant
to note that (1) the iesult is asymptotically independent of the size and complexity of the ciicuit undei test;
(2) foi | 16, the piobability of aliasing is only about 10
-6
and thus quite acceptable; and (3) the empiiical
iesults show that in piactice this method is even moie effective. Most of all, this is the chosen methodology
when BIST is iequiied foi its effectiveness, speed, and small aiea oveihead.
A secondaiy issue in data compaction is in the deteimination of the expected good" signatuie. The best
way is to use fault-fiee simulation foi both the ciicuit and the compactoi, and then the appiopiiate compaiatoi
can be built as pait of the testing ciicuitiy Baidell et al., 1987; Abiamovici, 1992].
FIGURE 85.5 Data compaction testing.
2000 by CRC Press LLC
The most impoitant issue is in the choice of a compactoi. Although no peifect" compactoi can be found,
seveial have been shown to be veiy effective. Seveial compaction techniques have been ieseaiched: tounng
et|nques, as in one`s count, syndiome testing, tiansition count, and Walsh spectia coeffcients; and sgnaure
ana|yss et|nques based on lineai feedback shift iegisteis (LFSRs) oi lineai cellulai automata iegisteis (LCARs).
Only these lattei ones aie discussed heie. LFSRs and LCARs aie also the piefeiied implementation foi the input
pattein geneiatois.
LFSRs as Pseudu-Randum Pattern Generaturs
An autonomous LFSR is a clocked synchionous shift iegistei augmented with appiopiiate feedback taps and
ieceiving no exteinal input Baidell et al., 1987; Abiamovici, 1992]. It is an example of a geneial lineai fnite
state machine, wheie the memoiy cells aie simple D ip-ops and the next state opeiations aie implemented
by EXOR gates only. Figuie 85.6 shows an example of an autonomous LFSR of length | 3. An LFSR of length |
can be desciibed by a polynomial with binaiy coeffcients of degiee |, wheie the nonzeio coeffcients of the
polynomial denote the positions of the iespective feedback taps. In Fig. 85.6, the high-oidei coeffcient foi x
3
is 1, and thus theie is a feedback tap fiom the iightmost cell s
2
; the coeffcient foi x
2
is 0, and thus no feedback
tap exists aftei cell s
1
; howevei, taps aie piesent fiom cell s
0
and to the leftmost stage since x and x
0
have nonzeio
coeffcients. Since this is an autonomous LFSR, theie is no exteinal input to the leftmost cell.
The state of the LFSR is denoted by the binaiy state of its cells. In Fig. 85.6, the next state of each cell is
deteimined by the implementation given by its polynomial and can be summaiized as follows: s
0
-
s
2
, s
1
-

s
0


s
2
, s
2
-
s
1
, wheie the s

-
denotes the next state of cell s

at each clock cycle. If the LFSR is initialized in a

nonzeio state, it cycles thiough a sequence of states and eventually comes back to the initial state, following
the functionality of the next-state iules implemented by its polynomial desciiption. An LFSR that goes thiough
all possible 2
|
1 nonzeio states is said to be desciibed by a rme polynomial (see theoiy of Galois felds
foi the defnition of piimitive), and such polynomials can be found fiom tables Baidell et al., 1987].
By connecting the output of each cell to an input of a ciicuit undei test, the LFSR implements an ideal input
geneiatoi, as it is inexpensive in its implementation and it piovides the stimuli in pseudo-iandom oidei foi
eithei exhaustive oi pseudo-exhaustive testing.
LFSRs as Signature Ana!yzer
If the leftmost cell of an LFSR is connected to an exteinal input, as shown in Fig. 85.7, the LFSR can be used
as a compactoi Baidell et al., 1987; Abiamovici, 1992]. In geneial, the undeilying opeiation of the LFSR is to
compute polynomial division ovei a fnite feld, and the theoietical analysis of the effectiveness of signature
analysis is based on this functionality. The polynomial desciibing the LFSR implementation is seen to be the
divisoi polynomial. The binaiy input stieam can be seen to iepiesent the coeffcients (high oidei fist) of a
dividend polynomial. Foi example, if the input stieam is 1001011 (bits aie input left to iight in time), the
dividend polynomial is x
6
- x
3
- x - 1. Aftei seven clock cycles foi all the input bits to have enteied the LFSR,
the binaiy output stieam exiting fiom the iight denotes the quotient polynomial, while the last state of the
cells in the LFSR denotes the iemaindei polynomial.
In the piocess of computing a signatuie foi testing the ciicuit, the input stieam to the LFSR used as a
compactoi is the output stieam fiom the ciicuit undei test. At the end of the testing cycles, only the last state
of the LFSR is examined and consideied to be the compacted signatuie of the ciicuit. In most ieal cases, ciicuits
have many outputs, and the LFSR is conveited into a multiple-input shift iegistei (MISR). A MISR is constiucted
by adding EXOR gates to the input of some oi all the ip-op cells; the outputs of the ciicuit aie then fed
thiough these gates into the compactoi. The piobability of aliasing foi a MISR is the same as that of an LFSR;
FIGURE 85.6 Autonomous LFSR.
2000 by CRC Press LLC
howevei, some eiiois aie missed due to cancellation. This is the case when an eiioi in one output at time is
canceled by the EXOR opeiation with the eiioi in anothei output at time - 1. Given an equally likely piobability
of eiiois occuiiing, the piobability of eiioi cancellation has been shown to be 2
1-m-N
, wheie m is the numbei
of outputs compacted and N is the length of the output stieams.
Given that the noimal length of signatuies used vaiies between | 16 and | 32, the piobability of aliasing
is minimal and consideied acceptable in piactice. In MISR, the length of the compactoi also depends on the
numbei of outputs tested. If the numbei of outputs is gieatei than the length of the MISR, algoiithms oi
heuiistics exist foi combining outputs with EXOR tiees befoie feeding them to the compactoi. If the numbei
of outputs is much smallei, vaiious choices can be evaluated. The amount of aliasing that actually occuis in a
paiticulai ciicuit can be computed by full fault simulation, that is, by injecting each possible fault into a
simulated ciicuit and computing the iesulting signatuie. Changes in aliasing can be achieved by changing the
polynomial used to defne the compactoi. It has been shown that piimitive polynomials, essential foi the
geneiation of exhaustive input geneiatois (see above), also possess bettei aliasing chaiacteiistics.
Data Cumpactiun vith Linear Ce!!u!ar Autumata Registers
LCARs aie one-dimensional aiiays composed of two types of cells: iule 150 and iule 90 cells Cattell et al.,
1996]. Each cell is composed of a ip-op that saves the cuiient state of the cell and an EXOR gate used to
compute the next state of the cell. A iule 150 cell computes its next state as the EXOR of its piesent state and
of the states of its two (left and iight) neighbois. A iule 90 cell computes its next state as the EXOR of the states
of its two neighbois only. As can be seen in Fig. 85.8, all connections in an LCAR aie neai-neighboi connections,
thus saving iouting aiea and delays (common foi long LFSRs).
Up to two inputs can be tiivially connected to an LCAR, oi it can be easily conveited to accept multiple
inputs fed thiough the cell iules. Theie aie some advantages of using LCARs instead of LFSRs: fist, the
localization of all connections, and second, and most impoitantly, it has been shown that LCARs aie much
bettei" pseudo-iandom pattein geneiatois when used in autonomous mode, as they do not show the coiie-
lation of bits due to the shifting of the LFSRs. Finally, the bettei pattein distiibution piovided by LCARs as
input stimuli has been shown to piovide bettei detection foi delay faults and open faults, noimally veiy diffcult
to test.
As foi LFSRs, LCARs aie fully desciibed by a chaiacteiistic polynomial, and thiough it any lineai fnite state
machine can be built eithei as an LFSR oi as an LCAR. It is, howevei, moie diffcult, given a polynomial, to
deiive the coiiesponding LCAR, and tables aie now used. The main disadvantage of LCARs is in the aiea
oveihead incuiied by the extia EXOR gates necessaiy foi the implementation of the cell iules. This is offset by
theii bettei peifoimance. The coiiesponding multiple-output compactoi is called a MICA.
Summary
Accessibility to inteinal dense ciicuitiy is becoming a gieatei pioblem, and thus it is essential that a designei
considei how the IC will be tested and incoipoiate stiuctuies in the design. Foimal DFT techniques aie
FIGURE 85.7 LFSR foi signatuie analysis.
FIGURE 85.8 LCAR foi signatuie analysis.
2000 by CRC Press LLC
conceined with pioviding access points foi testing (see tonro||a||y and o|sera||y in Section 85.2). As test
pattein geneiation becomes even moie piohibitive, piobabilistic solutions based on compaction and using fault
simulation aie moie widespiead, especially if they aie suppoited by DFT techniques and they can avoid the
majoi expense of dedicated exteinal testeis. Howevei, any technique chosen must be incoipoiated within the
fiamewoik of a poweiful CAD system pioviding semiautomatic analysis and feedback, such that the ru|e o[ en
can be kept undei contiol: if one does not fnd a failuie at a paiticulai stage, then detection at the next stage
will cost 10 times as much!
Dehning Terms
Aliasing: Whenevei the faulty output pioduces the same signatuie as a fault-fiee output.
Built-in self-test (BIST): The inclusion of on-chip ciicuitiy to piovide testing.
Fault coverage: The fiaction of possible failuies that the test technique can detect.
Fault simulation: An empiiical method used to deteimine how faults affect the opeiation of the ciicuit and
also how much testing is iequiied to obtain the desiied fault coveiage.
1
DDq
testIng: aramert et|nque o monor |e turren I
DD
that a ciicuit diaws when it is in a quiescent
state. It is used to detect faults which inciease the noimally low I
DD
.
LFSR: A shift iegistei foimed by D ip-ops and EXOR gates, chained togethei, with a synchionous clock,
used eithei as input pattein geneiatoi oi as signatuie analyzei.
MISR: Multiple-input LFSR.
Off-line testing: Testing piocess caiiied out while the tested ciicuit is not in use.
On-line testing: Concuiient testing to detect eiiois while ciicuit is in opeiation.
Pseudo-random pattern generator: Geneiates a binaiy sequence of patteins wheie the bits appeai to be
iandom in the local sense (1 and 0 aie equally likely), but they aie iepeatable (hence only pseudo-iandom).
Random testing: The piocess of testing using a set of pseudo-iandomly geneiated patteins.
Sequential fault: A fault that causes a combinational ciicuit to behave like a sequential one.
Signature analysis: A test wheie the iesponses of a device ovei time aie compacted into a chaiacteiistic value
called a signatuie, which is then compaied to a known good one.
Stuck-at fault: A fault model iepiesented by a signal stuck at a fxed logic value (0 oi 1).
Test pattern (test vector): Input vectoi such that the faulty output is diffeient fiom the fault-fiee output (the
fault is stimulated and detected).
Re!ated Tupic
23.2 Testing
Relerences
M. Abiamovici, M.A. Bieuei and A.D. Fiiedman, Dga| Sysems Tesng anJ Tesa||e Desgn, Rockville, Md.:
IEEE Piess, 1992.
P.H. Baidell, W.H. McAnney, and J. Savii, Bu|-In Tes [or VLSI. PseuJoranJom Tet|nques, New Yoik: John
Wiley and Sons, 1987.
K. Cattell and J.C. Muzio, Synthesis of one-dimensional lineai hybiid cellulai automata," IEEE Trans. Comuer
JeJ Desgn, vol. 15, no. 3, pp. 325-335, 1996.
N.H.E. Weste and K. Eshiaghian, Prnt|es o[ CMOS VLSI Desgn, Addison-Wesley, 1993.
T.W. Williams (Ed.), VLSI Tesng, Amsteidam: Noith-Holland, 1986.
Further Inlurmatiun
The authoi would like to iecommend ieading the book by Abiamovici et al. 1992] that, at the piesent time,
gives the most compiehensive view of testing methods and design foi testability. Moie infoimation on detei-
ministic pattein geneiation can also be found in Fau| To|eran Comung, edited by D.K. Piadhan, and foi
2000 by CRC Press LLC
newei appioaches of iandom testing the book by Baidell et al. contains basic infoimation. The latest state-of-
the-ait ieseaich is to be found mainly in pioceedings of the IEEE Inteinational Test Confeience.
85.2 Design lur Test
u|enr I. Dervog|u
Testing of electionic ciicuits, which has long been puisued as an activity that follows the design and manufactuie
of (at least) the piototype pioduct, has cuiiently become a topic of up-fiont investigation and commitment.
Today, it is not uncommon to list the Jesgn [or esa||y (DFT) featuies of a pioduct among the so-called
[untona| iequiiements in the defnition of a new pioduct to be developed. Just how such a majoi tiansfoi-
mation has occuiied can be undeistood by examining the testability pioblems faced by manufactuiing oiga-
nizations and consideiing theii impact on time to maiket (TTM).
The Testabi!ity Prub!em
The piimaiy objective of testing digital ciicuits at chip, boaid, oi system level is to detect the piesence of
haidwaie failuies induced by faults in the manufactuiing piocesses oi by opeiating stiess oi weaiout mecha-
nisms. Fuitheimoie, duiing manufactuiing, a secondaiy but equally impoitant objective is to accuiately
deteimine which component oi physical element (e.g., connecting wiie) is faulty so that quick diagnosis/iepaii
of the pioduct becomes possible. These objectives aie necessaiy due to impeifections in the manufactuiing
piocesses used in building digital electionic components/systems. All digital ciicuits must undeigo appiopiiate
level testing to avoid shipping faulty components/systems to the customei. Analog ciicuits may have minimum
and maximum allowable input signal values (e.g., input voltage) as well as infnitely many values in between
these that the component has to be able to iespond to. Testing of analog ciicuits is often achieved by checking
the ciicuit iesponse at the specifed uppei and lowei bounds as well as obseiving/quantifying the change of the
output iesponse with vaiying input signal values. On the othei hand, the behavioi of a digital system is
chaiacteiized by disciete (as opposed to continuous) iesponses to disciete opeiating state/input signal peimu-
tations such that testing of digital ciicuits may be achieved by checking theii behavioi undei eveiy opeiating
mode and input signal peimutation. In piinciple this appioach is valid. Howevei, in piactice, most digital
ciicuits aie too complex to be tested using such a biute foice technique. Instead, test methods have been
developed to test digital ciicuits using only a fiaction of all possible test conditions without saciifcing test
coveiage. Heie, es toerage is used to iefei to the iatio of faults that can be detected to all faults which aie
taken into consideiation, expiessed as a peicentage. At the piesent time the most populai [au| moJe| is the so-
called sut|-a fault model that iefeis to individual nets being consideied to be fault-fiee (i.e., gooJ newor|)
oi consideied to be peimanently stuck at eithei one of the logic 1 oi logic 0 values. Foi example, if the Jete
unJer es (DUT) contains seveial components (oi building blocks), wheie the sum of all input and output
teiminals (noJes) of the components is |, theie aie said to be 2| possible stuck-at faults, coiiesponding to each
of the ciicuit nodes being peimanently stuck at one of the two possible logic states. In geneial, a laigei numbei
of possible stuck-at faults leads to incieased diffculty of testing the digital ciicuit.
Foi the puipose of es aern (i.e., input stimulus) geneiation it is often assumed that the trtu unJer es
(CUT) is eithei fault-fiee oi it contains only one node which is peimanently stuck at a paiticulai logic state.
Thus, the most widely used fault model is the so-called sng|e sut|-a [au| model. Using this model each fault
is tested by applying a specifc test pattein that, in a good ciicuit, diives the paiticulai node to the logic state
which has the opposite value fiom the state of the fault assumed to be piesent in the faulty ciicuit. Foi example,
to test if node is stuck at logic state x (denoted by /x oi -x), a test pattein must be used that would cause
node to be diiven to the opposite of logic state x if the ciicuit is not faulty. Thus, the test pattein attempts
to show that node is not stuck at x by diiving the node to a value othei than x, which foi a two-valued digital
ciicuit must be the opposite of x (denoted by ~x). This leads to the iequiiement that to detect any stuck-at
fault /x, it is necessaiy to be able to contiol the logic value at node so that it can be set to ~. If the signal
value at node can be obseived diiectly by connecting it to a test equipment, the paiticulai fault /x can be
detected ieadily. Howevei, in most cases, node may be an nerna| node, which is inaccessible foi diiect
2000 by CRC Press LLC
obseivation fiom outside the component package. In that case, it is necessaiy to cieate a condition wheie the
value of the signal on an exteinally obseivable node, say node , will be diffeient foi each of the two possible
values that node can take on, that is, node shall be diiven to logic state y oi ~y depending upon whethei
node is at logic state x oi ~x, iespectively. Note that x and y may iepiesent the same oi diffeient logic states.
The exteinal pins of a component aie the only means of applying the stimuli and obseiving the behavioi of
that component. Duiing testing, a test pattein is used as the stimulus to detect the piesence of a paiticulai
fault by causing at least one output pin of the component to take on a diffeient value depending upon whethei
the taigeted fault is piesent oi not. Thus, a test pattein is used foi tonro||ng the ciicuit`s nodes so that the
piesence of a fault on a ciicuit node can be o|sereJ on at least one of the ciicuit`s exteinal pins. Solving the
dual pioblems of tonro||a||y and o|sera||y is the piimaiy objective of all test methods. The |ogt-o-n
rao of a digital ciicuit is a ielative measuie of the iatio of possible faults in the ciicuit to the numbei of signal
pins (i.e., not including the constant powei/giound pins) of that component. A laige-value logic-to-pin iatio
implies that logic states of a laige numbei of ciicuit nodes must be contiolled using a small numbei of exteinal
pins. As a iesult, conicting iequiiements foi contiollability and obseivability become haidei to satisfy, and
the ciicuit is consideied to be moie diffcult to test.
Considei Fig. 85.9, which depicts a single (hypothetical) negraeJ trtu (IC) component and shows its
inteinal ciicuitiy which uses foui NAND gates. The nodes of the ciicuit aie numbeied 1 thiough 12 and the
exteinal pins of the component aie labeled , B, and C. To detect if node 7 is stuck at logic 0 (i.e., 7/0), a test
pattein must be found that sets node 7 (and hence, node 5) to the logic 1 state. This can be achieved by setting
eithei oi both of the exteinal pins and B to the logic 0 state. Fuitheimoie, to obseive (oi deduce) the value
of node 7 at the only exteinally visible ciicuit pin, C, it is necessaiy to cieate a condition wheie the logic state
of node 12 becomes dependent on the value of node 7. The only path fiom node 7 to node 12 passes thiough
node 10, and since node 10 is the output of a NAND gate the second input to that gate (i.e., node 6) must be
set to the logic 1 state by setting input pin to the logic 1 state. Theiefoie, the only possible test pattein foi
7/0 is 1 and B 0. At this point, we must still continue the analysis to see if indeed node 12 will ieect
the value of node 7. With input teiminals and B set to logic 1 and logic 0, iespectively, node 9 will be set to
logic 0, which causes node 11 to become logic 1. With these settings, the value at node 12 will be deteimined
by the value at node 10 and the test pattein is valid. Table 85.2 shows the values of all ciicuit nodes when this
test pattein is applied to the ciicuit of Fig. 85.9.
It should be evident fiom the simple example of a tom|naona| trtu desciibed above that test pattein
geneiation foi digital ciicuits can be veiy diffcult and involved. The pioblem becomes much moie complex
when dealing with sequena| trtus, wheie the nerna| sae ara||es (i.e., bistable memoiy stoiage elements
such as latches and ip-ops) must be tieated as seuJo-nus and seuJo-ouus that must be contiolled and
obseived using the exteinal pins of the component. In this case test patteins become es sequentes that must
be applied in piecise oidei, and outputs must be obseived only at piesciibed times. Thus, the testing of sequential
FIGURE 85.9 Example logic ciicuit with inteinal node 7 stuck at 0 (7/0).
TABLE 85.2 Test Pattein foi Node 7/0 foi the Ciicuit in Fig. 85.9
B 1 2 3 4 5 6 7 8 9 10 11 12 C
1 0 1 0 1 0 1 1 1 1 0 0 1 1 1 good ciicuit
1 0 1 0 1 0 1 1 0 1 0 1 1 0 0 with fault 7/0
2000 by CRC Press LLC
ciicuits is much haidei to achieve compaied to the testing of combinational ciicuits. Computei piogiams,
called automatic test pattein geneiation (ATPG) piogiams, have been developed foi geneiating test patteins
foi combinational oi sequential ciicuits. By fai, the geneiation of test patteins foi combinational ciicuits is
bettei undeistood and automated than doing the same foi sequential ciicuits.
Befoie discussing the vaiious techniques that may be used to impiove testability of digital ciicuits, it is
necessaiy to mention the ielated pioblem of deteimining test effectiveness. A typical digital system contains a
veiy laige numbei of possible stuck-at faults. This and the logical complexity of the ciicuits make it unacceptable
to guess" how effective the test patteins (oi the diagnostic piogiam) will be in detecting all possible faults.
This pioblem is often appioached in a foimal mannei by using a class of test tool called a [au| smu|aor
piogiam. A fault simulatoi uses the given set of test patteins to simulate the given ciicuit fist when theie aie
no faults assumed piesent (i.e., good ciicuit simulation). Next, the ciicuit is simulated with the same set of test
patteins, but this time the effects of each possible stuck-at fault aie consideied one at a time. Foi a given test
pattein, and given stuck-at-type fault, if the output of the good ciicuit simulation diffeis fiom the output
obtained duiing fault simulation, then the given fault will be detected by the given test pattein. This way, it is
possible to deteimine the peicentage of all possible stuck-at faults that may be piesent in a digital ciicuit which
will be coveied by the given set of test patteins.
Most ATPG piogiams opeiate by picking a possible fault fiom among the possible faults, geneiating a specifc
test pattein that coveis it, simulating the logic ciicuit with the newly geneiated test pattein to deteimine which
othei faults aie incidentally coveied by the same pattein, and continuing the piocess until all faults have been
consideied. Of the two ielated piocesses of es aern generaon and [au| smu|aon, the lattei is by fai the
moie time-consuming one.
A diffeient appioach is taken in some testability analysis tools wheieby iathei than deteimining which faults
aie coveied by a given test pattein, the analysis piogiam assigns a numeiic value to indicate the degiee of
diffculty of contiolling and obseiving the digital ciicuit`s nodes. This analysis, which can be done much moie
quickly compaied to peifoiming fault simulation, should be done piioi to attempting to geneiate the test
patteins foi a ciicuit so that time will not be spent unnecessaiily on digital ciicuits which aie likely to piesent
diffculties foi the ATPG/fault-simulation piocess to deal with.
Design lur Testabi!ity
Low-cost/high-volume manufactuiing iequiies that pioduct testability be consideied up fiont since a pioduct
which is inheiently haid to test will cost both time and money to achieve a desiied level of quality. Theie aie
many steps that can be taken to impiove the testability of digital ciicuits and systems. The following subsections
desciibe some of the techniques that can be used.
Ad-Huc Techniques [Abramuvici et a!., 1990, Barde!! et a!., 1978j
CIrcuIt/System Reset RequIrements. A simple and stiaightfoiwaid mechanism foi iesetting a digital ciicuit
to a known state is an essential iequiiement foi testability. It should be noted that the iequiiement is not only
foi having the ieset function piovided but fuithei that it should be simple to execute. Foi example, applying
a defned sequence of exteinal signals to a ciicuit which must be synchionized with a fiee-iunning clock signal
would not be consideied a simple ieset mechanism. Instead, keeping an exteinal signal at some logic value foi
a minimum duiation is a much moie desiiable appioach. It is veiy desiiable that the ieset function be
asynchionous (i.e., not iequiie system clock pulses to execute) since duiing powei-up a ciicuit may need to be
ieset even befoie fiee-iunning clock pulses can be staited.
C|vc| Cvntrv| RequIrements. Anothei veiy impoitant iequiiement foi implementing DFT is the ability to
contiol the clocking of the inteinal logic of the digital ciicuit. If the exteinal clock signal is gated with some
othei signals such that it is necessaiy to deteimine how to set these othei signals to theii iequiied values to
allow the exteinally applied clock pulse to ieach the inteinal ip-op clock teiminals, then the ATPG piogiam
has anothei level of constiaints to iesolve in geneiating the test patteins. Fuitheimoie, some of these additional
iequiiements may pose diffculties in satisfying them duiing component and/oi system testing. Most ATPG
piogiams assume that once the test pattein has been applied to the pins of the component, the system`s iesponse
to that pattein can be captuied by applying an exteinal clock pulse which enables the inteinal ip-ops to
2000 by CRC Press LLC
iespond to the test pattein. Thus, the ATPG piogiams assume that the inteinal ip-op clock inputs aie
contiolled diiectly fiom an exteinal pin of the component. This veiy desiiable chaiacteiistic is often expiessed
by stating that exerna||y a|eJ t|ot| u|ses are no a||oweJ o |e gaeJ |y o|er sgna|s |e[ore |ese reat| |e
t|ot| ermna|s o[ |e nerna| [-[os. A side beneft of this design iule is that it pievents glitches (i.e.,
undesiiable pulses) which might be geneiated at the ip-op clock teiminals due to changing the othei inputs
to the clock gating ciicuit while the clock pulse is piesent.
MunugIng "Unused" 1nputs v] Cvmpvnents. When designing digital systems fiom existing components theie
may be inputs of those components that, foi the cuiient implementation, aie not needed. Foi example, if a
two-input AND gate is needed to implement a logic ciicuit on a piinted ciicuit boaid, it may be possible to
use one of the unused thiee-input AND gate elements fiom an IC package alieady piesent on that boaid. In
this case, the unused thiid input of that AND gate must be connected to the logic 1 level in oidei that a thiee-
input AND function may be implemented using the othei two inputs to that gate. Thus, the unused input to
the AND gate may be connected diiectly to the V
tt
(i.e, powei supply) signal. Similaily, if a ip-op contains
unused rese oi t|ear teiminals, these may be tied off to theii iespective deasseited states. In many cases piinted
ciicuit boaids aie tested using an n-trtu eser which uses a |eJ-o[-na|s test fxtuie to make physical contact
with selected nets on the boaid so that theii values can be obseived oi contiolled by the testei. Foi the in-
ciicuit testei to contiol the value of a net it has to backdiive the output of the component which noimally
diives that net. Since IC components have limited output diive capabilities, the in-ciicuit testei can oveicome
the electiical diive fiom that component and can foice that net to a value opposite the value which the diiving
IC is tiying to achieve. By keeping such backdiiving conditions to last only a veiy shoit peiiod, damage to the
opposing IC component is pievented. Howevei, if the net is diiven not by an IC but diiectly fiom the V
tt
oi
giound (CnJ) signals, then the in-ciicuit testei may not be able to oveicome theii diive. Fuitheimoie, back-
diiving the V
tt
oi CnJ levels would pievent the othei IC components fiom being able to peifoim theii noimal
functions. Instead, if the logic signals to such unused teiminals aie applied using u||-u oi u||-Jown iesistois
when connecting these to the V
tt
oi CnJ levels, iespectively, these signals may be contiolled by the in-ciicuit
testei. Foi example, this way it becomes possible to set/ieset a ip-op value by using the noimally unused"
pieset/cleai teiminal of that ip-op. Note that if the ip-op contains both a pieset and a cleai input which
aie unused, these must be pulled up (oi pulled down) thiough sepaiate iesistois so that each can be contiolled
by the in-ciicuit testei independent of the othei. This is illustiated in Fig. 85.10.
Synchrvnvus versus Asynchrvnvus DesIgn Sty|e. Moie than any othei issue, discussions conceining synchio-
nous veisus asynchionous design style cieate the most disagieements conceining design foi testability. Many
logic designeis who aie expeiienced in using SSI and MSI IC chips have adapted a design style wheie synchionous
(e.g., clocked) and asynchionous (e.g., self-timed) designs aie fieely mixed togethei. Using clocked ip-ops
FIGURE 85.10 Using pull-up iesistoi to tie off unused pieset/cleai inputs of ip-ops.
2000 by CRC Press LLC
with asynchionous pieset/cleai inputs is a typical example of this design style. Similaily, building latches out
of, say, cioss-coupled NAND gates and using these as state vaiiables in implementing fnite-state machines used
to be a veiy common technique. Howevei, conceins about system initialization and pattein geneiation have
made this style undesiiable foi implementing DFT. Indeed, most of the so-called srutureJ design styles
desciibed below make it a iequiiement that all inteinal stoiage elements be constiucted fiom clocked ip-ops,
and feedback loops in combinational ciicuits aie bioken with the inseition of such ip-ops, along the feedback
paths. Asynchionous ciicuits suffei fiom combinational ciicuit hazaids that aie glitches cieated as a iesult of
delay diffeiences along ciicuit paths. Some hazaids may be pievented by constiaining the mannei (i.e., sequence)
in which ciicuit inputs aie allowed to be changed. Wheieas such constiaints may be met duiing iegulai system
opeiation, often test pattein geneiation algoiithms cannot take such constiaints into account. Theiefoie,
asynchionous logic may cieate seveie pioblems duiing testing.
AvvIdIng Redundunt LvgIc. Technically speaking, iedundancy is the only ieason why a given stuck-at fault
might not be detectable by any test. Foi example, if an INVERTER function is implemented by tying both
inputs of a two-input NAND gate togethei, then a stuck-at 1 fault on eithei one of the inputs becomes
undetectable since the output signal can still be deteimined coiiectly by the iemaining nonfaulty input signal.
This cieates two pioblems. Fiist, conventional ATPG piogiams might spend a lot of time tiying to geneiate a
test pattein foi such a fault befoie they declaie the fault untestable. Second, the piesence of an undetectable
fault can cause a detectable fault to become undetectable (it may also cause an undetectable fault to become
detectable). Foi example, considei a paiity checking ciicuit in which an existing stuck-at fault may cause the
wiong paiity to be geneiated, and the existence of a second fault may coiiect the paiity and hence hide both
failuies. The iemedy foi these situations is to tiy to avoid iedundancy in the fist place, and when this is not
possible piovide additional ciicuit modes wheie the iedundant ciicuits might be isolated. Alteinately (oi in
addition) it may be useful to piovide additional test points, as desciibed below.
PrvvIdIng Test PvInts. A test point is an input oi output signal to contiol oi obseive inteimediate signals in
a logic ciicuit. Foi example, if tiiple iedundancy has been used to implement a fault-toleiant ciicuit, additional
output signals might be piovided so that signal values fiom the identical functional units become individually
obseivable, impioving the testability of the oveiall ciicuit. Similaily, contiol signals might be piovided so that,
duiing testing, outputs fiom some functional units may be foiced into ceitain states which allow easiei
obseivation of the outputs fiom othei ciicuits. Recommended sites foi inseiting test points include iedundant
nets, nets with laige fan-outs, pieset and cleai inputs of ip-ops, nets that caiiy system clock signals, (at least
some of the) inputs to logic ciicuit gates with laige numbei of inputs (i.e., laige fan-in), data and/oi addiess
lines of bus lines, as well as inteimediate points in cascaded ciicuits (such as long iipple counteis, shift iegisteis).
LvgIc PurtItIvnIng. Tiaditionally logic paititioning has been used as a stiategy when the ciicuit is too
laige/complex foi the test geneiation tools to handle. Thus, its objective is to ieduce the numbei of ciicuit
nodes that must be consideied jointly in oidei to geneiate test patteins. The paititioning piocess identifes the
|ogt tones, which aie sections of logic ieceiving inputs fiom multiple input souices and geneiating a single
output. Thus, a digital ciicuit would be bioken into as many individual logic cones as theie aie individually
obseivable output signals. Obviously, the logic cones may (and often do) oveilap with each othei since they
shaie common input signals oi inteimediate signals geneiated fiom inside one paitition and used in anothei
paitition. This is illustiated in Fig. 85.11(a), wheie two oveilapping cones of logic aie shown. Heie, logic cones
O
1
and O
2
contain piimaiy inputs I
1
, I
2
, I
3
, I
4
and I
3
, I
4
, I
5
, I
6
, iespectively. When eithei paitition is dependent
on moie inputs than what the ATPG tools oi the testei can accommodate, it is possible to inseit an additional
gate, contiolled by a testei input in oidei to test each paitition independently of the othei. This is illustiated
in Fig. 85.11(b), wheie an additional input pin I

has been added such that with I

set to logic 0 by the testei,

it is possible to test eithei paitition without iequiiing to contiol shaied inputs I
3
oi I
4
. Logic paititioning has
become moie impoitant as a iesult of incieased use of seuJo-ex|ause esng (to be desciibed latei).
TestIng Emhedded Memvry B|vc|s. A majoi testability pioblem aiises when a iegulai-stiuctuie memoiy block
such as iandom-access memoiy (RAM) oi iead-only memoiy (ROM) is embedded into a logic ciicuit. This
cieates thiee pioblems:
2000 by CRC Press LLC
1. Testing logic that is downstieam fiom the RAM block (i.e., output of RAM block diives the downstieam
logic) is diffcult since this iequiies setting the test pattein at the RAM outputs. This pioblem is usually
solved by pioviding a bypass mode wheie data inputs to the RAM (oi ROM) block aie channeled diiectly
to the RAM (oi ROM) outputs without (oi in addition to) being stoied inside the RAM block. This way
the RAM data outputs can be contiolled by contiolling the data inputs as desiied.
2. Testing logic that is upstieam fiom the RAM block (i.e., outputs fiom logic ciicuit aie captuied by the
RAM block) is diffcult since the obseivation point is the RAM block. That is, it is necessaiy to access
the RAM block in oidei to obseive the test iesults. This pioblem might be solved by impioving the
obseivability of the RAM inputs and/oi making the RAM outputs moie easily obseivable as well as
pioviding the |yass capability. This way, inputs to the RAM might be bypassed diiectly to the RAM
outputs wheie they may be obseived. This may iequiie adding an o|sere-on|y iegistei to captuie the
RAM outputs.
3. Testing of the RAM block itself is diffcult since contiolling its inputs and obseiving its outputs iequiie
manipulating the upstieam and downstieam logic ciicuit blocks, which may be diffcult to achieve.
Solution to this pioblem involves pioviding adequate contiol of the RAM block inputs (data, addiess,
and iead/wiite contiol) as well as pioviding obseivability of the RAM outputs. In effect, the embedded
RAM block can be made testable as if it was a stand-alone block wheie established memoiy test algoiithms
can be applied Bieuei and Fiiedman, 1976].
Figuie 85.12 illustiates how to impiove testability of an embedded RAM stiuctuie.
Structured Techniques
An alteinate appioach to impioving the testability of digital ciicuits is to caiiy out the ciicuit design by following
ceitain iules that, by constiuction, assuie high testability of the iesulting ciicuits. Since the main pioblem in
achieving testability of a digital ciicuit is achieving adequate contiollability/obseivability of its inteinal nodes,
stiuctuied DFT appioaches Baidell and McAnney, 1978] follow stiict design iules that aie aimed at achieving
this goal. Fuitheimoie, most stiuctuied DFT appioaches iequiie/iecommend additional design iules aimed at
pieventing incoiiect ciicuit opeiation as a iesult of signal iaces and hazaids.
FIGURE 85.11 (a) Logic paititioning with oveilapping logic cones. (b) Adding an additional test point to ieduce depen-
dence on piimaiy inputs.
2000 by CRC Press LLC
Leve|-SensItIve Scun DesIgn (LSSD). Level-sensitive scan design Eichelbeigei and Williams, 1978] imposes
stiict iules on clock signal usage and allows implementing sequential behavioi to be implemented only using
the shift-iegistei latch (SRL). In the fist place, by not allowing any feedback involving combinational ciicuit
elements alone, the LSSD appioach pievents timing failuies that might be piesent in puiely asynchionous
designs. Fuitheimoie, iigid clocking iules aie stated in oidei to pievent SRL data inputs fiom changing while
the clock pulse(s) is (aie) tiansitioning. Hence, the digital ciicuit is sepaiated into two sections: (1) a iobust
(i.e., level-sensitive) multi-input/multi-output combinational ciicuit and (2) a set of SRL elements with which
sequential behavioi is implemented. In addition to theii noimal system inteiconnections each SRL is also
connected to its two neighboiing SRLs to foim a shift-iegistei stiuctuie. The seiial shift input and shift output
signals aie labeled stan-n and stan-ou, iespectively, and tieated as piimaiy input/output teiminals. Figuie 85.13
FIGURE 85.12 Pioviding testability in a design containing an embedded memoiy block.
FIGURE 85.13 (a) LSSD ciicuit model. (b) SRL block diagiam. (c) SRL logic diagiam.
2000 by CRC Press LLC
shows an LSSD ciicuit model and the geneial foim of an SRL. The signifcance of the shift-iegistei (often
iefeiied to as the stan-regser) stiuctuie is that, duiing testing, it allows each SRL`s value to be individually
contiollable and obseivable by shifting (i.e., scanning) a seiial vectoi into/out of the scan iegistei. Hence, the
SRLs can be tieated as seuJo-nu/ouu ermna|s, and the testing of the digital ciicuit is ieduced to that of
a combinational ciicuit only. Figuie 85.13(a) shows an LSSD ciicuit model, and the geneial foim of an SRL is
given in Fig. 85.13(b). A possible gate-level ciicuit implementation of an SRL is shown in Fig. 85.13(c).
Among the most impoitant LSSD design iules aie the following:
1. All inteinal stoiage is implemented using SRLs. Each SRL opeiates such that the L1 latch accepts one
oi the othei of the system data-in oi the scan-in data values depending upon whethei the system clk oi
the scan-in clk clock pulse is applied, iespectively. The L2 latch accepts the L1 latch value when the scan-
out clk clock pulse is applied. The L1 and L2 latches aie stable (i.e., cannot change) when the clocks aie off.
2. The SRL clocks system clk, scan-in clk, and scan-out clk must be contiolled fiom piimaiy ciicuit
teiminals and must be opeiated in nonoveilapping fashion. This eliminates dependency on minimum
ciicuit delay and assuies hazaid-fiee (i.e, level-sensitive) opeiation.
3. System data-out fiom SRL
1
may feed the system data-in teiminal of SRL
2
only if the system clk which
feeds SRL
1
does not oveilap with the system clk which feeds SRL
2
. This iule pievents the data input to
a latch fiom changing while its clock signal is tiansitioning.
4. All SRLs aie inteiconnected into one oi multiple shift iegisteis by connecting the scan-out teiminal fiom
one SRL to the scan-in teiminal of the next one in seiies. If multiple shift iegisteis aie implemented,
each must be capable of being shifted simultaneously with the otheis and must have its own scan-in
and scan-out piimaiy teiminals.
Scun Puth. The stan-a| Funatsu et al., 1975] appioach can be seen as a geneialization of the LSSD appioach
since it follows the same piinciples but uses standaid D-type ip-ops as the stoiage elements instead of the
SRLs. The scannable ip-ops can be implemented using dual-poited latches (similai to the L1 latch in the
SRL) oi using a multiplexoi to select between the scan-in and system data-in signals to feed the D input of a
standaid D-type ip-op, as shown in Fig. 85.14.
Scun/Set LvgIc. Scan/set Stewait, 1977] is anothei foim of implementing scan technology wheieby the
sequential ciicuit stiuctuie is sepaiated fiom its accompanying scan/set iegistei. This is illustiated in Fig. 85.15.
A vaiiation on this scheme is the so-called shadow-iegistei concept that has been implemented in some off-
the-shelf IC components AMDI, 1987].
Rundvm-Access Scun. Random-access scan Ando, 1980] uses a technique akin to addiessing locations in a
memoiy (e.g., RAM) block in oidei to make the states of all stoiage elements contiollable and obseivable fiom
piimaiy input/output teiminals. Using this appioach, each stoiage element is made individually addiessable
(i.e., accessible) so that in oidei to contiol and/oi obseive the value of an individual stoiage element it is not
necessaiy to shift in/shift out all othei stoiage elements as well. Figuie 85.16(a) shows the geneial model of a
digital ciicuit employing the iandom-access scan appioach. A possible gate-level ciicuit implementation of an
addiessable latch is given in Fig. 85.16(b).
FIGURE 85.14 Model of a digital ciicuit with scan path.
2000 by CRC Press LLC
Using this appioach, each stoiage element in the ciicuit is given a unique x/y addiess and the decoded addiess
signals aie connected to the x/y addiess inputs of the latches. As seen in the ciicuit of Fig. 85.16(b), each latch
can then be individually wiitten into using the stan-n teiminal oi its output can be obseived using the stan-
ou teiminal, piovided that the paii of x/y addiess lines connected to the cuiient latch aie both asseited (i.e.,
FIGURE 85.15 Geneiic scan/set ciicuit design.
FIGURE 85.16 (a) Geneial model foi digital ciicuit implementing iandom-access scan. (b) Logic diagiam foi addiessable
latch.
2000 by CRC Press LLC
set to logic 1). Fuitheimoie, wheieas it is also necessaiy to apply the stan-n t|| in oidei to wiite into the latch,
no clock is necessaiy to obseive the latch output. This is a convenient featuie that allows the latch values to be
selectively obseivable even while the iegulai system opeiations aie being executed. The stan-ou values fiom
the individual latches aie combined togethei into a single AND gate and biought out to a piimaiy output
teiminal of the ciicuit. This aiiangement woiks since foi any given addiess only one of the addiessable latches
will be selected and the scan-out fiom all othei latches will be foiced to the logic 1 state. On the othei hand,
a disadvantage of this appioach is that befoie addiessing each latch its piopei addiess must fist be applied to
the ciicuit.
Bvundury Scun. Unlike the othei scan-based techniques desciibed above, boundary scan IEEE, 1990] is
intended piimaiily foi testing the boaid-level inteiconnections among the IC components on a piinted ciicuit
boaid (PCB). In effect, boundaiy scan is a special foim of scan path that is implemented aiound eveiy I/O pin
of an IC component in oidei to piovide contiollability and obseivability of the I/O pin values duiing testing.
Test contiol signals piovided by an on-chip contiollei aie used to disable the boundaiy-scan cells duiing iegulai
system opeiation so that signal values can ow in/out of the IC component without inteifeience fiom the test
ciicuits. Duiing testing, ouu pin values can be contiolled using values pieloaded into the boundaiy-scan
iegistei. Similaily, signal values ieceived on the nu pins can be captuied into the boundaiy-scan iegistei and
subsequently shifted out to be obseived on an exteinal testei.
Boundaiy scan has become an impoitant tool in achieving design foi testability following the adoption of
the IEEE 1149.1 Test Access Poit and Boundaiy-Scan Aichitectuie in 1990. The IEEE 1149.1 Standaid defnes
a mandatoiy foui-pin (plus an optional ffth pin) test access poit (TAP) foi pioviding the inteiface between
the IC component and a digital testei. TAP signals compiise test data input (TDI), test data output (TDO),
test clock (TCK), and test mode select (TMS) plus an optional asynchionous tap ieset (TRST) signal. The
oveiall IEEE 1149.1 test aichitectuie (see Fig. 85.17) includes:
The TAP
The TAP contiollei
The instiuction iegistei (IR)
A gioup of mandatoiy and optional test data iegisteis (TDRs)
The TAP contiollei is chaiacteiized by a 16-state fnite-state machine (FSM) whose behavioi is defned by
the IEEE 1149.1 Standaid. State tiansitions of the TAP FSM aie contiolled by the TMS input line and the
dedicated test clock, TCK. Figuie 85.18 shows the state-tiansition diagiam foi the TAP FSM.
FIGURE 85.17 Aichitectuie of IEEE 1149.1 boundaiy-scan standaid.
2000 by CRC Press LLC
A most impoitant test data iegistei defned by the IEEE 1149.1 Standaid is the boundaiy-scan iegistei that
has individual cells associated with each I/O pin of the IC component. Mandatoiy and peimissible featuies of
the boundaiy-scan iegistei cells aie defned by the standaid. In addition, a special single-bit iegistei called the
BYPASS iegistei has been piovided to fuinish a moie effcient way to shift data thiough IC components when
multiple ICs aie chained togethei by connecting the TDO output fiom one component to the TDI input of
anothei.
Anothei mandatoiy featuie of the IEEE 1149.1 Standaid is the instiuction iegistei and an associated list of
mandatoiy/peimissible instiuctions that govein the behavioi of the IC component duiing testing. The thiee
mandatoiy instiuctions aie called SAMPLE/PRELOAD, BYPASS, and EXTEST. SAMPLE allows taking a snap-
shot of the noimal opeiation of the IC, wheieas PRELOAD is used foi shifting the captuied values out while
new values aie loaded into the boundaiy-scan iegistei. BYPASS allows shoitening the (electiical) distance
between the TDI and TDO pins by pioviding a single-bit iegistei as a shoitcut duiing scan opeiations involving
multiple IC components that aie connected in seiies. EXTEST is the woikhoise" instiuction that allows diiving
the signal values on the component`s output pads fiom the boundaiy iegistei while captuiing the input values
into theii iespective cells in the boundaiy iegistei. This is followed by shifting the captuied values out (using
the TDO output) while simultaneously shifting in the new diiving values (using the TDI input).
An alteinative to using boundaiy scan is to use a tiaditional" in-ciicuit testei that uses a special bed-of-
nails" fxtuie. In this appioach Paikei, 1987], eveiy net on a PCB would be piobed using a testei pin which
comes in physical contact with that net such that the cuiient signal value of the net can be obseived by the
testei. The testei can also be used to contiol the signal values of the individual nets by injecting appiopiiate
cuiients thiough the testei pins. Howevei, since each net is alieady connected to an output pin of a component
on the PCB, this appioach amounts to |at|Jrng the output diiveis of IC components and theiefoie poses a
potential iisk of damage to the IC components. This appioach is becoming moie diffcult and/oi costly to
implement as the numbei of nets goes up and IC pin spacing is ieduced. Fuitheimoie, due to fxtuiing
diffculties, double-sided PCBs cannot be tested in this mannei. The IEEE 1149.1 boundaiy-scan standaid
IEEE, 1990] helps solve these pioblems by pioviding convenient diiect access to the I/O pins of an IC
component without iequiiing the tiaditional bed-of-nails fxtuie.
The "CrvssChec|" TechnIque. The CiossCheck appioach Gheewala, 1989] uses cells with built-in test points
to obseive ciitical signal values. The test points aie connected to an undeilining giid stiuctuie using veiy small
FETs called tross-on swt|es. An on-chip test contiol ciicuit geneiates the necessaiy signals to addiess the
individual piobe lines and captuie the iesults in a mu|-nu sgnaure regser (MISR). Test patteins can be
FIGURE 85.18 State-tiansition diagiam foi the TAP FSM.
2000 by CRC Press LLC
geneiated exteinally oi by using an on-chip pattein geneiatoi, and the fnal test signatuie (i.e., contents of
MISR) can be accessed using dedicated test pins, such as by pioviding an IEEE 1149.1 TAP (see pievious
subsection). Figuie 85.19 shows how the CiossCheck technique is implemented on an ASIC.
CiossCheck methodology piovides a high degiee of obseivability of the ASIC. Since it is not possible to
piovide obseivability of all signals of a design, caieful analysis must be peifoimed to deteimine the most
effective points foi inseiting the cioss-point switches. Similaily, the size of the giid stiuctuie foi the piobe lines
might be chosen to be design-dependent. Howevei, in many instances it may be bettei to implement the piobe
lines as pait of the IC mastei slice in oidei to ieduce the amount of customization to a minimum.
The beneft offeied by the CiossCheck technique is due to the potential foi the ieduced numbei of test
patteins necessaiy to test an ASIC. This is due to the fact that as obseivability of inteinal nodes is incieased it
becomes easiei to geneiate effcient test patteins which can detect many faults simultaneously. Fuitheimoie,
incieased obseivability of inteinal nodes also impioves diagnosability and may help deteimine the ioot cause
of a failuie soonei. On the negative side, the CiossCheck technique does not help impiove contiollability of
inteinal nodes as achieved using scan-path techniques. Also, a piimaiy disadvantage of the CiossCheck meth-
odology is aiea penalty due to iouting channels that must be set aside foi the giid stiuctuie. Fuitheimoie,
added capacitance of the cioss-point switches may affect peifoimance, especially in high-speed applications.
In addition, since the technique offeis veiy good obseivability but no contiollability of the inteinal nodes, it
lacks the advantage offeied by scan-based appioaches foi system debug and inteinal path-delay testing [Dei-
visoglu and Stong, 1991]. Howevei, iecent advances have been made that impiove the contiollability of inteinal
nodes using the CiossCheck technique in gate-aiiay ICs.
FIGURE 85.19 (a) Cioss-point switch implementation. (b) Oveiview of the CiossCheck technique.
2000 by CRC Press LLC
BuI|t-In Se|]-Test (B1ST) TechnIques. The teim built-in self-test (oi BIST) is a geneiic name given to any
test technique in which an exteinal test iesouice (e.g., component testei) is not needed to apply test patteins
and check a ciicuit`s iesponse to those patteins. This implies that the test patteins must be pieloaded into the
taiget device oi be geneiated by the taiget device itself, in ieal time. Foi example, dedicating a section of an
IC component foi implementing a ROM-based sequencei to apply piestoied patteins to test anothei section
of that IC would be classifed as a BIST technique. It is often moie cost effective to geneiate the test patteins
in ieal time (i.e., duiing testing), but in geneial it is not possible to develop ieal-time test pattein geneiation
techniques that geneiate aibitiaiily selected test patteins without additionally geneiating unnecessaiy ones.
Note that wheieas stoiing the test patteins in a ROM might be acceptable in some cases, the size of ROM
necessaiy to stoie the test patteins pievents this technique being used foi implementing BIST in laige/complex
digital ciicuits.
One appioach to test vectoi geneiation is to ignoie the specifcs of the taiget ciicuit and enumeiate all
possible peimutations of inputs. Thus, using ex|ause testing, an n-input combinational logic cone would be
tested by checking its iesponse to all 2n peimutations of input values. In this case, a binaiy countei can be
used as the test pattein geneiatoi (TPG). Othei, moie effcient countei foims (such as a maxma|-|eng| |near
[eeJ|at| s|[ regser, LFSR) may also be used as the TPG. An LFSR is a special kind of ciiculai-shift iegistei
wheie the seiial data input is deteimined by an EXCLUSIVE-OR function of some of the bit positions. Bit
positions which aie included in the feedback EXCLUSIVE-OR function aie iefeiied to as the tap positions. Foi
any given Jegree (i.e., numbei of bits) n of LFSR theie is at least one set of tap positions that iesult in the LFSR
going thiough all nonzeio n-bit peimutations when it is staited in any nonzeio state. An LFSR that can go
thiough all 2n states is called a maximal-length LFSR. Figuie 85.20 shows a 3-bit maximal-length LFSR and
the state sequence that it pioduces. Exhaustive testing guaiantees that all Jeeta||e faults which do not tiansfoim
a combinational ciicuit into a sequential ciicuit will be detected. Depending upon the clock fiequency, this
appioach becomes impiactical to apply when the numbei of input vaiiables goes up (usually above 22)
McCluskey, 1984].
In cases wheie the numbei of test patteins necessaiy to achieve exhaustive testing is too laige to be applicable,
a ielated technique, called pseudo-random testing, may be used. Pseudo-iandom testing achieves many of the
benefts of exhaustive testing but iequiies much fewei test patteins. This is achieved by geneiating the test
patteins in iandom fashion fiom among the 2n possible patteins. Howevei, the iandom geneiation of test
patteins is done using a deteiministic algoiithm that pioduces test patteins in iepeatable sequence. Befoie
pseudo-iandom testing is chosen, it is necessaiy to examine the pseudo-iandom test iesistance of the ciicuit.
Foi example, if 500,000 pseudo-iandom test patteins aie applied to a 20-input AND gate, theie is only a
0.00004% piobability that an essential test pattein (which sets all 20 inputs to logic 1) will be included among
them.
Yet anothei ielated technique is to use seuJo-ex|ause testing that aims at bieaking a ciicuit into sepaiate
paititions and testing each paitition exhaustively Baizilai et al., 1985; Deivisoglu, 1985; Baidell and McAnney,
1984]. Pseudo-exhaustive testing uses the same techniques used in exhaustive testing foi testing the individual
paititions without geneiating test patteins that covei the entiie ciicuit. Mathematical consideiations foi pseudo-
iandom/pseudo-exhaustive testing aie too complex to desciibe heie. The following example is piesented foi
illustiation puiposes only. Figuie 85.21 depicts the combinational poition of a digital ciicuit consisting of a
numbei of oveilapping logic cones that each pioduce a single output signal. All inputs aie assumed to be
FIGURE 85.20 Thiee-bit maximal-length LFSR.
2000 by CRC Press LLC
connected to scannable ip-ops (i.e., pseudo-inputs) oi to piimaiy input pins of the component such that
all inputs aie 100% contiollable eithei by contiolling the values in the ip-ops oi the piimaiy input pins. All
ip-ops aie assumed to be scannable and aie aiianged into a single stan a| such that the logic cones have
n oi fewei inputs all of which lie within | consecutive bits along the scan path. Outputs fiom the individual
logic cones connect (not shown heie) to the inputs of ip-ops and/oi piimaiy output pins. Thus, all logic
cone outputs aie also 100% obseivable. Now, assume that the seiial output fiom the LFSR shown in Fig. 85.20
is connected as the scan-in" input to the scan-path iegistei shown in Fig. 85.21. In this case any tonsetue
3-bit paitition of the scan-path iegistei will go thiough the same state sequence as the LFSR itself, delayed fiom
it by the numbei of ip-ops between that paitition and the output bit of the LFSR. Foi example, the thiid
logic cone that has inputs fiom ip-ops 4, 5, and 6 will see all input peimutations except the all-zeios case
which can be applied sepaiately as a special case. On the othei hand, the fist logic cone, with inputs fiom ip-
ops 1, 2, and 4, will not ieceive all possible nonzeio peimutations of thiee input vaiiables. This is because
the fist logic cone ieceives its thiee inputs fiom thiee nontonsetue positions of the scan-path iegistei. In this
case only input peimutations that have even paiity acioss positions 1, 2, and 4 will be ieceived by the fist logic
cone. Fuitheimoie, the fouith logic cone that also ieceives inputs fiom thiee nonconsecutive bit positions
which aie 4 bits apait will ieceive all 3-bit nonzeio input peimutations. Analysis of which set of input
peimutations may be geneiated acioss nonconsecutive n bits of a scan-path iegistei which ieceives the outputs
fiom an mth degiee (m n) LFSR is based on |near JeenJente and is outside the scope of this section. Howevei,
the pioblem may also be appioached statistically by choosing the degiee of the LFSR to be highei than n but
smallei than | which is the laigest span of inputs to any logic cone. Foi example, in Fig. 85.21 the degiee of
the LFSR may be chosen as 4. In this case, the piobability that a logic cone which has 4 oi fewei inputs sepaiated
by | bits (heie, | 5) may be calculated Lempel and Cohn, 1985]. It should be noted that a logic cone may
be tested in full even when it has not ieceived all 2n input peimutations.
BIST also iequiies ability to captuie the test iesults without the need foi an exteinal testei. This is often
achieved by using a mu|-nu sgnaure regser (MISR) to captuie individual test iesults and compiess these
into an oveiall value called the test sgnaure. Figuie 85.22 shows a sample signatuie iegistei that can compiess
test iesults captuied fiom foui sepaiate outputs into a single 4-bit signatuie. Piovided that the test ciicuit has
deteiministic behavioi, a signatuie iegistei can be staited in a given staiting state, and its fnal value may be
compaied to a known good signatuie to deteimine pass/fail status. Howevei, compiessing test iesults into a
single oveiall signatuie may pievent piopei fault detection if multiple eiioneous outputs (which may iesult
FIGURE 85.21 Oveilapping logic cones connected to a common scan path.
FIGURE 85.22 A foui-bit paiallel-input signatuie iegistei.
2000 by CRC Press LLC
fiom the same fault being detected on multiple test vectois) causes the fnal test signatuie to be coiiect even
though inteiim signatuies weie wiong. The piobability that a faulty ciicuit signatuie will be the same as the
good ciicuit signatuie is known as aliasing piobability. It can be shown that if the test length is suffciently
long, aliasing piobability diminishes towaid 2

, wheie is the numbei of bits of the signatuie iegistei Deivi-

soglu, 1985].
The two constiucts of LFSR and the MISR can be meiged into a single multipuipose iegistei in a |u|-n
|ogt ||ot| o|seraon (BILBO) appioach Konemann et al., 1979] wheie each iegistei can have multiple modes
of opeiation including the LFSR mode, MISR mode, SCAN mode, and NORMAL mode. In this case an on-
chip test-contiol ciicuit may be used to contiol the modes of opeiation of the BILBO iegisteis so that, in tuin,
each iegistei is used as a test pattein geneiatoi oi signatuie iegistei to test a digital component. Figuie 85.23
illustiates how to use the BILBO scheme in a stepwise fashion to test a laige digital ciicuit.
Path-De!ay Testing
Path-delay testing is aimed at testing whethei a given component/system opeiates at a specifed peifoimance
level that is often measuied as the maximum system clock fiequency. Foi example, the lowei bound foi the
maximum clock fiequency which a miciopiocessoi IC is specifed that it can ieach needs to be veiifed. Howevei,
due to the veiy laige numbei of diffeient opeiations that a miciopiocessoi can peifoim it is not piactical to
veiify coiiect behavioi of such a component opeiating at maximum clock fiequency foi eveiy possible single
opeiation oi sequence of opeiations that it is designed to peifoim. On the othei hand, it may be possible to
examine the stiuctuie of the design to discovei its |ogt a|s and veiify that signals can be piopagated along
FIGURE 85.23 Using BILBO technique to paitition and test a laige ciicuit. (a) Testing combinatoiial ciicuit C
1
. (b) Testing
combinatoiial ciicuit C
2
.
2000 by CRC Press LLC
these paths within a specifed piopagational delay time between the initiation of a signal tiansition at the
beginning of the path and the aiiival of the fnal values at the end of that path. This is called a|-Je|ay testing.
A modein IC component with typical complexity would contain many hundieds of thousands of logic paths,
so that it becomes impiactical to test all of them foi at-speed opeiation. All synt|ronous digital ciicuits aie
designed so that theie is a fxed clock peiiod iesulting fiom the use-constant fiequency clock signals to time
theii opeiation. Obviously, the clock peiiod constitutes an uppei bound foi the piopagational delay thiough
any logic path, since otheiwise clock pulses may aiiive at the ip-ops while theii data input signals may still
be tiansitioning. On the othei hand, piopagational delay thiough some logic paths may be veiy close to this
uppei bound (i.e., clock peiiod) value wheieas otheis may have moie slack in them. It is theiefoie impoitant
to identify the trta| paths and peifoim path-delay testing on these. Hence path-delay testing can be bioken
into the two phases of ciitical-path selection and path-delay test pattein geneiation.
Seveial diffeient appioaches can be used in identifying the ciitical paths, including:
1. Select suffciently laige numbei of paths selected at iandom fiom a list of all logic paths.
2. Calculate woist-case timing foi all logic paths and select a ceitain peicentage of the slowest paths.
3. Fiist identify ceitain key nodes and then select paths that pass thiough those nodes using eithei of the
two appioaches listed in (1) and (2) above.
The moie challenging pioblem is to geneiate the test patteins to veiify that none of the signal piopagations
along a given logic path iequiie longei than the clock-peiiod time to complete. A path-delay test pattein is a
paii of patteins that geneiates the desiied signal tiansition(s) and piovides the sensitization of the signal paths
wheieby the geneiated tiansition(s) is (aie) sensitized thiough the combinational ciicuit to the input of a ip-
op wheie it will be captuied when the system clock is applied. Foi example, Fig. 85.24 shows a combinational
ciicuit and identifes a specifc signal path foi which the path delay is to be measuied. To deteimine the
appiopiiate path-delay test patteins, a dummy AND gate is fist added to the ciicuit as shown. An input to the
AND gate is deiived fiom the output of the combinational ciicuit thiough which the input signal tiansition is
to be piopagated. This signal is used in its tiue oi complemented foim depending upon whethei the fnal value
of the signal tiansition is a logic 1 oi logic 0, iespectively. Othei inputs to the dummy AND gate come fiom
all iemaining inputs of gates thiough which the desiied signal tiansitions must ow. If the desiied signal
tiansition is owing thiough an AND oi NAND gate, the iemaining inputs of these gates aie also fed to the
inputs of the dummy AND gate, wheieas if the desiied signal tiansitions ow thiough OR oi NOR gates, theii
iemaining inputs aie inveited and then connected to the inputs of the dummy AND gate. The dummy AND
gate is not actually implemented as pait of the combinational logic but iathei acts as a convenient place to
FIGURE 85.24 Ciicuit example to illustiate path-delay test pattein geneiation (all ip-ops aie clocked using a common
clock signal that has not been shown).
2000 by CRC Press LLC
collect all the necessaiy conditions foi sensitizing the tiansitions. Foi example, in the example given above the
fist pattein iequiies input ip-ops , B, and C all to be set to the logic 1 value in oidei to sensitize a low-o-
|g| tiansition at the D input, wheieas the second test pattein iequiies , B, and C all to iemain at logic 1
while D is changed fiom logic 0 to the logic 1 value. This way the tiansitions cieated on input D will tiavel
thiough the identifed signal path to ieach the destination ip-op Z.
Path-delay test patteins become much easiei to geneiate and also apply to a ciicuit if the ciicuit is designed
using scannable ip-ops that aie additionally capable of stoiing two aibitiaiily selected values in them. This
can be done in such a fashion that the initial value available at the ip-op output will be ieplaced by the
second value when a fist clock pulse is applied, and the ip-op will ieveit to its noimal mode of opeiation
befoie the second clock pulse is applied. This way the paii of test patteins that foim a path-delay test aie fist
loaded into the ip-ops (using scan) and then two clock pulses aie applied at speed. The fnal iesult captuied
by the second clock pulse is then scanned out and examined to deteimine pass/fail status. It is also possible to
get an actual measuiement of the path delays by iepeating the same test ovei and ovei again while systematically
ieducing the time distance between the two clock pulses to deteimine the minimum sepaiation of the two
clock pulses iequiied foi piopei opeiation.
Figuie 85.25 shows a modifed LSSD latch design Malaiya and Naiayanaswamy, 1983] that can be used to
enable path-delay testing as desciibed above. Using this design, it is possible to load any two aibitiaiy test
vectois to the combinational ciicuit in iapid succession. Fiist, test vectoi Q
1
, Q
2
,.,Q
n
would be scanned into
the L1 latches outputs by using clocks C
3
and C
2
. Next, the test vectoi would be moved into the L2 latches by
applying a single C clock. This way the ip-op outputs would be set to theii initial values defned by Q
1
,
Q
2
,.,Q
n
. Following this, the second test vectoi Y
1
, Y
2
,.,Y
n
would be scanned into the L1 latches using clock
signals C
3
and C
2
. Now applying the C clock causes the fist test vectoi (Q

) to be ieplaced by the second test

vectoi (Y

), and if the C
1
clock is applied next, the iesponse of the combinational ciicuit will be captuied in
the L1 latches. This way, the minimum delay between the clock signals C and C
1
that is necessaiy to allow the
signals to piopagate thiough the combinational ciicuit can be deteimined. Othei ip-op designs with built-
in featuies to suppoit Jou||e-sro|e testing aie also possible Deivisoglu and Stong, 1991].
A diffeient and moie diffcult-to-use appioach foi geneiating test patteins foi path-delay measuiement is
to peifoim scan-in to load the inteinal ip-ops with a special pattein that piioi ciicuit analysis will have
deteimined will be tiansfoimed into the actually intended test pattein when the fist functional clock pulse is
FIGURE 85.25 Using a thiee-latch ip-op design to enable path-delay testing.
2000 by CRC Press LLC
applied. The ciicuit analysis iequiied to use this appioach amounts to peifoiming simulation in ieveise time
ow to deteimine what state the device undei test should be placed in (using scan) so that its next state
coiiesponds to the desiied test pattein.
Future lur Design lur Test
Piesent-day tiends foi stiiving to achieve shoitei time to maiket while at the same time meeting competitive
cost demands aie going to continue into the foieseeable futuie. Design foi testability is one of seveial aieas
that manufactuieis fiom IC components to complete systems aie paying incieased emphasis to in oidei to
meet theii pioduct goals. Twenty yeais ago some pioduct manageis consideied testing as being necessaiy to
weed out the bad fiom the good but did not considei DFT to be adding value to a pioduct. Howevei, since
testing is essential, the value of DFT is seen in ieducing the cost of an essential item. Hence DFT adds value
to a pioduct at least by an amount equal to the savings in test costs that it biings about. Fuitheimoie, DFT
impioves time to maiket by making it possible to identify initial pioduction pioblems at an eailiei point in
time. Foi example, initial pioductions of high-peifoimance ASIC components may contain aws that pievent
theii at-speed opeiation undei ceitain ciicumstances. If these aws aie not discoveied in a timely mannei, they
may tuin into showstoppei" issues causing seiious delays in ievenue shipments of pioducts. Wheieas no
guaianteed" solutions exist to pievent and/oi fnd a solution foi all types of pioblems, design foi testability
is a iapidly matuiing feld of digital design.
Dehning Terms
Boundary scan: A technique foi applying scan design concepts to contiol/obseive values of signal pins of IC
components by pioviding a dedicated boundaiy-scan iegistei cell foi each signal I/O pin.
Built-in self-test (BIST): Any technique foi applying piestoied oi ieal-time-geneiated test cases to a subcii-
cuit, IC component, oi system and computing an oveiall pass/fail signatuie without iequiiing exteinal
test equipment.
Path-delay testing: Any one of seveial possible techniques to veiify that signal tiansitions cieated by one
clock event will tiavel thiough a paiticulai logic/path in a subciicuit, IC component, oi system and will
ieach theii fnal steady-state values befoie a subsequent clock event.
Pseudo-random testing: A technique that uses a lineai feedback shift iegistei (LFSR) oi similai stiuctuie to
geneiate binaiy test patteins with statistical distiibution of values (0 and 1) acioss the bits; these patteins
aie geneiated without consideiing the implementation stiuctuie of the ciicuit to which they will be
applied.
Scan design: A technique wheieby stoiage elements (i.e., ip-ops) in an IC aie connected in seiies to foim
a shift-iegistei stiuctuie that can be enteied into a test mode to load/unload data values to/fiom the
individual ip-ops.
Re!ated Tupic
23.2 Testing
Relerences
M. Abiamovici, M. A. Bieuei, and A. D. Fiiedman, Dga| Sysems Tesng anJ Tesa||e Desgn, Rockville, Md.:
Computei Science Piess, 1990.
Advanced Micio Devices Inc. AMDI], Am29C818 CMOS Pipeline Registei with SSR Diagnostics," pioduct
specifcation, Bus Inteiface Pioducts Data Book, 1987, pp. 47-55.
H. Ando, Testing VLSI with iandom access scan," in digest of papeis, COMPCON, Febiuaiy 1980, pp. 50-52.
P. H. Baidell and W. H. McAnney, Paiallel pseudoiandom test sequences foi built-in test," in Pioc. Inteinational
Test Confeience, Octobei 1984, pp. 302-308.
P. H. Baidell, W. H. McAnney, and J. Savii, Bu|-In Tes [or VLSI. PseuJoranJom Tet|nques, New Yoik: Wiley,
1978.
2000 by CRC Press LLC
Z. Baizilai, D. Coppeismith, and A. L. Rosenbeig, Exhaustive geneiation of bit patteins with applications to
VLSI self-testing," IEEE Trans. on Comuers, vol. C-32, no. 2, pp. 190-194, Febiuaiy 1985.
M. A. Bieuei and A. D. Fiiedman, Dagnoss anJ Re|a||e Desgn o[ Dga| Sysems, Rockville, Md.: Computei
Science Piess, 1976, pp. 139-146, 156-160.
B. I. Deivisoglu, VLSI self-testing using exhaustive bit patteins," in Pioc. IEEE Inteinational Confeience on
Computei Design, Octobei 1985, pp. 558-561.
B. I. Deivisoglu and G. E. Stong, Design foi testability: Using scanpath techniques foi path-delay test and
measuiement," in Pioc. Inteinational Test Confeience, Octobei 1991, pp. 364-374.
E. B. Eichelbeigei and T. W. Williams, A logic design stiuctuie foi LSI testability," Journa| o[ Desgn uomaon
anJ Fau|-To|eran Comung, vol. 2, no. 2, pp. 165-178, 1978.
S. Funatsu, N. Wakatsuki, and T. Aiima, Test geneiation systems in Japan," in Pioc. 12th Design Automation
Symposium, June 1975, pp. 114-122.
T. Gheewala, CiossCheck: A cell based VLSI testability solution," in Pioc. 26th Design Automation Confeience,
1989, pp. 706-709.
IEEE Standaid Test Access Poit and Boundaiy-Scan Aichitectuie," IEEE Std. 1149.1-1990, May 1990.
B. Konemann, J. Mucha, and G. Zwiehoff, Built-in logic block obseivation technique," in digest of papeis,
Inteinational Test Confeience, Octobei 1979, pp. 37-41.
A. Lempel and M. Cohn, Design of univeisal test sequences foi VLSI," IEEE Trans. on In[ormaon T|eory, vol.
IT-31, no. 1, pp. 10-17, 1985.
Y. K. Malaiya and R. Naiayanaswamy, Testing foi timing faults in synchionous sequential integiated ciicuits,"
in Pioc. Inteinational Test Confeience, 1983, pp. 560-571.
E. J. McCluskey, Veiifcation testing. A pseudoexhaustive test technique," IEEE Trans. on Comuers, vol. C-33,
no. 6, pp. 541-546, June 1984.
K. P. Paikei, Inegrang Desgn anJ Tes, New Yoik: IEEE Computei Society Piess, 1987.
J. H. Stewait, Futuie testing of laige LSI ciicuit caids," in Pioc. Semiconductoi Test Symposium, Cheiiy Hill,
N.J., Octobei 1977, pp. 6-15.
Further Inlurmatiun
An excellent tieatment of design foi testability topics is found in Abiamovici et al. 1990]. Also, Bieuei and
Fiiedman 1976] piovide a veiy good tieatment of pseudo-iandom test topics.
C. M. Maundei and R. E. Tulloss (T|e Tes ttess Por anJ BounJary-Stan rt|eture, IEEE Computei
Society Piess Tutoiial, 1990) piovide a usei`s guide foi boundaiy-scan and the IEEE 1149.1 Standaid.
B. I. Deivisoglu (Using Scan Technology foi Debug and Diagnostics in a Woikstation Enviionment," in
Pioc. Inteinational Test Confeience, 1988, pp. 976-986) piovides a veiy good example of applying DFT
techniques all the way fiom the IC component level to the system level. Also, B. I. Deivisoglu (Scan-Path
Aichitectuie foi Pseudoiandom Testing," IEEE Desgn c Tes o[ Comuers, vol. 6, no. 4, pp. 32-48, August
1989) desciibes using pseudo-iandom testing at the system level. Similaily, P. H. Baidell and M. J. Lapointe
(Pioduction Expeiience with Built-in Self-Test in the IBM ES/9000 System," in Pioc. Inteinational Test
Confeience, Octobei 1991, pp. 28-36) desciibe application of BIST foi testing a commeicial pioduct at the
system level.