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Chip Multicore Processors - Tutorial 2: 2.1: Frequency and Voltage Scaling, Amdahl's Law

The document summarizes a tutorial on chip multicore processors that discusses: 1) Estimating power dissipation and density for a 2GHz single core processor using frequency and voltage scaling equations. 2) Calculating how power would change with 4 cores running at a lower voltage and frequency. 3) Re-doing the calculations to use the minimum required voltage of 0.9V. 4) Comparing the power of a lower power 0.9GHz, 4.5mm^2 core to the original designs. 5) Applying the core configurations and Amdahl's Law to optimize for a multimedia application with 14.3% sequential work.

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Bobby Beaman
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51 views

Chip Multicore Processors - Tutorial 2: 2.1: Frequency and Voltage Scaling, Amdahl's Law

The document summarizes a tutorial on chip multicore processors that discusses: 1) Estimating power dissipation and density for a 2GHz single core processor using frequency and voltage scaling equations. 2) Calculating how power would change with 4 cores running at a lower voltage and frequency. 3) Re-doing the calculations to use the minimum required voltage of 0.9V. 4) Comparing the power of a lower power 0.9GHz, 4.5mm^2 core to the original designs. 5) Applying the core configurations and Amdahl's Law to optimize for a multimedia application with 14.3% sequential work.

Uploaded by

Bobby Beaman
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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MUNCHEN TECHNISCHE UNIVERSITAT Lehrstuhl f ur Integrierte Systeme

Chip Multicore Processors Tutorial 2


April 24, 2013

2.1: Frequency and Voltage Scaling, Amdahls Law


After your graduation you get hired by a processor manufacturer, that does not produce multicore processors so far. On your rst working day your task is to estimate the potentials of their existing implementation of a processor core in multicore processors. The ag ship of the company is a 2 GHz processor CPU0 that include many performance optimization techniques. It is a superscalar processor that in average nishes three instructions per clock cycle (IPC). The process technology of the processor has a threshold voltage of Vth = 0, 3 V and the processor is operated at Vdd = 1, 05 V. The implementation has an area of 7 mm2 . a) You remember your knowledge of the lecture Chip Multicore Processors. You try to estimate the power dissipation and the power density. Deep in your brain you recover that the dynamic power dissipation can be expressed as
2 Pdyn = Cf Vdd

(1)

A colleague suggests to combine and C to a processor implementation-dependent coecient . For the given processor 0 = 8, 6 104 W/(MHzV2 ) applies. What is the power dissipation and power density? How many instructions can be executed per second? b) You remember a simple estimation from the lecture, that describes how you can scale the supply voltage and frequency to save power. You therefore plan with four processor cores and simplify by assuming the software can be perfectly parallelized. How does the power change? c) Your colleague is proud of your math skills, but reminds you the processor cannot run with the supply voltage. Instead a miminal voltage of 0, 9 V is required. At this voltage you will get something around maximum 1, 4 GHz. Redo you calculations. d) After that you need a coee. In the kitchen you meet a guy from another working group. They work on a power-optimized version of the processor. After a few minutes you nd a mail containing their specication: Vdd = 0, 9 V, f = 800 MHz with a reduced area of 4.5 mm2 . You ask for you new invented value of this implementation and your colleague coarsely estimates it as ab zu 1 = 7, 71 104 W/(MHzV2 ). Calculate the power for this processor variant. e) These calculations start to become fun to you. What is still missing is a real world example. After some phone calls to systems and software-guys you receive data regarding a multimedia application of a custones, which executes 8, 4 109 instructions per second on the processor. Lucky you, a colleague already analyzed the source code and did some proling. He found 14,3% of the application are sequential. You shortly discuss the application and come to the conclusion the remaining parallel share can be executed on the four processor cores. Which of

2 above congurations suits the application? Calculate the average utilization of the processor cores. f) You rethink the whole setup. It might be worth running the three cores that do not run the sequential part with a slower clock frequency. The sequential parts needs to be run faster then. Find a system of the available cores that matches these conditions. After a long rst working day you feel satised and go home.

2.2: Amdahls Law in the Multicore Era


Please read the article Amdahls Law in the Multicore Era of Mark D. Hill und Michael R. Marty as published in Computer of IEEE. How would you summarize the essential points of the article? What characterizes symmetric and asymmetric multicore processors? What are Dynamic Multicore Chips? According to you, what are important factors that are not considered neither by task 2.1 nor the article?

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