Institute for Integrated Systems Technische Universitt Mnchen Prof. Dr. sc.techn.

Andreas Herkersdorf

Final Exam System on Chip Solutions in Networking SS 2010

Munich, August 2, 2010 Room: N1070 and N1090 Time: 09:00 I hereby confirm that I have been informed prior to begin of the examination that I have to notify the examination supervisors immediately, if sudden illness occurs during the examination. This will be noted in the examination protocol. An application for exam withdrawal has to be filed immediately at the board of examiners being in charge. A medical certificate from one of the physicians acknowledged by the Technische Universitt !nchen issued on the same day as the examination must be forwarded without delay. In case the examination is regularly completed despite of illness, a subsequent withdrawal due to illness cannot be accepted.

.. Name

Matriculation #

.. ignature Examination Time: 75 minutes

Room/ eat

At !irst, "lease !ill in the title "age #ith $our name, matriculation num%er and the num%er o! $our seat. &o not !orget to sign the e'am( )! $ou hand in an$ e'tra sheets o! "a"er, the$ must also contain $our name and matriculation num%er. *e #ill chec+ the student )& and "ass"ort during the e'am. The num%ers in "arentheses are indicati,e !or the num%er o! credits $ou can earn !or a correct ans#er o! this -uestion. The ma'imum num%er o! credits to %e earned is 7.. u%/ -uestions #hich ma$ %e ans#ered inde"endentl$ o! other "arts are mar+ed #ith an asteris+ 012. 3lease note that in multi"le/choice -uestions !alse ans#ers lead to negati,e credits. No materials allo#ed in the e'am e'ce"t: "en, non/"rogramma%le "oc+et calculator, one sheet A4 #ith $our "ersonal notes.

Good Luck!

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1) Right or wrong? Remark: correct answer +1, wrong answer 1, no answer ! points, min.: ! True &ata transmission in onet6 &7 ring net#or+s is %it serial e,en at rates o! 40 89it6s. 9ranch "rediction is used in "i"elined "rocessors to a""roach the "ro%lem o! data ha;ards. onet6 &7 !rames ha,e a constant o,erhead to "a$load ratio !or all hierarch$ le,els. 7ead/o!/line %loc+ing usuall$ is a "ro%lem o! shared out"ut/%u!!ered s#itches. Thermal con,ection is t$"icall$ dominating the thermal resistance in "rocessor cooling solutions. A t$"ical net#or+ "rocessor design com%ines <3= resources #ith s"eci!ic hard#are to achie,e the "er!ormance re-uirements o! the a""lications. ATM idle cells are mi'ed into the "a$load stream o! &7 !rames to ease the cloc+ reco,er$. <3)Mem can ha,e a huge in!luence on the total <3) o! a : : : :

!) 5alse

: :

micro"rocessor architecture.

") #oes the $%& o' a (i(e)ined (rocessor de(end on the (i(e)ine*s de(th? Ex()ain +our answer! ,) >es 012, %ecause higher "i"eline de"th leads to more stalling c$cles 012 in case o! control ha;ards and data ha;ards 012

,) -ow does mu)tithreading in micro(rocessors increase their (er'ormance? Ex()ain the di''erence .etween hardware and so'tware mu)tithreading and gi/e one ad/antage 'or each t+(e! 5) Multithreading uses idle times o! a "rocessor that ma$ origin !rom memor$ accesses to e'ecute other tas+s. 012 7ard#are threading: multi"le register %an+s 012, !ast conte't s#itches 012

o!t#are threading: registers stored in cache 012, lo#er hard#are com"le'it$ 012

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0) 1T2 3witch $onsider the design o' the 'o))owing !x! (ort 1T2 ce)) switch:
5rom TM4 linecards #)? )n"ut Eueue #)nt To TM4 linecards

"4)

)n"ut Eueue

)n"ut Eueue

The in(uts and out(uts o' the switch are connected to )inecards that each terminate and dri/e one 3T250 3#- )ink6 a) 7 -ow is this architecture ca))ed? Name the (ro.)em o' this switch architecture and ex()ain this (ro.)em? ,)

)n"ut %u!!ered s#itch 012 7ead o! line %loc+ing 012: 3ac+ets in the -ueue ha,e to #ait %ehind a "ac+et that cannot %e s#itched, although their out"uts are !ree. 012

.) 7 3ketch the 'rame 'ormat o' an 3T250 3#- 'rame and )a.e) it with its characteristic /a)ues6 $a)cu)ate the maximum data rate o' 1T2 ce))s carried inside a 3T250 'rame! 5) Rectangle #ith !ields 0?AM, 03?7,2 3a$laod2022@&imensions6Time 022 3a$load rate: 4'2.0'9'A %it 6 12BCsDB99 M%it6s 012

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c) 7 8e'ore the 1T2 ce))s )ea/e the )ine cards the+ are extended with a switch s(eci'ic header o' 11 8+tes6 1ssume that in a/erage "9 : o' the 1T2 ce))s arri/ing at the 3#- 'ramer are id)e ce))s6 #eri/e the tota) maximum and tota) a/erage incoming data rate that has to .e hand)ed .+ the 1T2 switch! 5) "int: If you could not sol#e b$ assume a payload data rate of %&' cells for an (&' ) frame of *!! '+it,s.

Total ma'imum rate Rma' D B99 M9it6s 1 .4 6 BFD 72F M9it6s 022 Rma',tot D B99 M9it6s 1 A 0"orts2 1.4 6 BFD B.79 89it6s 012

Total a,erage rate: )dle cells are remo,ed in the !ramer: Ra,g D Rma' 1 0.A D B7A M9it6s 012 Total a,erage in"ut rate to %e s#itched Ra,g,tot D B7A M9it6s 1 A 0"orts2 D 4..F 8%it6s 012

d) 7 Gi/en is the norma)i;ed de)a+ 5 )oad gra(h 'or the switch architecture used in our 1T2 switch6 <ou)d it .e a.)e to hand)e the a/erage incoming data tra''ic= i' the through(ut o' the switching e)ement itse)' was dimensioned to hand)e the maximum tota) incoming data rate? >usti'+ +our answer! ") No, it cannot handle the a,erage data rate #hich is A0 G o! the ma'imum total incoming rate, since the ma'imum through"ut o! this s#itch architecture is .0G o! the theoretical through"ut 0B.79 89it6s2. 022

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e) Now= +ou want to achie/e a norma)i;ed de)a+ o' " 'or 1T2 ce))s at the a/erage tota) in(ut rate6 8+ how man+ (ercent wou)d +ou ha/e to o/er(ro/ision the through(ut o' the data (ath 'rom the read side o' the in(ut ?ueues o/er the switch to the out(uts? 0) "int: If you could not sol#e c$ assume total a#erage input rate of ).- .+it,s and a total maximum input rate of * .+it,s.

&esigned theoretical through"ut ' 40G D 4..F 89it6s 0A,erage total data rate2 022 &esigned theoretical through"ut D 11.. 89it6s 012 ?,er"ro,ision !actor D 011.. 89it6s H B.79 8%it6s26B.79 89it6s D 100G 012

') 7 Now +ou ha/e to dimension the data (ath widths o' the &@As w&A and interna) data (aths wint6 -ere.+= consider the o/er(ro/isioning= .ut on)+ where necessar+! -ow wide wou)d +ou choose the &@A (aths w&A that connect the switch to the 'ramers? 1)so= determine the B&BA read (ort width and the interna) data (aths wint o' the switch? <idths shou)d .e chosen according to "n6 The c)ock 're?uenc+ o' the &@As is )imited to "99 2-; and that o' the )ogic is )imited to ,99 2-;6 <hat c)ock 're?uencies '&A and 'int do +ou end u( with? 0) "int: If you could not sol#e d$ assume an o#erpro#isioning factor of /01. "int: If you could not sol#e c$ assume total a#erage input rate of ).- .+it,s and a total maximum input rate of * .+it,s.

#)? D Rma' 6 !)?,ma' D 72F M9it6s 6 200M7; D F..1B DI #)? D 4 012 !)? D Rma' 6 #)? D 72F M9it6s 6 4 D 1A0 M7; 012

#int D 11.. 89it6s 6 A 6 !int,ma' D 4.A DI #int D A 012 !int D 11.. 89it6s 6 A 6 #int D 1A1 012

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Bor the rea)i;ation +ou choose a $2A3 (rocess and design )i.raries in which the 1T2 switch re?uires 1 2i))ion gates o' )ogic6 The su(()+ /o)tage 'or the )ogic is 16" C6 1)) in(ut and out(ut (ins o' the chi( are dri/en with "65 C6 g) 7 $a)cu)ate the tota) (ower dissi(ation o' the 1T2 switch6 There'ore= assume an a/erage &@A ca(acitance o' D9 (B and a switching 'actor o' D9: on the )inecard inter'aces6 Each )ine card inter'ace has its own c)ock )ine6

Bor the )ogic assume a (ower consum(tion o' 0n<@ 2-;7gate) at a switching 'actor o' 16 1ccording to simu)ations +ou ex(ect an a/erage switching 'actor o' 96, 'or the )ogic6 D)
"int: if you could not sol#e e$ assume wI,23 - and fI,231/0 '"4. Jine/card inter!ace: onl$ out"uts count 012 N)6?DA ' 04@12D40 3Dal"ha ' ! ' N ' < ' KL 012 D .. ' 1A0 M7; ' 40 ' .0 "5 ' 2.BL KL D 1..2 * 012 3core D 1M gates M 4 n*60M7; gate2 M 1A1 M7; M .0.F D 217 m* 022 Total 3o#er: 3 D 3line @ 3core D 1.AF * 012

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5) $hi( %ackage -eat #issi(ation a) 7 $onsider a chi(*s heat dissi(ation o' " < within the 'o))owing (ackage:

4)

#ie su.strate: t3iE965 mm= F3iE104 <@mG= 13iE199 mmH G)ue: tg)ueE969" mm= Fg)ueE96! <@mG= 1g)ueE199 mmH 1)uminum )id: h1)=1ir E 5 "I/1ir@ m@s)) <@mHG= 1)idE5999 mmH $a)cu)ate the therma) conducti/e resistance Rcond o' the (ackage omitting the )id! Ex()ain wh+ the conducti/e resistance o' the )id can .e neg)ected? 5) "int: 5eglect the thermal resistance of the routing layers and the wires6 RcondDt6NA 012 RsiD 0.000Bm 6 149 *6mO 6 0.0001 mL D 0.0F4 O6* 012 RglueD0.00002 6 0.A *6mO 1 0.0001 mL D 0.2B O6* 012 RtotalD0.2A4 O6* 012 Aluminum has a high thermal conducti,it$ and thus can %e neglected in a serial heat trans"ort chain #ith silicon and glue. 012

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.) 7 The heat trans'er coe''icient 'or the therma) con/ection at the )id gi/en a.o/e is de(endent on the s(eed o' air ')owing o/er the )id6 <hat is the maximum am.ient tem(erature at which the chi( cou)d sti)) .e o(erated without a 'an= i' the tem(erature o' the Junction must not rise a.o/e 199K$? 0) "int: If you could not sol#e h$ assume a total thermal conducti#e resistance of !.7 8,96

Rcon,D16hA 012 !or ,Air D 0: Rtotal D 16hA @ Rcond D 16010 *6OmL 1B000mmL2 @ 0.2A4 O6*D 20.2 O6*

012
RDPT63 DI PTD3R 012 PT D 2 * ' 20.2 O6* D 40.4 O Tma',am%ient D100 Q< H 40.4 ODB9.. Q< 012

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D) Network %rocessor 3+stem "") $onsider the 'o))owing N% architecture with 'our em.edded (rocessors= memor+ su.s+stem and (orts to 'our G.it@s Ethernet (orts6
<3= 287; J1 <ache <3= 287; J1 <ache <3= 287; J1 <ache <3= 287; J1 <ache

&MA

Memctrl. *
ram

Memctrl. D .4 9it

*%us D F2 9it !%us D A00 M7;

*&ram D .4 9it &&R/ &RAM ! mem D 400 M7; . / 0.B

8iga%it Rthernet

RAM 2 ns access time

An arri/a) at the (orts= the (ackets are stored in the ##R53#R12 .+ the #216 The (ackets are then (rocessed and 'orwarded according to the run5to5com()etion mode)6 The (rogram im()ementing this 'unctiona)it+ is 09 k8+tes in si;e and is stored in the 3R126 The 'orwarding takes 059 instructions and the (rocessing re?uires "9 instructions (er (a+)oad data .+te6 &n the 'o))owing we on)+ want to consider (ackets o' the 'o))owing 'ormat: 7eader 3a$load F2 9$te 4. to 1B00 9$te The $%Ls are sing)e5issue (i(e)ined R&3$ cores that run at " G-; and ha/e a sing)e )e/e) o' cache6 The L1 cache consists o' D0 k8 instruction cache and D0 k8 data cache6 The si;e o' cache )ines is D0 8+te in each cache6 a) 7 #eri/e the (acket rates 'or a stream o' on)+ short (ackets &) and a)so 'or a stream o' on)+ )ong &&) (ackets! &n .oth cases= assume that the (ackets arri/e .ack5to5.ack6 ") 0)2 rshortD4 8%it6s 6 7. 9$tes D ..41 M""s 012 0))2 rlongD4 8%it6s 6 1BF2 9$tes D F2. +""s 012

.) 7 3ince the network (rocessor shou)d not dro( an+ (ackets= the (acket (rocessing shou)d .e work conser/ing6 <hat is the maximum time a/ai)a.)e 'or each (rocessor to com()ete the (acket (rocessing in case o' a continuous stream o' minimum si;e (ackets &) and maximum si;e (ackets &&)6 0) 0)2 7. 9$te, total line s"eed 4 8%it6s DI 1B2 ns inter arri,al time 012 DI s"read on 4 <3=s DI .0A ns "er <3= 012 0))2 1BF2 9$te, total line s"eed 4 8%it6s DI F0.4 ns inter arri,al time 012 DI s"read on 4 <3=s DI 12,2B.ns 012

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c) 7 <hat is the o(timum $%&core=o(t that each $%L can achie/e? <3)core,o"t D 1 012

1)

&n the 'o))owing assume that the e''ecti/e $%&core is 160 due to data and contro) ha;ards6 d) 7 #etermine the L1 miss (ena)ties 'or data accesses! 1ssume that the re?uested in'ormation is on)+ a/ai)a.)e a'ter the 'u)) cache )ine has .een )oaded into the cache6 1ssume that +ou wi)) ha/e to wait 'or an additiona) ha)' data cache )ine read .+ another $%L on a/erage6 5)

&ata cache line: .4 9$te D A 1 .4 9its D A &RAM memor$ #ords 012 Trans!er time: . @ 7 1 0.B D 9.B c$cles at 400 M7; 012 9us has hal! #idth, %ut dou%le !re-uenc$ DI 19 c$cles S A00 M7; 012 3enalt$ in <3= c$cles 19 1 2000 6 A00 D 47.B D 4A 012 Additional hal! data cache line read 4A @ 24 D 72 012

e) 7 <h+ does the instruction miss (ena)t+ not ha/e a re)e/ant im(act on the (er'ormance o' the network (rocessor s+stem? ")

A!ter the "rocessing o! the !irst "ac+et, the "rogram is com"letel$ loaded into the instruction cache 012. A!ter#ards, instruction miss rate #ill %e 0 012.

') 7 1ssume that during the 'orwarding and encr+(tion (rocess the res(ecti/e $%L re?uires the who)e (acket 'or the (acket (rocessing6 -ow man+ c+c)es does a $%L sta)) whi)e waiting 'or the data cache 'i))s during the (rocessing o' maximum si;e (acket? ") "int: If you could not sol#e d$ assume a data cache miss penalty of *! cycles6

0)2 <ache misses "er ma' si;e "ac+et: 1BF2 9$te 6 .4 9$te D 2F.9 D 24 cache misses 012 24 1 72 c$cles D 172A <3= c$cles 012

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g) 7 #eri/e the num.er o' $%L instructions that ha/e to .e executed in case o' the maximum si;e (ackets! <hat is the resu)ting e''ecti/e $%& i' +ou consider the sta))s due to the memor+ accesses? 0) "int: %ssume a that a :;< waits for 1-!! cycles for data cache fills during processing of a maximum si4e packet.

5or#arding 4B0 instructions @ encr$"tion 1B00 1 20 instructions D F04B0 instructions 012 F04B0 instructions at <3) D 1.4 D 42.F0 c$cles 012 <3) D 042.F0 c$cles @ 172A c$cles26F04B0 instructions 012 D 1.4. 012

h) $heck whether the $%Ls ha/e enough (er'ormance to 'inish the (acket (rocessing 'or maximum si;e (ackets in the a/ai)a.)e time .udget that +ou ca)cu)ated in .)? ") "int: If you could not sol#e b$ assume a time budget of 1=us for maximum si4e packets6

Time re-uired !or "rocessing: 42.F0 c$cles S 2 87; D 21.Fus 012 I 12.2us a,aila%le %udget 012 The <3=s ha,e not enough "er!ormance.

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