Machine Instructions and Programs

Number, Arithmetic Operations, and Characters

Signed Integer
3 major representations:
Sign-magnitude Ones complement Twos complement

Assumptions:
4-bit machine word 16 different values can be represented Roughly half are positive, half are negative

Sign and Magnitude Representation

-7 -6 -5 -4 -3 -2
1100 1011 1010 1001 1111 1110

+0
0000 0001

+1 +2 +3 +4
+ 0 100 = + 4 1 100 = - 4 -

1101

0010

0011 0100 0101 0110 1000 0111

+5

-1

+6

-0

+7

High order bit is sign: 0 = positive (or zero), 1 = negative Three low order bits is the magnitude: 0 (000) thru 7 (111) Number range for n bits = +/-2n-1 -1 Two representations for 0

Ones Complement Representation

-0 -1 -2 -3 -4 -5
1100 1011 1010 1001 1111 1110

+0
0000 0001

+1 +2 +3 +4
+ 0 100 = + 4 1 011 = - 4 -

1101

0010

0011 0100 0101 0110 1000 0111

+5

-6

+6

-7

+7

Subtraction implemented by addition & 1's complement Still two representations of 0! This causes some problems Some complexities in addition

Twos Complement Representation

-1 -2 -3
like 1's comp except shifted one position clockwise
1111 1110

+0
0000 0001

+1 +2 +3 +4
+ 0 100 = + 4 1 100 = - 4 -

1101

0010

-4 -5 -6

1100 1011 1010 1001

0011 0100 0101 0110 1000 0111

+5

-7

+6

-8

+7

Only one representation for 0 One more negative number than positive number

Binary, Signed-Integer Representations

B b 3 b 2 b1 b 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 Sign and magnitude +7 +6 +5 +4 +3 +2 +1 +0 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 Values represented 1's complement +7 +6 +5 +4 +3 +2 +1 +0 -7 -6 -5 -4 -3 -2 - 1 -0 2's complement + + + + + + + + 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1

Binary, signed-integer representations.

Addition and Subtraction 2s Complement

4 +3 If carry-in to the high order bit = carry-out then ignore carry if carry-in differs from carry-out then overflow 7 0100 0011 0111 -4 + (-3) -7 1100 1101 11001

4 -3 1

0100 1101 10001

-4 +3 -1

1100 0011 1111

Simpler addition scheme makes twos complement the most common choice for integer number systems within digital systems

2s-Complement Add and Subtract Operations

(a) 0010 + 0011 0101 (c) 1011 + 1110 1001 1101 - 1001 0010 - 0100 0110 - 0011 1001 - 1011 1001 - 0001 0010 - 1101 ( + 2) ( + 3) ( + 5) (- 5) (- 2) (- 7) (- 3) (- 7) ( + 2) ( + 4) ( + 6) ( + 3) ( - 7) (- 5) (- 7) ( + 1) ( + 2) ( - 3) (d) (b) 0100 + 1010 1110 0111 + 1101 0100 1101 + 0111 0100 0010 + 1100 1110 0110 + 1101 0011 1001 + 0101 1110 1001 + 1111 1000 0010 + 0011 0101 ( - 2) ( + 4) (- 6) (- 2) ( + 7) ( - 3) ( + 4) (e)

( + 4)

(f)

(g)

( + 3)

(h)

( - 2)

(i)

( - 8)

(j)

( + 5)

2's-complement Add and Subtract operations.

Overflow - Add two positive numbers to get a negative number or two negative numbers to get a positive number

-1 -2 -3 -4 -5 -6 -7 -8
1110 1101 1100 1011 1010 1001 1000 1111

+0
0000 0001 0010 0011 0100 0101 0110 0111

-1 +1 +2 +3 +4 +5 -6 -7 -8 -7 - 2 = +7 -4 -5 -3 -2
1110 1101 1100 1011 1010 1001 1000 1111

+0
0000 0001 0010 0011 0100 0101 0110 0111

+1 +2 +3 +4 +5

+6

+6

+7 5 + 3 = -8

+7

Overflow Conditions
5 3 -8 Overflow 5 2 7 No overflow 0000 0101 0010 0111 0111 0101 0011 1000 -7 -2 7 Overflow -3 -5 -8 1111 1101 1011 11000 1000 1001 1100 10111

No overflow

Overflow when carry-in to the high-order bit does not equal carry out

Sign Extension
Task: Given w-bit signed integer x Convert it to w+k-bit integer with same value Rule: Make k copies of sign bit: X = xw1 ,, xw1 , xw1 , xw2 ,, x0
X
k copies of MSB

Sign Extension Example

short int x = 15213; int ix = (int) x; short int y = -15213; int iy = (int) y;

x ix y iy

Decimal Hex 3B 15213 15213 00 00 C4 C4 -15213 -15213 FF FF C4

Binary 6D 00111011 92 00000000 00000000 00111011 93 11000100 93 11111111 11111111 11000100

01101101 01101101 10010011 10010011

Memory Locations, Addresses, and Operations

Memory Location, Addresses, and Operation

n bits

Memory consists of many millions of storage cells, each of which can store 1 bit. Data is usually accessed in n-bit groups. n is called word length.

first word second word

i th word

last word

Memory words.

Memory Location, Addresses, and Operation

32-bit word length example
32 bits b31 b30 b1 b0

Sign bit: b31= 0 for positive numbers b31= 1 for negative numbers (a) A signed integer

8 bits

8 bits

8 bits

8 bits

ASCII character

ASCII character

ASCII character

ASCII character

(b) Four characters

Memory Location, Addresses, and Operation

To retrieve information from memory, either for one word or one byte (8-bit), addresses for each location are needed. A k-bit address memory has 2k memory locations, namely 0 2k-1, called memory space/ address space. 24-bit memory: 224 = 16,777,216 = 16M (1M=220) 32-bit memory: 232 = 4G (1G=230) 1K(kilo)=210 1T(tera)=240

Memory Location, Addresses, and Operation

It is impractical to assign distinct addresses to individual bit locations in the memory. The most practical assignment is to have successive addresses refer to successive byte locations in the memory byte-addressable memory. Byte locations have addresses 0, 1, 2, If word length is 32 bits, they successive words are located at addresses 0, 4, 8,

Big-Endian: lower byte addresses are used for the most significant bytes of the word

Big-Endian and Little-Endian Assignments

Byte address 0 4 1 5 2 6 3 7 0 4 3 7 Byte address 2 6 1 5 0 4

Little-Endian: opposite ordering. lower byte addresses are used for the less significant bytes of the word
Word address 0 4

k k k k k k k k

k k

2 -4

2 -4

2 -3

2- 2

2 - 1

2 - 4

2- 1

2 - 2

2 -3

2 -4

(a) Big-endian assignment

(b) Little-endian assignment

Figure 2.7. Byte and word addressing.

Memory Location, Addresses, and Operation

Address ordering of bytes Word alignment
Words are said to be aligned in memory if they begin at a byte addr. that is a multiple of the num of bytes in a word.
16-bit word: word addresses: 0, 2, 4,. 32-bit word: word addresses: 0, 4, 8,. 64-bit word: word addresses: 0, 8,16,.

Access numbers, characters, and character strings

Memory Operation
Load (or Read or Fetch)
Copy the content. The memory content doesnt change. Address Load Registers can be used

Store (or Write)

Overwrite the content in memory Address and Data Store Registers can be used

Instruction and Instruction Sequencing

Must-Perform Operations
Data transfers between the memory and the processor registers Arithmetic and logic operations on data Program sequencing and control I/O transfers

Register Transfer Notation

Identify a location by a symbolic name standing for its hardware binary address (LOC, R0,) Contents of a location are denoted by placing square brackets around the name of the location (R1[LOC], R3 [R1]+[R2]) Register Transfer Notation (RTN)

Assembly Language Notation

Represent machine instructions and programs. Move LOC, R1 = R1[LOC] Add R1, R2, R3 = R3 [R1]+[R2]

CPU Organization
Single Accumulator
Result usually goes to the Accumulator Accumulator has to be saved to memory quite often

General Register
Registers hold operands thus reduce memory traffic Register bookkeeping

Stack
Operands and result are always in the stack

Instruction Formats
Three-Address Instructions
ADD ADD ADD ADD R1, R2, R3 R1, R2 M R3 [R1] + [R2] R2 [R1] + [R2] AC AC + [M] TOS [TOS] + [(TOS 1)]

Two-Address Instructions One-Address Instructions Zero-Address Instructions RISC Instructions

Lots of registers. Memory is restricted to Load & Store

Opcode Operand(s) or Address(es)

Instruction Formats
Example: Evaluate X = (A+B) (C+D) Three-Address
1. ADD 2. ADD 3. MUL A, B, R1 C, D, R2 R1, R2, X ; R1 [A] + [B] ; R2 [C] + [D] ; X [R1] [R2]

Instruction Formats
Example: Evaluate X = (A+B) (C+D) Two-Address
1. 2. 3. 4. 5. 6. MOV ADD MOV ADD MUL MOV A, R1 B, R1 C, R2 D, R2 R2, R1 R1, X ; R1 [A] ; R1 [R1] + [B] ; R2 [C] ; R2 [R2] + [D] ; R1 [R1] [R2] ; X [R1]

Instruction Formats
Example: Evaluate X = (A+B) (C+D) One-Address
1. 2. 3. 4. 5. 6. 7. LOAD ADD STORE LOAD ADD MUL STORE A B T C D T X ; AC [A] ; AC [AC] + [B] ; T [AC] ; AC [C] ; AC [AC] + [D] ; AC [AC] [T] ; X [AC]

Instruction Formats
Example: Evaluate X = (A+B) (C+D) Zero-Address
1. 2. 3. 4. 5. 6. 7. 8. PUSH PUSH ADD PUSH PUSH ADD MUL POP A B C D ; TOS [A] ; TOS [B] ; TOS [A] + [B] ; TOS [C] ; TOS [D] ; TOS [C] + [D] ; TOS (C+D)(A+B) ; X [TOS]

Instruction Formats
Example: Evaluate X = (A+B) (C+D) RISC
1. 2. 3. 4. 5. 6. 7. 8. LOAD LOAD LOAD LOAD ADD ADD MUL STORE A, R1 B, R2 C, R3 D, R4 R1, R2, R1 R3, R4, R3 R1, R3, R1 R1, X ; R1 [A] ; R2 [B] ; R3 [C] ; R4 [D] ; R1 [R1] + [R2] ; R3 [R3] + [R4] ; R1 [R1] [R3] ; X [R1]

Using Registers
Registers are faster Shorter instructions
The number of registers is smaller (e.g. 32 registers need 5 bits)

Potential speedup Minimize the frequency with which data is moved back and forth between the memory and processor registers.