Brett Cardena Dr.

Ackland CPE - 690 12/2/13 Design Project: 4-Bit Synchronous Counter For my design project for this semester I laid out a 4-Bit Synchronous Counter using JK Flip-Flops. The design involves approximately 174 transistors forming various gates including 3-input NAND gates, 2-input NAND gates, and Inverters. These gates are then arranged as JK Flip-Flops, with NAND gates and Inverters placed appropriately to achieve the synchronous counter functionality I desired. Overall the software did not

get too much in my way, despite being very clunky to use. Most issues I faced during my layout and simulations were caused by simple mistakes that I made, not any inherent problems with software. The remainder of this paper will be devoted to showing the schematics, layout and simulation of each cell as the project progressed, beginning with the inverter from our LASI tutorial.

1. CMOS Inverter My design involved approximately 10 inverters. As we did this as our tutorial project I will not spend a great amount of time explaining the process of designing and laying it out. On the next page you can see the schematic used, and final layout of my

CMOS inverter, as well as the simulation window from LTSpice that was generated from this layout.

Figure 1 - Below is the transistor-level schematic of a CMOS Inverter. To the right is a LASI circuit layout of the Inverter, and at the bottom of the page is the LTSpice simulation window for the inverter.

2.

2-Input NAND Gate

My counter involved about 25 2-Input NAND Gates, making it the most commonly used gate in the entire layout, therefor it was of the utmost importance that it functioned properly. The gate is a level 2 cell involving just 2 PMOS transistors in parallel connected to Vdd and 2 NMOS transistors in series connected to ground. Below you

can see the transistor-level schematic of the gate, as well as the LASI layout and LTSpice simulation.

Figure 2(a) - Below you can see the transistor level schematic of a 2-Input NAND gate. To the right, is the LASI layout of the gate.

Figure 2(b) - Above you can see the LTSpice simulation of the 2-Input NAND gate. You can see a small dip in output voltage occur when inputs A and B switch simultaneously, and then, as expected, the output goes to 0 when both inputs go high.

3. 3-Input NAND Gate The counter circuit I built used 9 3-Input NAND Gates. Similar to the 2-Input

NAND, the 3-Input NAND is a Level 2 cell that does a simple NAND operation on 3 inputs using 3 PMOS transistors in parallel connected to Vdd and 3 NMOS transistors in series connected to ground. On the next page you can see the transistor-level schematic

of the gate, the LASI layout and the LTSpice simulation waveforms extracted from the design.

Figure 3 - Below you can see the transistor level schematic of a 3-Input NAND gate. To the right is the LASI layout of the gate. At the bottom of the page is the LTSpice simulation waveform. As expected, the only time the output goes low is when all inputs are high.

4. JK Flip-Flop The JK Flip-Flop features two selector inputs, J and K, and a clock input as well as 2 outputs with one output being the inverse of the other. Each Flip-Flop uses 2 Inverters, 6 2-Input NAND Gates and 2 3-Input NAND Gates to accomplish its specified function. To put it simply, the JK Flip-Flop acts as a toggle flip-flop when both J and K are high, defaults to a logical 1 when J is high and K is low, defaults to logical 0 when K is high and J is low, and holds its current value if both J and K are low. In my work designing the Flip-Flop I found that I had a strange behavior where my output would toggle exactly one time after setting both inputs low, before holding its value. After working closely on the problem I determined that this functionality did not interfere with my Synchronous Counters functionality, and felt that it was safe to assume that this is how the Flip-flop is meant to function. Below you will see the Circuit symbol (to be used in my top-level schematic), the gate-level schematic, the LASI layout, and the LTSpice simulation waveform for the JK Flip-Flop.

Figure 4(a) - Above you can see the circuit symbol and gate-level schematic of the JK Flip-Flop.

Figure 4(b) - above is the LASI layout of the JK Flip-Flop

Figure 4(c) - Above you can see the simulation waveform of the JK Flip-Flop. When both inputs are high the output toggles, when J is high the output goes high, when K is high the output goes low, and when both are low the output toggles once then holds its value. 5. 4-Bit Synchronous Counter My top level cell is a 4-bit synchronous counter, consisting of 4 JK Flip-Flops, 2 Inverters, a 2-Input NAND and a 3-Input NAND gate. This circuit outputs a 4 digit binary number, starting at 0, and counts up to 15 before beginning again. This is accomplished by holding the J and K inputs of the first Flip-Flop high, to create a toggle for the lowest bit. The output of this bit is also used to drive the J and K inputs of the next, to create the next highest bit. This process, although modified with NAND gates, is used to create the final 2 bits of the counter. On the next few pages will be the gate-level schematic of the Synchronous Counter, the LASI layout for the counter, and the LTSpice simulation waveforms to show proper operation.

Figure 5(a) - Above is the Gate-Level Schematic of the 4-Bit Synchronous Counter.

Figure 5(b) - (Top) The full LASI layout of the Counter. (Bottom) A detail view of the first 2 Flip Flops.

Figure 5(c) - A detail view of the third Flip-Flop, including both the 2-Input NAND and Inverter pair, and the 3-Input NAND and inverter pair, to each side of it.

Figure 5(d) - A detail view of the fourth and final Flip-Flop including the 4 output wires. I named them in reverse of what I named them on the schematic.

Figure 5(e) - An example of the output of the counter, with all of the output values labeled in decimal form. As expected, every output bit updates simultaneously on each negative clock edge.

6.

Design Rule Check and SPICE Code

Once my layout was completed I took the steps to ensure that my design did not break any of the design rules. Using the LASI Design Rule Checker, I had the software Upon completion of the

double check my design to ensure that there were no violations. check the software found no violations of the design rules.

Figure 6(a) - Proof of completion of Design Rule Check

On the next few pages, you can examine the SPICE file generated by the LASI Circuit Extractor.

Figure 6(b) - A copy of the generated SPICE file. The code continues onto the next page.

7. Simulation and Analysis In this section I will examine how temperature and supply voltage affect the Synchronous Counters operation. I will begin by varying the temperature between -25C, 25C, and 100C, and examining the output waveforms. 7(a). These waveforms can be examined in detail in Figure

When examining the waveforms the only major difference is the effect that the At -25C the initial output is There are also

temperature has on the initial conditions of the system.

0010, whereas it is 0110 and 1110 for 25C and 100C respectively.

very minor changes in the amount of noise affecting the output, but it is almost unnoticeable. We see almost no change in delay times as all the flip-flops are made to

only update on the negative clock edge, giving ample time for the new values to update before the next negative clock edge arrives. I would assume that this is part of the

reason why Synchronous Counters are more useful than Ripple Counters. Finally, I varied the supply voltage driving the device, starting at 2.5V, then to 3.0V and 3.5V. The output waveforms for this can be seen in Figure 7(b). Once again we

see that the initial outputs change with the supply voltage, starting at 1111 at 2.5V, then going to 0110 at 3.0V, and ending at 1011 at 3.5V. We can also see that the amount

of noise effecting the outputs becomes smaller at higher voltages, although the change is negligible. Similar to the varying temperatures, there is almost no change in delay times,

most likely because of the synchronicity of the flip-flops.

Figure 7(a) - These are the simulation waveforms of the counter at: (Top) -25C, (Middle) 25C, (Bottom) 100C.

Figure 7(b) - Output waveforms at varying supply voltages: (Top) 2.5V, (Middle) 3.0V, (Bottom) 3.5V.