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VHDL Ratings: (0)|Views: 1,302|Likes: 8 Published by Punith Gowda M B See More

The state register is represented by Q, which is a 3-bit vector (Q1 , Q 2, Q 3 )and the next state of this register is Qplus. In VHDL, a RO M can be represented by a c onstant one dim ensional array of bit vectors. In this example, a type statement is used to declare type ROM as an arrayof 16 words of 4 bit vectors. A constant declaration specifies the contents of the ROM namedFSM_RO M. The input to the FSM_ROM is Q concatenated with X. Since the inde x of an array m ust be an integer, the vec2int function is called to conve rt Q& X to an integ er. The variable ROMvalue is set equal to the ROM output, and then ROMValue is split into Qplusand Z. The state register Q is updated after the rising edge of the clock. Note: This programuses the user defined library bitlib for converting vector to integer, So this library should becreated before this program is run. Procedure for creating this library is as explained in the presentation on packages and libraries . From the waveform we can see that Q1Q2Q3X ARE 0000 output Qplus is 100 and is Z is 1 .for each positive edge trigger of the clock the Qplus which is the input to D f/f istransferred to Q. .since the first process in the program gets evaluated for change inX or Q this process also gets evaluated as soon as Q changes.. We can verify thewaveform by seeing the state diagram given in figure 7.43 Output waveform for BCD to excess-3 using ROM

Programmable Logic Array A programmable logic array (PLA) performs the same basic function as a ROM. It ist h e m o s t f l e x i b l e d e v i c e i n t h e f a m i l y o f P L D s . T h e i n t e r n a l o r g a n i z a t i o n o f a P L A i s different from that of the ROM. The decoder of the ROM is replaced with an AND array thatreali zes elected product terms of the input vari ables. The AND array is followed by an O R arra y which Ors to gethe r the product term s needed to form the output functions. Both the AND and the OR arrays are programmable giving a lot of flexibility for implementing logicdesign.

Fig 8 Internal Logic Diagram of a PLA Internall y the PLA uses NOR -NOR l ogic but the added i nput and output inverti ng b u f f e r s m a k e i t equivalent to AND-OR logic. Logic gates are formed in the array byc o n n e c t i n g N M O S s w i t c h i n g t r a n s i s t o r s b e t w e e n t h e c o l u m n l i n e a n d r o w l i n e . T h e transistors act as switche s, so if the gate input is a logic zero, the transistor is turned off whereas if the gate input is a logic one, the transistor provides a conducting path to ground.44

Fig 9 PLA with 3 inputs , 5 product terms and 4 outputs The above set of formulas are implemented using NOR-NOR logic of PLA as shownin Fig. 9 by plac ing the NMOS switching transistors whe rever the con nection has to be e s t a b l i s h e d . T h e s a m e s e t o f e q u a t i o n s c a n b e i m p l e m e n t e d u s i n g a n A N D - O R a r r a y equivalent as shown in Fig. 10 on the next page.45F0 = m(0,1,4,6) = AB+AC F1 = m(2,3,4,6,7) = B+ACF2 = m(0,1,2,6) =AB+BCF3 = m(2,3,5,6,7) =AC+B

Fig 10 AND-OR array equivalent of Fig. 9 The contents of a PLA can be specified by a modified truth table as shown in Fig.11.T h e i n p u t s i d e o f t h e t a b l e s p e c i f i e s t h e p r o d u c t t e r m s . T h e s y m b o l s 0 , 1 a n d i n d i c a t e whether a vari able is com plem ented, not com plem ented or not present in the correspondi ng product term . The output side of the table specifies w hich produc t terms appear i n which output function. A 1 or 0 in the output terms indicate whether a given product term is presentor not present in the corresponding output function. fig 11 PLA Table for Fig. 10 The first ro w of the tabl e ind icates that th e term AB is present in out put functions F0 and F2. The second row indicates that AC is present in F0 and F1. This PLA table can bewritten directly using the given set of equations to be realized using PLA logic.Realization of a given function using min number of rows in the PLA46F1 = m(2,3,5,7,8,9,10,11,13,15) .(1)F2 = m(2,3,5,6,7,10,11,14,15) . (2)F3 = m(6,7,8,9,13,14,15) . (3)

Fig 12 Multiple Output Karnaugh Map F1 = BD+BC+AB .(4)F2 = C+ABD .(5)F3 = BC+ABC+ABD .(6)Equations 1,2 and 3 can be reduced to equations 4, 5 and 6 respectively using Karnaughmap as shown in Fig.12.If we implement these reduced equations 4,5 and 6 in a PLA then a total of 8 different product terms (including C) are required. So instead of minimizing each function separately,w e h a v e t o m i n i m i z e t h e t o t a l n u m b e r o f r o w s i n t h e P L A t a b l e . W h e n w e a r e t r y i n g t o design a logic using PLA, the num ber of term s in each equation is not im portant since the size of the PLA does not depend on the number of terms. The term ABC is already presentin function F3. So we can use it in F1 instead of AB by writing AB as AB(C+C) . F1 can be now written asF1 = BD + BC + AB(C+C)= BD + BC + ABC + ABC= BD + BC (1+ A) + ABC= BD + BC + ABC This sim plification of F1 elim inates the need to use a separat e row for the ori ginal term AB present in F1 of equation (4).Since the terms ABD and ABD are needed in F2 and F3 respectively, we can replacethe term BD in F1 with ABD + ABD. This elim inates the need for a ro w to im plem ent theterm BD in PLA. Sim ilarly, since BC and BC are used in F1 an d F3 respectively, w canreplace C in F3 wi th BC + BC. Now the equati ons for F1, F2 and F3 wit h the ab ove sai d changes can be written as :F1 = BD(A+A) + BC + AB(C+C)= ABD + ABD + BC +ABC .(7)47

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