SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SCAS538D OCTOBER 1995 REVISED OCTOBER 2002

D D D D

4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 9.5 ns at 5 V Inputs Are TTL-Voltage Compatible

SN54ACT573 . . . J OR W PACKAGE SN74ACT573 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW)

description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components.

OE 1D 2D 3D 4D 5D 6D 7D 8D GND

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE

SN54ACT573 . . . FK PACKAGE (TOP VIEW)

2D 1D OE VCC 3D 4D 5D 6D 7D

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

1Q 2Q 3Q 4Q 5Q 6Q

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA PDIP N SOIC DW 40 40C to 85C SOP NS SSOP DB TSSOP PW CDIP J 55C to 125C CFP W LCCC FK PACKAGE Tube Tube Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74ACT573N SN74ACT573DW SN74ACT573DWR SN74ACT573NSR SN74ACT573DBR SN74ACT573PWR SNJ54ACT573J SNJ54ACT573W SNJ54ACT573FK TOP-SIDE MARKING SN74ACT573N ACT573 ACT573 AD573 AD573 SNJ54ACT573J SNJ54ACT573W SNJ54ACT573FK

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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8D GND LE 8Q 7Q

SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SCAS538D OCTOBER 1995 REVISED OCTOBER 2002

FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z

logic diagram (positive logic)

1 OE LE 11

C1 1D 2 1D

19 1Q

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through, VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

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SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SCAS538D OCTOBER 1995 REVISED OCTOBER 2002

recommended operating conditions (see Note 3)

SN54ACT573 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 VCC VCC 24 24 8 0 0 MAX 5.5 SN74ACT573 MIN 4.5 2 0.8 VCC VCC 24 24 8 MAX 5.5 UNIT V V V V V mA mA ns/V

TA Operating free-air temperature 55 125 40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = 50 A VOH IOH = 24 mA IOH = 50 mA IOH = 75 mA IOL = 50 A VOL IOL = 24 mA IOL = 50 mA IOL = 75 mA IOZ II ICC ICC VO = VCC or GND VI = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, , Other inputs at GND or VCC VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 55V 5.5 06 0.6 0.25 0.1 4 5 1 80 15 1.5 0.1 0.1 0.36 0.36 0.1 0.1 0.44 0.44 1.65 1.65 2.5 1 40 15 1.5 A A A mA pF MIN 4.4 5.4 3.86 4.86 TA = 25C TYP MAX 4.49 5.49 SN54ACT573 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX SN74ACT573 MIN 4.4 5.4 3.76 4.76 V MAX UNIT

Ci VI = VCC or GND 5V 5 Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw tsu th Pulse duration, LE high Setup time, data before LE Hold time, data after LE 3.5 3 0 SN54ACT573 MIN 5 4.5 1 MAX SN74ACT573 MIN 4 3.5 0 MAX UNIT ns ns ns

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SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SCAS538D OCTOBER 1995 REVISED OCTOBER 2002

switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) D LE TO (OUTPUT) Q Q Q Q MIN 2.5 2.5 3 2.5 2 1.5 2.5 1.5 TA = 25C TYP MAX 6 6 6 5.5 5.5 5.5 6.5 5 10.5 10.5 10.5 9.5 10 9.5 11 8.5 SN54ACT573 MIN 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 MAX 13.5 13.5 13 12 11.5 11 13.5 10.5 SN74ACT573 MIN 2 2 2.5 2 1.5 1.5 1.5 1 MAX 12 12 12 10.5 11 10.5 12.5 9.5 UNIT ns ns ns ns

OE OE

operating characteristics, VCC = 5 V, TA = 25C

PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 25 UNIT pF

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SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SCAS538D OCTOBER 1995 REVISED OCTOBER 2002

PARAMETER MEASUREMENT INFORMATION

2 VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 VCC Open

500

3V Timing Input LOAD CIRCUIT tsu tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) tPZL 3V Input 1.5 V tPLH Output 50% VCC VOLTAGE WAVEFORMS 1.5 V 0V tPHL VOH 50% VCC VOL Output Waveform 1 S1 at 2 VCC (see Note B) tPZH Output Waveform 2 S1 at Open (see Note B) 50% VCC VOLTAGE WAVEFORMS 50% VCC 3V 1.5 V 1.5 V 0V tPLZ VCC VOL + 0.3 V tPHZ VOH 0.3 V VOH 0 V VOL Data Input 1.5 V 1.5 V th 0V 3V 1.5 V 0V VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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PACKAGE OPTION ADDENDUM

www.ti.com

18-Jul-2006

PACKAGING INFORMATION
Orderable Device 5962-87664012A 5962-8766401RA 5962-8766401SA SN74ACT573DBLE SN74ACT573DBR SN74ACT573DBRE4 SN74ACT573DW SN74ACT573DWG4 SN74ACT573DWR SN74ACT573DWRG4 SN74ACT573N SN74ACT573NE4 SN74ACT573NSR SN74ACT573NSRE4 SN74ACT573PW SN74ACT573PWE4 SN74ACT573PWLE SN74ACT573PWR SN74ACT573PWRE4 SNJ54ACT573FK SNJ54ACT573J SNJ54ACT573W
(1)

Status (1) ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Package Type LCCC CDIP CFP SSOP SSOP SSOP SOIC SOIC SOIC SOIC PDIP PDIP SO SO TSSOP TSSOP TSSOP TSSOP TSSOP LCCC CDIP CFP

Package Drawing FK J W DB DB DB DW DW DW DW N N NS NS PW PW PW PW PW FK J W

Pins Package Eco Plan (2) Qty 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 1 1 1 TBD TBD TBD TBD 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

Lead/Ball Finish

MSL Peak Temp (3)

POST-PLATE N / A for Pkg Type A42 SNPB A42 Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU N / A for Pkg Type N / A for Pkg Type Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 20 20 Pb-Free (RoHS) Pb-Free (RoHS)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 70 70 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 1 1 1 TBD TBD TBD

POST-PLATE N / A for Pkg Type A42 SNPB A42 N / A for Pkg Type N / A for Pkg Type

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Jul-2006

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA
MLCC006B OCTOBER 1996

FK (S-CQCC-N**)
28 TERMINAL SHOWN

LEADLESS CERAMIC CHIP CARRIER

18

17

16

15

14

13

12

NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20

A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)

B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)

19 20 21 B SQ 22 A SQ 23 24 25

26

27

28

4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)

0.020 (0,51) 0.010 (0,25)

0.055 (1,40) 0.045 (1,14)

0.045 (1,14) 0.035 (0,89)

0.028 (0,71) 0.022 (0,54) 0.050 (1,27)

0.045 (1,14) 0.035 (0,89)

4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004

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MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001

DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M

PLASTIC SMALL-OUTLINE

0,25 0,09 5,60 5,00 8,20 7,40

Gage Plane 1 A 14 08 0,25 0,95 0,55

Seating Plane 2,00 MAX 0,05 MIN 0,10

PINS ** DIM A MAX

14

16

20

24

28

30

38

6,50

6,50

7,50

8,50

10,50

10,50

12,90

A MIN

5,90

5,90

6,90

7,90

9,90

9,90

12,30 4040065 /E 12/01

NOTES: A. B. C. D.

All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150

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MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999

PW (R-PDSO-G**)
14 PINS SHOWN

PLASTIC SMALL-OUTLINE PACKAGE

0,65 14 8

0,30 0,19

0,10 M

0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0 8 0,75 0,50

Seating Plane 1,20 MAX 0,15 0,05 0,10

PINS ** DIM A MAX

14

16

20

24

28

3,10

5,10

5,10

6,60

7,90

9,80

A MIN

2,90

4,90

4,90

6,40

7,70

9,60

4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153

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