81

CHAPTER 4
DESIGN OF DIRECT DIGITAL FREQUENCY SYNTHESIZER
4.1 PREAMBLE
The ever increasing low cost but high performance telecom and
consumer electronics systems require Data Converters such as ADC & DAC with
customized capabilities in respect of resolution and speed. Static parameters such
as DNL error, INL error, Offset error and Gain error characterizes the low speed
behaviour of Data Converters. On the other hand, dynamic parameters such as
Signal to Noise Ratio (SNR), Spurious Free Dynamic Range (SFDR), Total
Hormonic Distortion (THD), Signal to Noise and Distortion Ratio (SINAD), and
Intermodulation Distortion (IMD) characterize the high speed behaviour of ADC.
The dynamic characterization of the Data Converter is critical in
telecommunication and embedded control applications. It is well known that
Automatic test equipment and Buit-in self test methods are the popular methods
used in industry for dynamic characterisation of Data Converters. In traditional
automated test equipment (ATE) the dynamic characterization of data converters
require spectrally pure and coherent sinusoidal signal (IEEE 1241-2000),
(Jingbo et al 2010). Hence the sinusoidal signal source used has to be tuned for
coherency to avoid spectral leakage during the spectral estimation of the device
under test. Because of such fine tuning requirement, the process becomes very
cumbersome and time consuming.
82
Joseph et al (1996) proposed that the spectral leakage during mixed
signal circuit testing can be reduced by using windowing techniques. A
predefined Hamming and Hanning windowing techniques are chosen to eliminate
the spectral leakage in spectral estimation (Alberto et al 2006). However,
irrespective of windowing, there will always be a compromise in accuracy, in
respect of spectral leakage minimization, frequency and amplitude precision, side
lobe amplitude reduction and main lobe broadening (Daniel et al 2007). In this
Chapter a digitally controlled sinusoidal signal generator is proposed to facilitate
cost effective and accurate dynamic characterization of Data Converters.
4.2 BUILT IN DIRECT DIGITAL FREQUENCY SYNTHESIZER
Avanindra Madisetti et al (1999) proposed a DDFS with an angle-
rotation algorithm which employs pipelining approach for the generation of
sinusoidal signal. The modular architecture provides arbitrary precision by way of
cascading more angle-rotation stages in the data path.
Bellaouar et al (2000) proposed a low-power direct digital frequency
synthesizer (DDFS) architecture. It uses a lookup table for sine and cosine
functions with additional hardware. The computation of the generated sine and
cosine functions is based on the linear interpolation between the sample points. A
DDFS with 60 dBc spectral purity for a 9-bit output is reported.
A Built-in Direct Digital Frequency Synthesizer (DDFS) has been
suggested in IEEE 1241-2000 for the generation of controllable and highly
coherent sinusoidal signal with minimum hardware overhead for testing the ADC.
83
Kroupa et al (2001) proposed a technique that combines direct digital
frequency synthesizer and PLL (phase locked loops) with frequency dividers in
the feedback path. To arrive at even closer channel spacing, the author introduced
the so called Fractional-N frequency synthesizers. A sigma delta modulator is
used as a means of spurious signal reduction
Chua-Chin Wang et al (2002) proposed a direct digital frequency
synthesizer employing a trigonometric quadruple angle method. The method uses
a 3 square multiplier and the spectral purity is shown to be 130 dBc for a 13-bit
output resolution.
Florean et al (2003) proposed a method using a look up table based on
CORDIC algorithm which uses an iterative angle computation with rotation
angles between a/2 and a/2 for the generation of sinusoidal signal. This method
produces 16 bit sine and cosine waveforms with spectral purity of 114 dBc and
having tuning latency of 2 cycles.
Caro (2004) has proposed a direct digital frequency synthesizer based
on optimized polynomial expansion of sine and cosine functions. Polynomial
computation is done by canonical-signed-digit (CSD) hyper folding technique.
This method provides a spectral purity of 80 dBc with an output resolution of 12-
bit.
Usman Hai et al (2005) proposed a compressed look-up table based
DDFS architecture using sine wave symmetry from 0 to a/2 to address the power
issue in wireless communication applications. He has reported that the method
84
possesses a spectral purity of 33 dBc with 16 words look up table having word
size of 9-bit.
Kesoulis et al (2007) proposed a DDFS based on a look-up table, which
performs a functional mapping from phase to amplitude of sinusoidal signal. He
uses a sine phase difference algorithm with a modified amplitude reduction
technique. He observed a spectral purity of 95.11 dBc using 14336-bit memory of
look-up table with 18-bit word size.
Lai Lin-hui et al (2008) proposed a low complex direct digital
frequency synthesizer (DDFS) based on a look-up table. The look-up table for
sine and cosine functions is split into a coarse precision ROM and a fine precision
ROM. The results show that the total size of ROM in this proposed DDFS
architecture is 328 bit and the spectral purity is 63.58 dBc.
Xiaojin Li et al (2009) presented a direct digital frequency synthesizer
(DDFS) using phase to sinusoidal amplitude conversion blocks based on the two
segment fourth-order parabolic approximation. Squarer and constant multipliers
have been proposed for the computation in the DDFS. The method shows that the
resolution is up to 14-bit and the spectral purity of about 90 dBc.
Wan Shuqin et al (2009) presented a Direct digital frequency
synthesizer (DDFS) based on modified CORDIC algorithm with reduced
hardware and reduced iteration clocks. The first rotation is implemented by using
a CORDIC realized in pipeline and carry-save arithmetic. The directions of the
CORDIC rotations are computed in parallel by using a look-up table, for the first
85
rotation. The method shows a spectral purity of 64.22 dBc with 14-bit word
length.
An equi-section division method utilizing the symmetry property and
amplitude approximation of a sinusoidal waveform to design a direct digital
frequency synthesizer (DDFS) is proposed. The sinusoidal phase of a one quarter
period is divided into equi-sections by Shiann-Shiun Jeng (2010). The error
between each line segment value and the sinusoidal amplitude value is stored in a
look-up table to reconstruct the actual sinusoidal waveform. The upper/lower
bound of the maximum error value stored in another table is derived to determine
the minimum required memory and word length with respect to the bit number of
the equi-sections. The method shows the spectral purity of 52.168-dBc with
14- bits word length.
Yao-Hua Chen et al (2010) proposed a 8
th
order even polynomial
approximation of a cosine function with square circuits for realizing DDFS with
reduced chip size and minimal spurious free dynamic range (SFDR).The method
has a spurious free dynamic range (SFDR) of 95 dBc for 13-bit resolution.
4.3 TRADATIONAL DDFS ARCHITECTURE
DDFS is a fine resolution sinusoidal waveform generator which can
generate signals with stable performance, in terms of amplitude, phase and
frequency. DDFS implementation mainly relies upon integer arithmetic, allowing
implementation on any hardware platform. The traditional DDFS architecture is
shown in Figure 4.1. It consists of a phase accumulator, a phase to amplitude
converter and a digital-to-analog converter (DAC). The phase accumulator is a
digital circuitry consisting of an adder with a feedback and an input as frequency
86
control word (FCW). The phase accumulator receives an input called FCW which
is linearly incremented in accordance with clock. The output of phase
accumulator is fed into the phase to amplitude converter which is a sine/cosine
generator that converts digital phase values into its equivalent digital sinusoidal
amplitude. Most of the methods use the ROM based look-up table for sine/cosine
generation. The linearly increasing output of the phase accumulator provides the
address to the ROM to access the sine/cosine amplitude values stored in the look-
up table (Vankka and Halonen 2001). The digital amplitude values from the
phase to amplitude converter are then fed into the DAC to obtain the required
sinusoidal output. The spectral purity of the sinusoidal output of the DDFS is
dependant on the word size of the ROM and number of words in the look-up table.
Figure 4.1 Traditional DDFS Architecture
Reducing hardware complexity by optimizing the number of ROMs
used has been one of the major challenges in DDFS design (Vankka 1997). The
impact of memory size on the power consumption and silicon area is very critical
for implementing integrated circuits and system on a chip. Many efficient
compression techniques that can reduce the size of look-up table have been
proposed (Vankka 1997) (Vankka and Halonen 2001).
Techniques which can reduce the ROM size while retaining the
spectral purity and frequency resolution include exploitation of trigonometric
identities and approximation of the sine function using Taylor series, parabolic
FCW
Phase
Accumulat or
Phase t o
Amplit ude
Conver t er
DAC
Sine
Out put
87
approximation (Amir M. Sodagar et al 2003) and polynomial approximation
wherein the samples of sine amplitude are computed from the digital phase
contents.
Sunderland (1984) architecture splits the ROM into two smaller
memories. The Nicholas architecture improves the Sunderland architecture to
obtain higher ROM-compression ratio (32:1). Kesoulis et al (2007) uses sine
phase difference algorithm with modified amplitude reduction technique to
achieve higher compression levels, thereby reducing the memory size. The
quadrant compression technique is able to compress the look-up table and reduce
the ROM by 75%. Lai Lin-hui et al (2008) applied sine-cosine symmetry and
reported 87.5% of ROM size reduction by storing sine and cosine values from 0
to a/4.
It has been observed from the existing methods that the traditional
ROM based DDFS have several drawbacks including higher ROM size, large
chip area, high computation complexity, iteration latency and high power
consumption. This necessitates the development of DDFS based on polynomial
approximation methods with reduced multiplication count. To achieve this, one
often subdivides the expansion region into several subintervals which in turn
carries out its own polynomial expansion, with less multiplication. However, the
reduction in multiplications is done at the cost of extra table to store the
polynomial coefficients, as well as the function values of the expansion points.
This chapter proposes a novel polynomial expansion method to develop a DDFS
with reduced hardware size, less computation complexity and high spectral purity.
88
4.4 PROPOSED DDFS ALGORITHM
The proposed DDFS design is based on the polynomial approximation
method with a judicious choice of polynomial to minimize the hardware
requirement. Though the polynomial algorithm used in the design is based on
Taylor series polynomial, the design is given as follows.
4.4.1 Taylor Series Approximation
In the Taylor series expansion, the Sine and Cosine functions can be
implemented at a point given by,
sin(0) = sin() + (0 - ) * cos() + . . . . (4.1)
cos(0) = cos() - (0 - ) * sin() + . . . . (4.2)
Earlier algorithms for synthesizing DDFS are based on Equations (4.1)
and (4.2) which utilize the sample magnitude of sin(0) stored in a ROM and its
slope (Jen-Chuan Chih et al 2001).
Neglecting higher order terms in Equations (4.1) and (4.2),
sin(0) ~ sin()+(0 - )*cos () (4.3)
cos(0) ~ cos()-(0 - )*sin () (4.4)
Where, is a constant. Another form of Taylor series expansion for
sine and cosine function at a point is given by,
sin() = (
3
/ 3! ) + (
5
/ 5! ) (
7
/ 7!) + . . . . (4.5)
cos() = 1 (
2
/ 2! ) + (
4
/ 4! ) (
6
/ 6! ) + . . . . (4.6)
89
For N-bits precision, the terms after (1(
2
/2!)) in cos() expansion and
in sin() expansion can be ignored because the magnitude of the higher order
terms are less than 2
-(N+1)
.
The Equations (4.5) and (4.6) are further simplified by neglecting
higher order terms as given by
sin() - (4.7)
cos() - 1 (
2
/ 2! ) (4.8)
By applying the Equations (4.7) and (4.8) in Equation (4.3)
sin(0) - + (0 - ) *(1 (
2
/ 2!) )
= 0 ((
2
/ 2 ) * 0 ) +
3
/ 2
Neglecting higher order terms further,
sin(0) - (1 (
2
/ 2)) * 0 (4.9)
The value for sine wave, denoted as
s
, is obtained using Equation (4.9) as,

s
= \ (2 * ( 1- (sin(0)/ 0))) (4.10)
Where, 0 ranges from 0 to 45.
Similarly, by applying Equation (4.7) and (4.8) in Equation (4.4),
cos(0) - (1 + ( * / 2 ) ) - ( 0 * ) (4.11)
The value is cosine function, denoted as
c,
is obtained using Equation (4.11) as,

c
2
-2 (0*
c
) 2 (cos(0) 1) = 0 (4.12)
Where, 0 ranges from 0 to 45. The minimum of the two roots from
Equation 4.12 is used for the computation.
90
Since the approximation is for the ranges from 0 to a/4, the remaining
quadrants values are obtained by the principle of sine/cosine symmetry
(Shu-Chung Yi et al 2006). The sine/cosine waveform is symmetrical between the
range [a, 2a] and [0, a]. Also, the sine waveform from a/2 to a/4 is the same as
the cosine from zero to a/4, and the cosine waveform from a/2 to a/4 is the same
as the sine from zero to a/4. Thus, it is sufficient to compute the sine and cosine
values from 0 to a/4 using Equations 4.9 and Equations 4.11. The entire sine
wave is generated from the translations given in Table. 4.1. The first quadrant is
regrouped as 1A & 1B and similarly other quadrants are regrouped as 2A & 2B,
3A & 3B and 4A & 4B. When the phase value is 0 to a/4 (0 to 45), the sine
value of the phase is computed from the sine generator straight away. When the
phase value is 45 to 90, the sine value of the phase is computed by subtracting
the phase value from 45 and then by passing to a cosine generator. Similarly for
other quadrants the sine values are computed.
Table 4.1 Translation of Phase Values
counter
value (bits)
Quadrant
index
Phase value
)
Degrees
Sine
computation
0 0 0
1A
0_0_45 sin(0)
0 0 1
1B
45<0_90 cos( 45- 0)
0 1 0
2A
90<0_135 cos(0)
0 1 1
2B
135<0_180 sin(45-0)
1 0 0
3A
180<0_225 -sin(0)
1 0 1
3B
225<0_270 -cos( 45- 0)
1 1 0
4A
270<0_315 -cos(0)
1 1 1
4B
315<0_360 -sin(45-0)
91
4.4.2 Proposed Architecture
Figure 4.2 shows the block diagram of the proposed DDFS
architecture to complement the above discussed algorithm. It consists of phase
generator, quadrant selector, sine/cosine generator, digital multiplexers and a
DAC in the output stage. The phase generator (PG) of the proposed DDFS
receives a frequency control word (FCW) as an input from the system to which
the proposed DDFS is to be integrated. The phase generator output is then fed to a
quadrant selector which selects the phase corresponding to the quadrant
requirement. The output of the quadrant selector is fed to a sine/cosine generator.
The multiplexer in the output stage selects the output either from sine generator
or cosine generator to complete a full cycle of sinusoid as given in Table 4.1. The
full cycle is generated by exploiting the symmetry of sine wave with respect to
zero crossings over one full period (Shu-Chung Yi et al 2006).
4.4.2.1 Phase generator
The phase generator consists of a phase accumulator, a maximum
range register (MRR), and a digital comparator as shown in Figure 4.3.The phase
accumulator is designed using an adder and a latch. The adder has two inputs and
one of the inputs is a frequency control word (FCW) and input is fed back from
the latch. The FCW is added with the same value on each clock signal and the
value is accumulated in the latch. For digital realization, the phase is quantized as
= n/2
N
(4.13)
Where N is the size of the frequency control word and n is the value to
be stored in maximum range selector register that takes on integer numbers in the
range 2
N
. The value of N and n determine the resolution of the phase
generator. The phase accumulator output 0 is quantized in the range 0 to a/4
periodically (i.e. 0 to 45). The maximum range value (n) for the maximum
92
phase angle of the phase generator (45) is /4 * 2
N.
The integer equivalent of the
maximum range is stored in a memory called maximum range register. On each
clock signal given to the latch, the phase accumulator generates consecutive
phases. The comparator compares the output of the latch with MRR, when they
are equal the comparator rises active high signal to reset the accumulated value in
the latch. The phase accumulated value (PAV) from the output of the latch, the
maximum range register output, and the comparators output (detect) are
connected to quadrant selector.
Figure 4.2 Block diagram of the proposed DDFS
MAX Range Reg
Compar at or
Phase
Accumul at or
MSB-1
+
Subt r act or
-
3 bit
Count er
LSB
MSB
MUX
PAV
Mux
DAC
Sine
Gener at or
(0-/ 4)
Cosi ne
Gener at or
(0-/ 4)
Sine O/ P
Phase
CLK
FCW
Phase Gener at or Quadr ant Select or
Si ne/ Cosi ne Gener at or
MRR
93
Figure 4.3 Phase generator
4.4.2.2 Quadrant selector
A quadrant selector consists of a subtractor, a multiplexer and a 3- bit
counter as shown in Figure 4.4. It receives the output of the comparator (detect),
the value from the MSR and output of the phase accumulator (PAV).
Figure 4.4 Quadrant selector
The phase generator is designed for generating phase value from 0 to
a/4, and to generate a full cycle of a sinusoidal the phase generator needs to
generate this phase range for 8 times. The comparator in the previous stage
detects the maximum range and generates the detect signal 8 times. The detect
To Quadr ant Select or
To Quadr ant Select or
+
FCW
Compar at or
Det ect
MAX
Range Reg
MRR
CLR
Lat ch
CLK
PAV
To Quadr ant Select or
PAV
MRR
SUBTRACTOR
Fr om Phase
Gener at or
3 bit Count er
MSB
MSB-1
LSB
det ect
Mux Phase
To Sine/ Cosine
Gener at or
94
signal is used as a clock signal to the 3-bit counter so as to count the number of
roll-overs and to identify the quadrant indices. The output of the 3-bit counter
enables the multiplexer to choose the appropriate phase for sine computation. The
MRR value and the phase values of each quadrant indices (1B, 2B, 3B & 4B) are
fed to the subtractor in sequence. The phase values of other indices are routed
directly to MUX. The phase value of each of the indices and the LSB output of
the 3-bit Counter are multiplexed to produce the phase for Sine/Cosine function.
4.4.2.3 Sine/Cosine Generators
The Figure 4.5 shows the block diagram of the Sine/Cosine generators,
which generate sine and cosine value for the input phase between 0 to a/4.The
arithmetic circuit is synthesized as per the Taylor expansion (Equation 4.9) and
(Equation 4.11) for sine and cosine generation respectively. This module receives
the phase value and quadrant indices from the quadrant selector. The phase value
is in the range from 0 to a/4, and this value is given to two section of arithmetic
circuit for generating equivalent sine and cosine value. The two arithmetic circuit
computes its equivalent sine and cosine value from the given phase value and
value. The sine and cosine values are computed using
s
and
c
respectively as
given by in the Equation 4.9 and Equation 4.11. The values of
s
and
c
are
computed in a separate hardware block given in Figure 4.6.
A full cycle of sinusoidal signal is generated from two arithmetic
sections with the assistance of quadrant index bits namely LSB and MSB-1.
These two bits decide the output from any one of these two arithmetic sections.
The selection of arithmetic is given in the Table 4.2. It is clear from the table that
an EX-OR of LSB and MSB-1 selects a cosine generator, otherwise a sine
generator is selected.
95
Figure 4.5 Sine/cosine generators for 0 to /4
Table 4.2 Arithmetic section selection for the quadrant index bits
Quadrant
Index
Bit
MSB-1 LSB
Quadrant
Index
Phase value ()
In degree
Arithmetic
Section
selection
0 0 1A 0_0_45 sin section
(1 (
2
/ 2))
0 1 1B 45<0_90 cosine section
( 1 + (
2
/ 2))
1 0 2A 90<0_135 cosine section
1 1 2B 135<0_180 sin section
0 0 3A 180<0_225 -(sin section)
0 1 3B 225<0_270 -(cosine section)
1 0 4A 270<0_315 -(cosine section)
1 1 4B 315<0_360 -(sine section)
Fr om
Quadr ant
Select or

c
-
1+
c
2
/2

1-
s
2
/2
Phase
Mux
Sign
Magni t ude
DAC
Sin
MSB-1
LSB
MSB-1
LSB
MSB
96
The quadrants 3A, 3B, 4A and 4B require negation in the output of the
DDFS, and this is done by MSB of the quadrant index bits. Once a full cycle of
sinusoidal wave is obtained the entire module starts for a new cycle.
4.4.2.4 Accumulator
Figure 4.6 shows the block diagram of the accumulator employed for
generating
s
values. It consists of an adder, latch, comparator, subtractor and a
multiplexer. Also the module comprises of two registers, one register to store the

max
value (
s
value corresponding to (/ 4 * 2
N
)
th
clock cycle) and another register
to store the step value (linear incremental step size of the ) which is a product
of frequency control word (FCW) and
max
/ (/ 4 * 2
N
).
For each clock input, the adder with the latch generates an accumulated
value with the step size of (
max
/ (a/4 *2
N
))*FCW. This accumulated value is
fed to a comparator and a subtractor.
The comparator compares accumulated value with the
max
value for
every instance of clock. When the accumulated value reaches to
max,
the latch
is cleared to zero and accumulation is started from initial value.
The subtractor subtracts accumulated value with the
max
value for
every instance of clock. The subtracted value of the accumulator is fed to
multiplexer and the accumulated value is also given to the multiplexer. One of
the inputs of the multiplexer is selected by the LSB of the counter in quadrant
selector and given to sine/cosine generator.
97
CLR
Thus, accumulator is employed to generate
s
values between 0 to / 4.
Similar hardware architecture is used to generate
c
values. The primary
difference between the architectures employed to generate
s
and
c
values lies in
the
max
register content. The appropriate values to be stored in the
max
registers
are determined from (Equation 4.10) and (Equation 4.12).
Figure 4.6 Block diagram of accumulator
4.5 RESULTS AND DISCUSSIONS
The Phase generator, quadrant selector, sine/cosine generator, and
accumulator are coded in Verilog and implemented in Altera FPGA DE1 kit. A
digital to analog circuit is assembled in a vero board. The DAC board and FPGA
kit are interfaced through GPIO. The value of N is assumed to 11-bit, the value of
n is computed as in Equation 4.3 using the symmetry of sine and cosine over
0_0_a/4 varies from 0 to 1608. The resolution of the proposed DDFS is
4.8843e
-004
. A Matlab program is written to calculate the values of
s
and
c
theoretically using Equations 4.10 4.13.
s
values range from 0.0003 to 0.4465
and
c
values range from 0.0005 to 0.6091. For the above values, the output
waveform of the designed DDFS is captured by a computer using Agilent
LSB
+
Mux

s
-
Compar at or
Lat ch

max
(
max
/ / 4 * 2
N
))* FCW
Subtractor
98
34401A through RS232 interface. The captured data are fed to the Matlab
program for extracting the graph. The spectrum of the captured data is shown in
Figure 4.15.
Figure 4.7 and Figure 4.8 show the comparison plot between ideal and
theoretical sine and cosine values for theoretical values in the time domain. It
can be seen that the ideal values of the sine wave and values obtained from the
proposed method coincides very well. Figure 4.9 show the spectrum obtained
using the theoretical values. It can be seen that the SFDR of the proposed DDFS
using the theoretical values is nearly 193 dBc.
Figure 4.7 Comparison plot for sine values between ideal and proposed
method using LUT for
s
sets
99
Figure 4.8 Comparison plot for cosine values between ideal and proposed
method using LUT for
c
sets
Figure 4.9 Spectrum of the proposed DDFS using LUT for values
100
Figure 4.10 and Figure 4.11 show the comparison plot between ideal
and proposed sine and cosine values for linear increment of values. As it is seen
from the Figure 4.10, the ideal and the proposed method coincide very well
proving the accuracy of the proposed algorithm. Whereas in the Figure 4.11 it can
be observed that there exists a slight deviation between the ideal and the proposed
method. This is due to the predominant contribution of values.
Figure 4.10 Comparison plot for sine values between ideal and proposed
method using accumulator
101
Figure 4.11 Comparison plot for cosine values between ideal and proposed
method using accumulator
Figure 4.12 shows the spectrum for DDFS using linear increment of
values. As it is seen from the graph, the SFDR performance of the DDFS using
linear increment of
s
and
c
over the range 0 - a/4 is about 135.623 dBc. Thus,
using the linear increment values, SFDR is reduced to 135.95 dBc as compared
to actual values set of 193dBc. A simple combinational circuitry can
automatically generate the values if one knows the range of values that is the
maximum and minimum values of , and the linear equation. Thus, using the
linear increment values, the ROM size is drastically reduced.
102
Figure 4.12 Spectrum of the proposed DDFS using accumulator in
simulation
Figure 4.13 Deviation plot for
s
values using LUT values and
accumulator
103
Figure 4.14 Deviation plot for
c
values using LUT values
and accumulator
Figure 4.13 shows the comparison between theoretical and the linear
increment values of
s
. It is inferred from the graph that the linear increment
s
values are in line with the theoretical
s
values. But, the variation between
theoretical
c
and linear increment
c
is slightly larger due to the strong
dependency of cosine function with . This can be observed from Figure 4.14. As
it can be seen from Figure 4.12, this deviation does not affect the applicability of
the proposed algorithm.
The SFDR from the measured data for the sine wave is 130.3 dBc,
which is comparable with theoretical calculation of 135.3 dBc.
104
Figure 4.15 Spectrum of the proposed practical DDFS using accumulator
Table 4.2 shows a comprehensive comparative study of various
performance parameters of ADC test bed namely, bit resolution, SFDR, SNR,
ROM table size and hardware overhead for various DDFS methods reported in
the literature with that of the proposed method. It can be noted that the measured
SFDR is 130.3dBc in the proposed method with only 11 bit resolution, as
compared to the SFDR of 130.3 dBc with 15-16 bit resolution used by most
methods. Moreover in this method since linear increment of is used, the
requirement of ROM has been reduced to minimal, thus reducing the hardware
requirement.
105
Table 4.3 Performance Summary of DDFS
Method
Bit
resolution
SFDR
(dBc)
SNR
(dB)
ROM
table
size
(bits)
Hardware
Overhead / Comments
Madisetti
et al (1999)
16 100 92.2 _
Multiplier-Less Feed-
Forward Data Path
Bellaouar
et al (2000)
11 60 60.48 416
Linear Interpolation
between
Sample Points
Jen-Chuan
et al (2001)
16 100 92 512 3 adders and 4 multipliers
Langlois et al
(2003) 14 96.2 78.92 960 64 Linear Segments
Sodagar et al
(2003)
12 66.8 69 728 Parabolic Initial Guess
Usman et al
(2005)
12 45 70 64
Sine Wave Symmetry from 0
to a/2
Shu-Chung
et al (2006)
17 80 98 384
Trigonometric Double Angle
formula, 3 adders and 3
multipliers
Ru Xin et al
(2007)
18 99.6 99.3 _ Area Optimized DDFS
Kesoulis et al
(2007)
12 63.12 65 448
Modified Amplitude
Compression Technique
Lai Lin-hui
et al (2008)
10 63.58 58.2 328 2 adders, 2 shift registers
Tze-Yun et al
(2009)
16 84.4 90.2 64
Multiplier Less,
Pipelined Data Path
Xiaojin et al
(2009) 14 90 75 _
Two Segment Fourth Order
Parabolic Approximation
Technique
Wan Shuqin et
al (2009)
16 84.4 91.8 69
Twenty eight adders,
52 shifters,14 latches,
20 multiplexers
Proposed 11 130.3 64 -
Using gamma accumulator
106
4.6 CONCLUSION
A novel DDFS architecture has been proposed to generate a sinusoidal
signal. The proposed method is implemented based on Taylor Series polynomial
approximations and improves the spectral purity remarkably. The replacement of
look-up table with a digital combinational and sequential circuits results in the
reduction of hardware complexity and also aids in faster computation. Results
shows that the spectral purity of the proposed DDFS is as high as 135.6 dBc for
11-bit resolution compared to 90 dBc for 14-bit resolution attainable with hybrid
CORDIC algorithm.