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FPGA Image/Video Processing Guide

This document provides instructions for image/video processing on an Xilinx FPGA using hardware co-simulation in Simulink. The steps include: 1) Loading a reference design and system generator block, 2) Compiling for the target board, 3) Connecting the hardware co-simulation block to a test bench, 4) Configuring the co-simulation block properties, and 5) Running the test bench to test the design.

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253 views4 pages

FPGA Image/Video Processing Guide

This document provides instructions for image/video processing on an Xilinx FPGA using hardware co-simulation in Simulink. The steps include: 1) Loading a reference design and system generator block, 2) Compiling for the target board, 3) Connecting the hardware co-simulation block to a test bench, 4) Configuring the co-simulation block properties, and 5) Running the test bench to test the design.

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VIJAYPUTRA
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© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Image/VideoProcessingonXilinxFPGATutorial

1. Loadthereferencedesignlocatedat: C:\Xilinx\10.1\DSP_Tools\sysgen\examles\shared_memory\hardware_cosim\conv5x5\conv5x5_ video_ex.mdlanddoubleclickontheSystemGeneratorblock.

2. ChangetheoptionforCompilationtoyourboardsnameunderHardwareCoSimulation

3. Choosetheinterfacingmethodavailableforyourboard,forexample:Ethernet>PointtoPoint orJTAGorPCIandUSB.Ethernetisthefastest,notsureaboutPCI.. 4. ChangetheTargetdirectoryto./hwcosim(thisiswhereallthecompiledfileswillbestoredfor HardwareCoSimulationpurposes,especiallythegeneratormodelfortheHWCoSimlibrary 1 Createdby:MostofaNoor|[email protected]|2010/03/04|v1.0

Image/VideoProcessingonXilinxFPGATutorial
block,thedirectorynamecanbeanything,justchangethedefault./netlisttosomethingelse thatdoesnotexist,orelseyoumaygeterrorsduringcompilation.) 5. ThenclicktheGeneratebuttontostartthecompilationprocessofthehardware.Sincethisisan unmodifiedreferencedesign,thereshouldnotbeanyerrorsduringthelongcompilation process. 6. Whencompleted,thereshouldpopupaSimulinkwindowwiththegenerated(greycolored) HWCoSimblockforyourdesign.

7. Loadthetestbenchmodelfile:conv5x5_video_testbench.mdl.Thisfileisthetoplevelmodule whichwillprovidestimulustotheinputsofyourdesignfromMatlabWorkspacevariablesor SimulinkSourceslikeSignalGenerators,forthismodelitwillbeastructurevariableinMatlab WorkspacethatwillbeloadedbythePreLoadfunctionmodeldescribedatalaterstep.

8. DoubleClickontheFPGAProcessingblock,thereshouldalreadybeaJTAGCosimblock instantiatedthere,selectanddeletethat. 9. DragyourCoSimblockthatyougeneratedtotheTestbench/FPGAProcessingwindowand placeitonthelightblueplacementmarkerandmakesurethegainandoffsetinputsare connected. Createdby:MostofaNoor|[email protected]|2010/03/04|v1.0

Image/VideoProcessingonXilinxFPGATutorial

10. RightClickontheCoSimblockandclickonBlockPropertiestochangethePriorityvalueto2. Thisistoproperlyprioritizetheruntimeblockpriorities,theSharedMemoryWriteblackhas firstpriority,thenyourHWCoSimblockissecondpriority,andthentheSharedMemoryRead blockis3rdpriority.

11. ThenDoubleClickontheHWCoSimblock,undertheBasictab,changetheClockingoptionto Freerunning.ThisallowstheFPGAtorunatitsfastestspeed,whichisnecessaryforrealtime simulation. 12. Next,ifyouaredoingPointtoPointEthernetHWCoSim,intheEthernettab,changetheHost interfacetoyourconfiguredEthernetadapter.YourEthernetadaptershouldbeconfiguredto thesettingsandIPaddress(192.168.8.2)shownontheUsersGuideforSystemGenerator.Also Winpcapshouldbeinstalled(foundatwww.winpcap.org)toallowstraightdataI/OviaEthernet andbypassingtheTCP/UDPpacketprocessingoverhead.Makesureyouchoosethecorrect Createdby:MostofaNoor|[email protected]|2010/03/04|v1.0

Image/VideoProcessingonXilinxFPGATutorial
EthernetportthatyouhaveconfiguredifyouhavemorethanoneEthernetportsbyverifying theMACaddress.

13. IntheConfigurationtab,chooseyourconfigurationinterface,ParallelCableIV,PlatformUSB, etc.ThisinterfacewillbeusedtodownloadthebitstreamandprogramtheFPGA.Notethat ParallelJTAGorUSBJTAGinterfacecanalsobeusedforruntimedataI/Oatslowerspeedthan Ethernet.

14. ClickOKtoclosetheconfigurationwindow.Nowyourtestbenchisreadytorun.Clickonthe playbuttonontopofthetestbenchtoolbar.Makesureyouturnonyourboardandconnectthe JTAGandEthernetcables.Ifyougetanerrorsaying,Errorevaluatingparameter VariableNameinconv..Undefinedfunctionorvariableimg.Thatmeansthepreload functionwasnotrun,justloadandrunconv5x5_video_testbench_PreloadFcn.mscripttoload thevariablesintotheMatlabWorkspaceandthenrunyourtestbenchagain. 4 Createdby:MostofaNoor|[email protected]|2010/03/04|v1.0

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