PAAVAI ENGINEERING COLLEGE

PAAVAI NAGAR, NH-7, PACHAL, NAMAKKAL-637018

Name: Branch: Register No: Roll No:

Certified that this is bonafide record of work done by the above student of the.laboratory ! 20 2 during the year 20

"ignature of #ab $n charge

"ignature of %ead of the &e'artment

"ubmitted for the (ractical )*amination held on ..

$nternal )*aminer

)*ternal )*aminer

CONTENTS

EXP. NO.

DATE

NAME OF THE EXPERIMENT

PAGE NO.

MARKS AWARDED

REMARKS

+odeling of "e,uential &igital "ystem -sing .%&# 2 +odeling of "e,uential &igital "ystem -sing .)R$#/0 &esign 2nd $m'lementation of 2#-sing 3(02 "imulation of N+/" 2nd C+/" circuits -sing "($C) &esign 2nd $m'lementation /f +ultirate "ystems -sing &"( "earching 2nd "orting 2lgorithms -sing 6 Bit +icro'rocessor "imulation of 8+3 -sing "imulation (ackages

EX.NO: 1 DATE: 2

MODELING OF SE !ENTIAL DIGITAL S"STEM !SING VHDL AIM: 9o model and simulate the se,uential digital system using .%&#. TOOLS RE !IRED: :ilin* $") ;. i (C PROCED!RE: 9he :ilin* $") ;. i is o'ened. $n the file menu New (ro<ect is selected. $n New (ro<ect wi=ard name is mentioned and then in new 'ro<ect wi=ard device 'ro'erties $") simulator is selected and then finish is chosen. $n 'ro<ect> new source!select ty'e> .%&# module is chosen and file name is given then the 'rogram for se,uential digital system ?&!3li'flo'> -' counter> &own counter> and "hift Register@ have been designed and saved. "ynta* is verified by using Check "ynta* o'tion in 'rocess navigator bar. "imulation is done by selecting Behavioral simulation from source window and the corres'onding file is selected. $n the 'rocess navigator tool 9)"9 B)NC% waveform is selected and the in'ut is given and the file is saved. 9hen the :ilin* $") "imulator is chosen and the simulated out'ut waveform will be generated.

PROGRAM: 1

D-FLIPFLOP library $)))A use $)))."9&B#/0$CB 64.2##A use $)))."9&B#/0$CB2R$9%.2##A use $)))."9&B#/0$CB-N"$0N)&.2##A !!!! -ncomment the following library declaration if instantiating !!!! any :ilin* 'rimitives in this code. !!library -N$"$+A !!use -N$"$+..Com'onents.allA entity gfhgh is (ort ? d : in "9&B#/0$CA clk : in "9&B#/0$CA , : out "9&B#/0$CA ,b : out "9&B#/0$C@A end gfhghA architecture Behavioral of gfhgh is begin 'rocess?clk@ begin if?clkCD D@then ,ECd after 0 nsA ,bECnot d after 20 nsA end ifA end 'rocessA end BehavioralA

LOGIC DIAGRAM FOR D-FLIPFLOP: 4

TR!TH TA#LE:

O!TP!T WAVEFORM FOR D-FLIPFLOP

!PCO!NTER 5

library $)))A use $)))."9&B#/0$CB 64.2##A use $)))."9&B#/0$CB2R$9%.2##A use $)))."9&B#/0$CB-N"$0N)&.2##A !!!! -ncomment the following library declaration if instantiating !!!! any :ilin* 'rimitives in this code. !!library -N$"$+A !!use -N$"$+..Com'onents.allA entity u' 24 is (ort ? clk : in "9&B#/0$CA rst : in "9&B#/0$CA , : out "9&B#/0$CB.)C9/R?1 downto 0@@A end u' 24A architecture Behavioral of u' 24 is signal dataout:stdBlogicBvector?1 downto 0@A begin 'rocess?clk>dataout@ begin if?clk Devent and clkCD D@then if?rstCD D@then dataoutECF0000FA else dataoutECdataoutG A end ifA end ifA ,ECdataoutA end 'rocessA end BehavioralA

LOGIC DIAGRAM FOR !P CO!NTER: 6

O!TP!T WAVEFORM FOR !PCO!NTER

DOWNCO!NTER 7

library $)))A use $)))."9&B#/0$CB 64.2##A use $)))."9&B#/0$CB2R$9%.2##A use $)))."9&B#/0$CB-N"$0N)&.2##A !!!! -ncomment the following library declaration if instantiating !!!! any :ilin* 'rimitives in this code. !!library -N$"$+A !!use -N$"$+..Com'onents.allA entity u' 24 is (ort ? clk : in "9&B#/0$CA rst : in "9&B#/0$CA , : out "9&B#/0$CB.)C9/R?1 downto 0@@A end u' 24A architecture Behavioral of u' 24 is signal dataout:stdBlogicBvector?1 downto 0@A begin 'rocess?clk>dataout@ begin if?clk Devent and clkCD D@then if?rstCD D@then dataoutECF0000FA else dataoutECdataout! A end ifA end ifA ,ECdataoutA end 'rocessA end BehavioralA

LOGIC DIAGRAM FOR DOWN CO!NTER: H

F RES

O!TP!T WAVEFORM FOR DOWNCO!NTER

SHIFT REGISTER ;

library $)))A use $)))."9&B#/0$CB 64.2##A use $)))."9&B#/0$CB2R$9%.2##A use $)))."9&B#/0$CB-N"$0N)&.2##A !!!! -ncomment the following library declaration if instantiating !!!! any :ilin* 'rimitives in this code. !!library -N$"$+A !!use -N$"$+..Com'onents.allA entity sisosat is (ort ? rs : in "9&B#/0$CA d : in "9&B#/0$CA clr : in "9&B#/0$CA clk : in "9&B#/0$CA , : out "9&B#/0$C@A end sisosatA architecture Behavioral of sisosat is signal s:stdBlogicBvector?1 downto 0@A begin 'rocess?clk@ begin if?clkDevent and clkCD D@then if?clrCD D@then sECF0000FA elsif rsECD D then s?1@ECdA s?2@ECs?1@A s? @ECs?2@A s?0@ECs? @A end ifA end ifA ,ECs?0@A end 'rocessA end BehavioralA

LOGIC DIAGRAM FOR SHIFT REGISTER: 0

O!TP!T WAVEFORM FOR SHIFTREGISTER

RES!LT: 9hus the se,uential systems were designed and simulated using .%&#.

EX.NO: $ DATE: MODELING OF SE !ENTIAL DIGITAL S"STEM !SING VERILOG AIM: 9o model and simulate the se,uential digital system using .)R$#/0. TOOLS RE !IRED: :ilin* $") ;. i (C PROCED!RE: 9he :ilin* $") ;. i is o'ened. $n the file menu New (ro<ect is selected. $n New (ro<ect wi=ard name is mentioned and then in new 'ro<ect wi=ard device 'ro'erties $") simulator is selected and then finish is chosen. $n 'ro<ect> new source!select ty'e> .)R$#/0 module is chosen and file name is given then the 'rogram for se,uential digital system ?&!3li'flo'> -' counter> &own counter> and "hift Register@ have been designed and saved. "ynta* is verified by using Check "ynta* o'tion in 'rocess navigator bar. "imulation is done by selecting Behavioral simulation from source window and the corres'onding file is selected. $n the 'rocess navigator tool 9)"9 B)NC% waveform is selected and the in'ut is given and the file is saved. 9hen the :ilin* $") "imulator is chosen and the simulated out'ut waveform will be generated

PROGRAM FOR D-FLIPFLOP: module dff?,> d> clk> rst@A out'ut ,A in'ut dA in'ut clkA in'ut rstA reg ,A alwaysI?'osedge clk or negedge rst@ if?rstCC0@ ,C Db0A else ,CdA endmodule

O!TP!T WAVE FORM FOR D FLIP FLOP:

!P CO!NTER: module u'?,> clk> clear@A out'ut J1:0K ,A in'ut clkA in'ut clearA regJ1:0K,A alwaysI?'osedge clear or negedge clk@ begin if?clear@ ,EC4Dd0A else ,EC,G A end endmodule

O!TP!T WAVE FORM FOR !PCO!NTER

DOWN CO!NTER: module down?,> clk> clear@A out'ut J1:0K ,A in'ut clkA in'ut clearA regJ1:0K,A alwaysI?'osedge clear or negedge clk@ begin if?clear@ ,EC4Dd0A else ,EC,! A end endmodule

O!TP!T WAVE FORM FOR DOWN CO!NTER

SHIFT REGISTER: module sr?s0> s > in> clk> clr> ,@A in'ut s0A in'ut s A in'ut inA in'ut clkA in'ut clrA out'ut J1:0K,A regJ1:0K,A alwaysI?'osedge clk or negedge clr@ begin if?clrCC0@ ,C4Db0000A if?s0CC @ ,CL,J1: K>inMA else if?s CC @ ,CL,J1: K>inMA end endmodule

20

O!TP!T WAVE FORM FOR SHIFT REGISTER

RES!LT: 9hus the se,uential systems were designed and simulated using .)R$#/0.

22

EX.NO: 3 DATE: DESIGN AND IMPLEMENTATION OF AL! !SING FPGA AIM: 9o design 2#- unit using .%&# coding and to im'lement using 3(02 Nit. TOOL RE !IRED: :$#$N: $") ;. i 3(02 kit (C PROCED!RE: Create a new 'ro<ect and set the device 'ro'erties in the 'ro<ect wi=ard. Create new source> s'ecify the in'uts and out'uts and ty'e the 'rogram. "ave file and go for check synta*. 0o to user constraints and assign the 'ackage 'ins. "ynthesi=e the 'rogram and for im'lementing the design. /nce the design is successfully im'lemented> generate the 'rogramming file and configure the device $+(2C9. Click finish. "elect the O.bit O file and o'en. 9hen the :$#$N: device will a''ear in the window. 9hen the 'rogram is loaded into the kit and (R/0R2+ "-CC))&)& will a''ear.

21

PROGRAM library ieeeA use ieee.stdBlogicB 64.allA use ieee.stdBlogicBunsigned.allA use ieee.stdBlogicBarith.allA entity 2#- is 'ort? 2: in stdBlogicBvector? downto 0@A B: in stdBlogicBvector? downto 0@A "el: in stdBlogicBvector? downto 0@A Res: out stdBlogicBvector? downto 0@@A end 2#-A architecture behv of 2#- is begin 'rocess?2>B>"el@ begin !! use case statement to achieve !! different o'erations of 2#case "el is when F00F CP Res EC 2 G BA when F0 F CP Res EC 2 G ?not B@ G A when F 0F CP Res EC 2 and BA when F F CP Res EC 2 or BA when others CP Res EC F::FA end caseA end 'rocessA end behvA

24

SIM!LATED O!TP!T:

PIN ASSIGNMENTS:

25

RES!LT:

26

9hus the 2#- unit was designed using .%&# and is im'lemented in 3(02 kit.

EX.NO: % DATE: SIM!LATION OF NMOS AND CMOS LOGIC GATES !SING SPICE. AIM: 9o &esign N+/" and C+/" logic 0ates using "($C) and simulate it. TOOLS RE !IRED: +$CR/Q$N& 1 PROCED!RE: /'en +$CR/Q$N& 1. Client dsch1com'lete. Click file and save it. "elect foundary cmos0 2o'en. +ake a verilog filecoding convert 'rogramok. /'en +$CR/Q$N&1 3ile"elect foundary cmos0 2.rulok. Com'ilecom'ile verilog fileR3ilename.vRo'en. Com'ile click back to editor /ut'ut will be generated. .iew"imulate .oltage vs 9ime.

27

SCHEMATIC DIAGRAM FOR NAND GATE !SING NMOS:

2H

LA"O!T:

2;

SIM!LATED O!TP!T:

10

SCHEMATIC DIAGRAM FOR NAND GATE !SING CMOS LOGIC:

LA"O!T:

12

SIM!LATED O!TP!T:

11

SCHEMATIC DIAGRAM FOR NOR GATE !SING CMOS LOGIC:

14

LA"O!T:

15

SIMULATED OUTPUT:

16

RES!LT: 9hus the C+/" and N+/" logic gates were simulated using "($C). 17

EX.NO: & DATE: DESIGN AND IMPLEMENTATION OF M!LTIRATE S"STEMS !SING DSP AIM: 9o design and im'lement &ecimation and $nter'olation using &"( (rocessor. TOOLS RE !IRED: CC"tudio1. &"( (rocessor. PROCED!RE: /'en 67 1&"N"tart(ass will a''ear. "elect 67 1&"N CC"tudio .1. o'en &ebugconnect. /'en 'ro<ectnew create 'ro<ectselect target?9+"120C67::@. 3ilesource file9y'e 'rogram "ave as Ofilename.cR. Click the 'ro<ect add files to 'ro<ecto'enclick source filename.c 2dd file to 'ro<ectrts6700.lib?'ath:c:Scccstudio v1. Sc6000ScgtoolsSlibSrts6700.lib@ 9o link the fileadd files to 'ro<ect hello.cmd?'ath: c:Sccstudio v1. StutorialSdsk67 1Shello. Shello.cmd@o'en (ro<ectcom'ile fileclick. (ro<ectbuild. 3ile load 'rogramdebug filename.outclick. &ebugrun .iew 0ra'h9time vs fre,uency.

1H

PROGRAM: DECIMATION: TincludeEstdio.hP TincludeEmath.hP Tdefine length 50 Tdefine & 2 Tdefine lengthB&?int@?lengthU&@ float :B&Jlength!&KA float VCJ50K>V"J50KA void sine?@A void decimate?@A void main?@ L sine?@A M void sine?@ L int nA float w0>fA fC50A w0C2W1. 4WfA VCJ0KCcos?w0@A V"J0KCsin?w0@A for?nC AnE50AnGG@ L VCJnKC?VCJ0KWVCJn! K@!?V"J0KWV"Jn! K@A V"JnKC?VCJ0KWV"Jn! K@G?V"J0KWVCJn! K@A M decimate?@A M void decimate?@ L int nA for?nC0AnElengthU2AnGG@ L :B&JnKCV"J2WnKA M M

1;

O!TP!T WAVEFORM:

40

INTERPOLATION: TincludeEstdio.hP TincludeEmath.hP Tdefine length 50 Tdefine & 2 Tdefine lengthB&?int@?lengthU&@ float :B&Jlength!&KA float VCJ50K>V"J50KA float :B$JlengthKA void sine?@A void decimate?@A void inter'olate?@A void main?@ L sine?@A M void sine?@ L int nA float w0>fA fC50A w0C2W1. 4WfA VCJ0KCcos?w0@A V"J0KCsin?w0@A for?nC AnE50AnGG@ L VCJnKC?VCJ0KWVCJn! K@!?V"J0KWV"Jn! K@A VCJnKC?VCJ0KWV"Jn! K@G?V"J0KWVCJn! K@A M decimate?@A M void decimate?@ L int nA for?nC0AnElengthU2AnGG@ L :B&JnKCV"J2WnKA M inter'olate?@A M void inter'olate?@ L int nA 4

for?nC0AnElengthU2AnGG@ L :B$J2WnKC:B&JnKA M for?nC0AnElengthU2AnGG@ L :B$J2WnG KC?:B$J?2Wn@KG:B$J2W?nG2@K@U2A MM O!TP!T WAVEFORM:

42

RES!LT:

41

9hus inter'olation and decimation 'rogram was 'erformed using &"( 'rocessor.

EX.NO: 6 DATE: SEARCHING AND SORTING ALGORITHMS !SING 16-#IT MICROPROCESSOR AIM: 9o find the numbers in a given array using 6 bit micro'rocessor. @ 2@ 1@ 4@ #argest "mallest &escending 2scending

TOOLS RE !IRED: H0H6 kit PROCED!RE: 9he assembly language code is entered the micro'rocessor kit by ty'ing O2R. 9he starting address is given. 9he 'neumonics are entered in the kit and its corres'onding o'codes are generated by the kit itself. Reset 0/ and starting address)nter for e*ecution of the 'rogram. 2gain Reset and ty'e "B ?substitute byte@ for 'roviding the in'ut. 0ive the in'ut address and the corres'onding in'uts. Reset 0/ and starting address)nter. Reset"B out'ut address )nter 9he /ut'ut will be dis'layed.

44

PROGRAM FOR LARGEST N!M#ER IN A DATA ARRA": +/. "$> 0100% +/. C:> J"$K +/. 2:> 0000 BCN $NC "$ $NC "$ C+( 2:> J"$K X2) 0/ +/. 2:>J"$K 0/ #//( BCN +/. J015 K> 2: $N9 1

PROGRAM FOR SMALLEST N!M#ER IN A DATA ARRA": +/. "$> 0100% +/. C:>J"$K +/. 2:> ;;;; BCN $NC "$ $NC "$ C+( 2:>J"$K XB 0/ +/. 2:>J"$K 0/ #//( BCN +/. J015 K> 2: $N9 1

45

O!TP!T FOR LARGEST N!M#ER: &292: 1000 ! 04 100 ! 00 1002 ! 52 1001 ! ;4 1004 ! H6 1005 ! 71 1006 ! 67 1007 ! 15 100H ! H6 100; ! ;5 R)"-#9: 105 ! H6 1052 ! ;5

O!TP!T FOR SMALLEST N!M#ER: &292: 1000 ! 04 100 ! 00 1002 ! 52 1001 ! ;4 1004 ! H6 1005 ! 71 1006 ! 67 1007 ! 15 100H ! H6 100; ! ;5 R)"-#9: 105 ! 67 1052 ! 15

46

PROGRAM TO SORT AN ARRA" IN DESCENDING ORDER: C#C +/. C:>J1000%K &)C C: # : (-"% C: +/. "$>2000 #2:+/. 2:>J"$K +/. B:>J"$G2K C+( B:>2: XB) #1 :C%0 2:>B: +/. J"$K>2: +/. J"$G2K>B: #1:$NC "$ $NC "$ #//( #2 (/( C: #//( # %#9

PROGRAM TO SORT AN ARRA" IN ASCENDING ORDER: C#C +/. C:>J1000%K &)C C: # : (-"% C: +/. "$>2000 #2:+/. 2:>J"$K +/. B:>J"$G2K C+( B:>2: X2) #1 :C%0 2:>B: +/. J"$K>2: +/. J"$G2K>B: #1:$NC "$ $NC "$ #//( #2 47

(/( C: #//( # %#9

O!TP!T FOR DESCENDING ORDER:

&292: 1000 ! 04 100 ! 00 2000 Y 01 200 Y 00 2002 Y 05 2001 Y 00 2004 Y 0H 2005 Y 00 2006 Y 06 2007 Y 00

R)"-#9:

2000 Y 0H 200 Y 00 2002 Y 06 2001 Y 00 2004 Y 05 2005 Y 00 2006 Y 01 2007 Y 00

O!TP!T FOR ASCENDING ORDER:

&292: 1000 ! 04 100 ! 00 2000 Y 01 200 Y 00 2002 Y 05 2001 Y 00 2004 Y 0H 2005 Y 00 2006 Y 06 2007 Y 00

R)"-#9:

2000 Y 01 200 Y 00 2002 Y 05 2001 Y 00 2004 Y 06 2005 Y 00 2006 Y 0H 2007 Y 00

4H

4;

RES!LT: 9hus the arrays of numbers were sorted using 6 bit micro'rocessor.

EX.NO: 7 DATE: SIM!LATION OF MF !SING SIM!LATION PACKAGE

AIM: 9o simulate the 8uadrature +irror 3ilter ?8+3@ using the simulation 'ackage ?+29#2B@. TOOLS RE !IRED: +29#2B PROCED!RE: "elect 3ile New +!file 9y'e the 'rogram. "ave it. Run the 'rogram to get the desired waveform.

50

PROGRAM: Z #oad scaling filter associated with an orthogonal wavelet. #oad db 0A "ub'lot ?12 @A stem ?db 0@A title ?Ddb 0 low!'ass filterD@A Z Com'ute the ,uadrature mirror filter. ,mfdb 0 C ,mf?db 0@A sub'lot?122@A stem?,mfdb 0@A title?D8+3 db 0 filterD@A Z Check for fre,uency condition ?necessary for orthogonality@: Z abs?fft?filter@@[2 G abs?fft?,mf?filter@@[2 C at each Z fre,uency. m C fft?db 0@A mt C fft?,mfdb 0@A fre, C J :length?db 0@KUlength?db 0@A sub'lot?121@A 'lot?fre,>abs?m@@A title?D9ransfer modulus of db 0D@ sub'lot?124@A 'lot?fre,>abs?mt@@A title?D9ransfer modulus of 8+3 db 0D@ sub'lot?125@A 'lot?fre,>abs?m@.[2 G abs?mt@.[2@A title?DCheck 8+3 condition for db 0 and 8+3 db 0D@ *label?D abs?fft?db 0@@[2 G abs?fft?,mf?db 0@@[2 C D@

O!TP!T:

52

51

RES!LT: 9hus the 8uadrature +irror 3ilter ?8+3@ was simulated using +29#2B software.

54