242

CHAPTER 7
7.1

7.2

(a) 16 K 8

Address lines = 14, Data lines = 8

(b) 512 K 16

Address lines = 19,

(c) 32 M 32

Address lines = 25, Data lines = 32

(d) 8 G 16

Address lines = 33, Data lines = 16

Data lines = 16

(a) 16 K Bytes
(b) 1024 K Bytes
(c) 128 M Bytes
(d) 16 G Bytes

7.3

1024 16 memory
word: no. 875
data 46654

7.4

Address line
Address bits
16-bit data

= 10, Data line = 16

= 11011011011
= 1011 0110 0011 1110
= B63E16

f CPU = 150 MHz, TCPU = 1/fCPU = 6.67-9 Hz-1

15 ns
6.67 ns

6.67 ns

6.67 ns

CPU clock
T1

Address

T2

T3

Address valid

Memory select

Data from CPU

Data valid for write

Data from memory

Data valid for read

7.5
Pending

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243

7.6

7.7

(a) 64 K = 216 = 28 28 = 256 256

Each decoder is 8 : 256
Decoder requires 512 AND gates, each with 8 inputs.
(b) 36,952 = 1001 0000 0101 1000
X = 1001 0000 = 144
Y = 0101 1000 = 88

7.8

(a)

512 K
= 8 chips
64 K

(b) 512 K = 219

19-bit address lines.

64 K = 216

16-lines are connected to each chip

and remaining (19 16) = 3 are for
selecting the chips.

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244
(c) 19 16 = 3 lines with 3 8 decoder.
7.9

Capacity of memory = 215 + 16 = 231 words = 2G.

7.10

Bit position = 1 2 3 4 5 6 7 8 9 10 11 12 13 14
P1

P2 0 P4 1 1 0 P8 1 0 1 0 1 1

P1 = XOR of (3, 5, 7, 9, 11, 13)

= XOR of (0, 1, 0, 1, 1, 1) = 0

P2 = XOR of (3, 6, 7, 10, 11, 14)

= XOR of (0, 1, 0, 0, 1, 1) = 0

P4 = XOR of (5, 6, 7, 12, 13, 14)

= XOR of (1, 1, 0, 0, 1, 1) = 0

P8= XOR of (9, 10, 11, 12, 13, 14) = XOR of (1, 0, 1, 0, 1, 1) = 0
Composite 14-bit code word = 00 0011 0010 1011
7.11

Bit position

1
P1

P2

P4

P8

10

P1 = XOR of (3, 5, 7, 9, 11, 13)

= XOR of (1, 1, 1, 1, 1, 0) = 1

P2 = XOR of (3, 6, 7, 10, 11)

= XOR of (1, 0, 1, 0, 1) = 1

P4 = XOR of (5, 6, 7, 12, 13)

= XOR of (1, 0, 1, 1, 0) = 1

P8 = XOR of (9, 10, 11, 12, 13)

= XOR of (1, 0, 1, 1, 0) = 1

11

12

11

12

13
0

13-bit code word = 1111101110110

7.12

Bit position

2
P1

(a)

P2
1

P4
1

10

13

P8

9-bit data word = 100110100

(b)
(c)

1
1
1
1
9-bit data word = 101000111
1

9-bit data word = 110011010

(d)

Bit position

8
1

9
1

10
1

11
0

12

13

C1 = XOR (1, 3, 5, 7, 9, 11, 13) = XOR (1, 1, 1, 1, 1, 1, 0) = 0

C2 = XOR (2, 3, 6, 7, 10, 11)

= XOR (0, 1, 0, 1, 0, 1)

=1

C4 = XOR (4, 5, 6, 7, 12, 13)

= XOR (1, 1, 0, 1, 1, 0)

=0

C8 = XOR (8, 9, 10, 11, 12, 13)

= XOR (1, 1, 0, 1, 1, 0)

=0

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245

C8C4C2C1 = 0010 bit 2 with error.

So, 9-bit data word 110110110

(e)

Bit position

1
0

2
0

3
0

6
0

7
0

8
0

9
1

10

11

12
0

13
1

C1 = XOR (1, 3, 5, 7, 9, 11, 13) = XOR (0, 0, 1, 0, 1, 1, 1) = 0

C2 = XOR (2, 3, 6, 7, 10, 11)

= XOR (0, 0, 0, 0, 0, 1)

=1

C4 = XOR (4, 5, 6, 7, 12, 13)

= XOR (0, 1, 0, 0, 0, 1)

=0

C8 = XOR (8, 9, 10, 11, 12, 13) = XOR (0, 1, 1, 0, 0, 1)

=0

C8C4C2C1 = 1010 bit 10 with error.

So, 9-bit data word 010011101

7.13

(a) 25 bits Check bits K = 5 6 parity bits

+1 bit

(b) 55 bits Check bits K = 6 7 parity bits

+1 bit

(c) 100 bits Check bits K = 7 8 parity bits

+1 bit
7.14

Bit position

(a)

P1

P2

3
P3

4
P4

P1 = XOR of (3, 5, 7, 9)

5
D5

6
D6

D7

P8

P9

= XOR of (0, 1, 0, 1) = 0

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246

P2 = XOR of (3, 6, 7)

= XOR of (0, 1, 0)

=1

P3 = XOR of (5, 6, 7)

= XOR of (1, 1, 0)

=0

P4 = XOR of (9)

= XOR of (1)

=1

Ans: 010011011
(b)

C1 = XOR of (1, 3, 5, 7, 9)

= XOR of (0, 0, 1, 0, 1) = 0

C2 = XOR of (2, 3, 6, 7)

= XOR of (1, 0, 1, 0)

=0

C4 = XOR of (4, 5, 6, 7)

= XOR of (0, 1, 1, 0)

=0

C8 = XOR of (8, 9)

= XOR of (1, 1)

=0

C
(c)

= C8C4C2C1 = 0000

9-bit composite word = 010010011

C1 = XOR of (1, 3, 5, 7, 9)

= XOR of (0, 0, 1, 0, 1) = 0

C2 = XOR of (2, 3, 6, 7)

= XOR of (1, 0, 0, 0)

=1

C4 = XOR of (4, 5, 6, 7)

= XOR of (0, 1, 0, 0)

=1

C8 = XOR of (8, 9)

= XOR of (1, 1)

=0

C8C4C2C1 = 0110 Error in bit 6 i.e., D6 = 1

(d)

Composite word : 0 1 0 0 1 1 0 1 1 P10

P10 = 1.
C1 = XOR of (1, 3, 5, 7, 9)

= XOR of (1, 1, 1, 0, 1) = 0

C2 = XOR of (2, 3, 6, 7, 10) = XOR of (1, 1, 1, 0, 1) = 0

C4 = XOR of (4, 5, 6, 7)

= XOR of (0, 1, 1, 0)

=0

C8 = XOR of (8, 9, 10)

= XOR of (1, 1, 1)

=1

P=0
Error in P1 and D3, so the composite word
1110110111
C8C4C2C1 = 1000 and P = 0 indicates double error.

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247

7.15

To construct 4K 8 ROM from 1K 8 we need 4 chips.

7.16

Total number of pins = Addr line + Data line + CS + 2

= 13 + 8 + 3 + 2
= 26 pins

7.17
Input Address

7.18

Output of ROM

I5 I4 I3 I2 I1

D6D5D4

D3D2D1

00000
00001

01000
01001

11110
11111

000
000

001
001

110
110

000
001

011
100

000
001

D0 (20) Decimal

0, 1
0, 1

0, 1
0, 1

0, 1
0, 1

0, 1
2, 3

16, 17
18, 19

60, 61
62, 63

(a) 5-bit binary multiplier:

Size of ROM = 210 10 = 1 K 10 ROM
(b) 5-bit adder-subtractor:
Size of ROM = 211 6 = 2 K 6 ROM

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248

(c) Quadruple 4 1 mux:

Size of ROM = 219 4 = 512 K 4 ROM
(d) 5 inputs 7 outputs
25 7
32 7 ROM
7.19

A(x, y, z) = (0, 2, 3, 7)
= xz + yz
A
= xy + xz + yz

B(x, y, z) = (1, 2, 4, 5, 6)
A(x, y, z) = yz + yz + xz

C(x, y, z) = (0, 1, 5, 7)
C(x, y, z) = xy + xz

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249

D(x, y, z) = (0, 2, 3, 4, 6)
D(x, y, z) = z + xy
D = Z(x + y) = xz + yz
PLA programming table:

Product term
1
2
3
4
5
6

xy
xz
yz
yz
xy
xz

Inputs
x y
1 0
1 - 0
- 1
0 0
1 -

z
0
1
0
1

Outputs
A B C
1 - 1 1 1 1 - 1 - - 1
- - 1
C T T

D
1
1
C

7.20

Inputs
w x
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0

y
0
0
1
1
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1
0
1
0
1

Outputs
A B C
0 1 0
1 0 1
0 1 1
1 0 0
0 1 0
1 0 1
0 1 1
1 0 1
0 1 1
1 0 0
0 1 0
1 0 0

D
1
0
0
1
1
0
0
1
1
0
0
1

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250

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

0
1
0
1

1
0
1
0

0
1
1
0

1
0
0
1

7.21 Note: See truth table in Fig. 7.12(b).

A2

A1

A1A0
00

01

m0

00
m0

m7

m6

A1

A1A0

m2

m5

10

m3

m4

A2

11

m1

A2

0
m4

A2

01
m1

0
m5

m7

01

00
m0

m7

m6

A1

A1A0

m2

m5

A2

10

m3

m4

A2

11

m1

m6

F2 = A2A'1 + A2A0
F2' = A'2 + A1A'0
A1

00

A0

A1A0
m0

10
m2

A0
F1 = A2A1
F'1 = A'2 + A'1

A2

11
m3

0
m4

A2

A0

01
m1

0
m5

11
m3

10
m2

0
m7

1
m6

A0

F3 = A'2A1A0 + A2A'1A0
F3' = A'0 + A'2A'1 +A2A1

F4 = A1A'0
F'4 = A'1 + A0

Product Inputs
Outputs
term A2A1A0 F1 F2 F3 F4
A2A1
A'2
A1A'0
A'2A1A0
A2A'1

1
2
3
4
5

1
0
1

1
1
1
0

0
1
1

1
T

1
1
C

1
1
T

1
T

Alternative: F'1, F'2, F3, F4

(5 terms)

7.22

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251

Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

0
1
4
9
16
25
36
49
64
81
100
121
144
169
196
225

w x y z

b7 b6 b5 b 4 b3 b 2 b 1 b0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1

0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1

0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
0

0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0

0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Note: b0 = z, and b1 = 0.
ROM would have 4 inputs
and 6 outputs. A 4 x 8
ROM would waste two
outputs.

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252

yz
wx

00

01
m1

m3

m2

m4

m5

m7

m6

00

m15

m14

m11

z
b2 = yx'

yz
wx

00

01
m1

m3

m2

m4

m5

m7

m6

1
m12

1
m13

m9

m11

m10

1
z
b3 = xy'z + x' yz
y
00

01

11

m0

m1

m3

m4

m5

m7

10
m2

m15

m8

m9

m11

m14

m12

m10

00
m0

m13

01
m1

11
m3

m15

1
m8

m9

00
m0

00

m11

m10

z
b5 = w'xy + wxz + wx'y
y

yz

10

m14

wx

m2

10

z
b4 = w'xz + xy'z' + wx' z
y

wx

m6

11

10

01
m1

11
m3

10
m2

00
m4

m5

m7

m6

m4

01

m5

m7

m6

01
m12

m13

11

m15

1
m8

10

m14

01

11

m15

00

01

yz

m8

yz

00

m13

wx

10

m0

m6

10

11

m7

11

10
m2

m12

m10

10

11
m3

m5

01

1
m9

m1

m4

11
m8

01

00

1
m13

00
m0

01

wx

10

m0

m12

yz

11

m9

m11

z
b6 = wy + wx'

m14

m12

1
m10

11
w

m13

1
m8

m15

1
m9

1
m11

m14

1
m10

10
z
b7 = wx

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253

7.23
Product Inputs
term A B C D

From Fig. 4-3:

w = A + BC + BD
w' = A'B' + A'C'D'
x = B'C + B'D + BC'D'
x' = B'C'D' + BC BD
y = CD + C'D'
y' = C'D + CD'
z = D'
z' = D
Use w, x', y, z (7 terms)

A
BC
BD
B'C'D'
CD
C'D'
D'

1
2
3
4
5
6
7

1
-

1
1
0
-

1
0
1
0
-

1
0
1
0
0

Outputs
F1 F2 F3 F4
1
1
1
-

1
1
1
-

1
1
-

T C T T

7.24
AND
Product Inputs
term A B C D
1
2
3
4
5
6
7
8
9
10
11
12

1
-

1
1
0
0
1
-

1
1
0
1
0
-

1
1
0
1
0
0
-

Outputs
w = A + BC + BD

x = B'C + B'D + BC'D'

y = CD + C'D'

z = D'

7.25

A = (1, 2, 4, 5, 6)
A = xy + yz + yz

B = (1, 2, 4, 5, 6, 7)
B = x + y'z + yz'
= xy + xy' + y'z+yz'
= A + xy

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254

C = (0, 2, 3, 4, 5, 7)
C = y'z' + x'y + xz

D = (1, 3, 4, 5, 7)
D = z + xy

xy
yz
yz
A
xy
yz
xy
xz
z
xy

Product term
1
2
3
4
5
6
7
8
9
10

x
1
1
0
1
1

Inputs
y z
0 0 1
1 0
- 1 0 0
1 - 1
- 1
0 -

Outputs
A
1
-

A = xy + yz + yz
B = A + xy

C = yz + xy + xz
D = z + xy

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255

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256

7.26

DA = (x y A)

= ((x y) A + (x y) A)
= xyA + xyA + xyA + xyA

7.27
The results of Prob. 6.17 can be used to develop the equations for a three-bit binary counter with D-type
flip-flops.
DA0 = A'0
DA1 = A'1A0 + A1A'0
DA2 = A'2 A1A0 + A2A'1 + A2A'0
Cout = A2A1A0

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257

Cout
0

A0

A1

10 11 12 13

A2
14 15

SET

CLR

A0

clock

SET

CLR

A1

clock

SET

CLR

clock

7.28

F1 = AB + BC + ABC
F2 = BC + AC + ABC

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A2

258

7.29

PLA programming table:

xyA
xyA
xyA
xyA

Product term
1
2
3
4

Inputs
x y
1 1
0 0
1 0
0 1

A
0
0
1
1

Outputs
DA
1
1
1
1

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