Section 14.

Motor Control PWM

HIGHLIGHTS
This section of the manual contains the following major topics: 14.1 Introduction .................................................................................................................. 14-2 14.2 Features of the MCPWM1 Module............................................................................... 14-2 14.3 Features of the MCPWM2 Module............................................................................... 14-3 14.4 Register Descriptions................................................................................................... 14-4 14.5 Special Function Registers .......................................................................................... 14-6 14.6 MCPWM Module Architecture Overview.................................................................... 14-19 14.7 MCPWM Module Operating Modes ........................................................................... 14-21 14.8 PWM Clock Control.................................................................................................... 14-22 14.9 Time Base Interrupts.................................................................................................. 14-26 14.10 PWM Output State Control......................................................................................... 14-27 14.11 PWM Output Modes................................................................................................... 14-28 14.12 Duty Cycle Register Buffering .................................................................................... 14-32 14.13 PWM Duty Cycle Resolution...................................................................................... 14-34 14.14 PWM Dead Time Control ........................................................................................... 14-36 14.15 PWM Fault Handling .................................................................................................. 14-40 14.16 Special Features of the MCPWM Module .................................................................. 14-43 14.17 Operation in Power-Saving Modes ............................................................................ 14-49 14.18 Register Maps............................................................................................................ 14-50 14.19 Related Application Notes.......................................................................................... 14-52 14.20 Revision History ......................................................................................................... 14-53

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Note: This family reference manual section is meant to serve as a complement to device data sheets. Depending on the device, this manual section may not apply to all dsPIC33F/PIC24H devices. Please consult the note at the beginning of the Motor Control PWM chapter in the current device data sheet to check whether this document supports the device you are using. Device data sheets and family reference manual sections are available for download from the Microchip Worldwide Web site at: http://www.microchip.com

14.1

INTRODUCTION
This section describes the Motor Control PWM (MCPWM) peripheral in the dsPIC33F/PIC24H family of devices.

14.1.1

Purpose of the MCPWM Module

The MCPWM is used to generate a periodic pulse waveform, which is useful in motor and power control applications. The MCPWM module acts as a timer to count up to a period count value. The time period and the duty cycle of the pulses are both programmable. Depending on the device, there are up to two MCPWM modules, MCPWM1 and MCPWM2, in the dsPIC33F/PIC24H family of devices. The features of these two modules are listed in 14.2 Features of the MCPWM1 Module and 14.3 Features of the MCPWM2 Module.

14.2

FEATURES OF THE MCPWM1 MODULE

The MCPWM1 module is used to generate multiple synchronized pulse-width modulated outputs. The following motor and power control applications are supported by the MCPWM1 module: Three-phase AC Induction Motor (ACIM) Switched Reluctance Motor Brushless DC (BLDC) Motor Uninterruptible Power Supply (UPS)

The distinctive features of the MCPWM1 module are summarized below: Up to eight PWM outputs with four duty cycle generators Dedicated time base that supports TCY/2 PWM edge resolution On-the-fly PWM frequency changes Hardware dead time generators Output pin polarity programmed by device Configuration bits Multiple operating and output modes: - Single event mode - Edge-aligned mode - Center-aligned mode - Center-aligned mode with double updates - Complementary Output mode - Independent Output mode Manual override register for PWM output pins Duty cycle updates that can be configured to be immediate or synchronized to the PWM Up to two hardware fault input pins with programmable function Special Event Trigger for synchronizing analog-to-digital conversions Output pins associated with the PWM can be individually enabled Note: Depending on the dsPIC33F/PIC24H device, there are different versions of the MCPWM1 module. Refer to the Motor Control PWM chapter in the specific device data sheet for more information.

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14.3 FEATURES OF THE MCPWM2 MODULE
The MCPWM2 module provides a pair of complementary PWM outputs, which are useful in the following applications: Independent Power Factor Correction (PFC) in a motor system Induction cooking systems Direct Current (DC) motor control systems Single-phase inverter control Single-phase ACIM control Two PWM outputs with one duty cycle generator Dedicated time base that supports TCY/2 PWM edge resolution On-the-fly PWM frequency changes Hardware dead time generator Output pin polarity programmed by device Configuration bits Multiple output and operating modes: - Single event mode - Edge-aligned mode - Center-aligned mode - Center-aligned mode with double updates - Complementary Operating mode Manual override register for PWM output pins Duty cycle updates that can be configured to be immediate or synchronized to the PWM A hardware fault input pin with programmable function Special Event Trigger for synchronizing analog-to-digital conversions Output pins associated with the PWM that can be individually enabled Note: The MCPWM2 module is present only in specific dsPIC33F/PIC24H devices. Refer to the Motor Control PWM chapter in the specific device data sheet for more information.

The distinctive features of the MCPWM2 module are summarized below:

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14.4 REGISTER DESCRIPTIONS
The following registers are used to control the operation of the MCPWM1 and MCPWM2 modules: Note: The letter x in the register names refers to the MCPWM module number.

PxTCON: PWM Time Base Control Register This register is used for the selection of Time Base mode, time base input clock prescaler, time base output postscaler, and for enabling the time base timer. PxTMR: PWM Time Base Register The time base count value and the time base count direction status are obtained in this register. PxTPER: PWM Time Base Period Register The PWM time base value is written into this register, which determines the PWM operating frequency. PxSECMP: Special Event Compare Register This register provides the compare value at which the analog-to-digital conversions are to be synchronized with the PWM time base. Comparison can be either during up-count or down-count in Center-aligned mode depending on the setting of the SEVTDIR bit in this register. PWMxCON1: PWM Control Register 1 Selection of either Independent or Complementary mode for each PWM I/O pair is performed in this register. PWMxCON2: PWM Control Register 2 This register provides the following selections: Selection of a PWM Special Event Trigger output postscaler value Immediate updating of duty cycle registers Selection of output override synchronization with the time base Enabling updates from duty cycle and period buffer registers

PxDTCON1: Dead Time Control Register 1 The dead time value and clock period prescaler for Dead Time Unit A and Dead Time Unit B can be selected using this register. PxDTCON2: Dead Time Control Register 2 Dead time insertions from Dead Time Unit A or Dead Time Unit B for each of the PWM outputs can be selected using this register. PxFLTACON: Fault A Control Register This register provides the following selections: - PWM output pin driven on an external fault active or inactive state - Fault mode Cycle-by-Cycle mode or Latched mode - Pin pair to be controlled or not controlled by Fault Input A PxFLTBCON: Fault B Control Register This register provides the following selections: - PWM output pin driven on an external fault active or inactive state - Fault mode Cycle-by-Cycle mode or Latched mode - Pin pair to be controlled or not controlled by Fault Input B PxOVDCON: Override Control Register This register is used for enabling the output override feature and for PWM output pin control selection. PxDC1: PWM Duty Cycle Register 1 The 16-bit PWM duty cycle value for the PWM output pair 1 is written into this register.

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PxDC2: PWM Duty Cycle Register 2 The 16-bit PWM duty cycle value for the PWM output pair 2 is written into this register. PxDC3: PWM Duty Cycle Register 3 The 16-bit PWM duty cycle value for the PWM output pair 3 is written into this register. PxDC4: PWM Duty Cycle Register 4 The 16-bit PWM duty cycle value for the PWM output pair 4 is written into this register. PWMxKEY: PWM Unlock Register This register enables the user to unlock the PWMxCON1, PxFLTACON and PxFLTBCON registers for write access. FPOR: POR Device Configuration Register In addition to the Special Function Registers (SFRs) associated with the MCPWM module, three device Configuration bits can be used to set up the initial Reset states and polarity of the PWM I/O pins. These device Configuration bits are located in the FPOR register. FOSCSEL: Oscillator Source Selection Register In addition to the SFRs associated with the MCPWM module, one device Configuration bit in this register can be used to set up the write-protect feature of the PWM Configuration registers.

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14.5 SPECIAL FUNCTION REGISTERS
PxTCON: PWM Time Base Control Register U-0 R/W-0 PTSIDL U-0 U-0 U-0 U-0 U-0 bit 8 R/W-0 R/W-0 PTOPS<3:0> R/W-0 R/W-0 R/W-0 PTCKPS<1:0> R/W-0 R/W-0 PTMOD<1:0> bit 0

Register 14-1: R/W-0 PTEN bit 15 R/W-0 bit 7 Legend: R = Readable bit

W = Writable bit 1 = Bit is set

U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown

-n = Value at POR bit 15

PTEN: PWM Time Base Timer Enable bit 1 = PWM time base is on 0 = PWM time base is off Unimplemented: Read as 0 PTSIDL: PWM Time Base Stop in Idle Mode bit 1 = PWM time base halts in CPU Idle mode 0 = PWM time base runs in CPU Idle mode Unimplemented: Read as 0 PTOPS<3:0>: PWM Time Base Output Postscale Select bits 1111 = 1:16 postscale 0001 = 1:2 postscale 0000 = 1:1 postscale PTCKPS<1:0>: PWM Time Base Input Clock Prescale Select bits 11 = PWM time base input clock period is 64 TCY (1:64 prescale) 10 = PWM time base input clock period is 16 TCY (1:16 prescale) 01 = PWM time base input clock period is 4 TCY (1:4 prescale) 00 = PWM time base input clock period is TCY (1:1 prescale) PTMOD<1:0>: PWM Time Base Mode Select bits 11 = PWM time base operates in Continuous Up/Down Count mode with interrupts for double PWM updates 10 = PWM time base operates in Continuous Up/Down Count mode 01 = PWM time base operates in Single Event mode 00 = PWM time base operates in Free Running mode

bit 14 bit 13

bit 12-8 bit 7-4

bit 3-2

bit 1-0

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Register 14-2: R-0 PTDIR bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown PxTMR: PWM Time Base Register R/W-0 R/W-0 R/W-0 R/W-0 PTMR<14:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 PTMR<7:0> R/W-0 R/W-0 R/W-0 bit 0

PTDIR: PWM Time Base Count Direction Status bit (read-only) 1 = PWM time base is counting down 0 = PWM time base is counting up PTMR<14:0>: PWM Time Base Register Count Value bits

bit 14-0

Register 14-3: U-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit

PxTPER: PWM Time Base Period Register R/W-0 R/W-0 R/W-0 R/W-0 PTPER <14:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 PTPER <7:0> R/W-0 R/W-0 R/W-0 bit 0

14
W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown

Motor Control PWM

-n = Value at POR bit 15 bit 14-0

Unimplemented: Read as 0 PTPER<14:0>: PWM Time Base Period Value bits

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Register 14-4: R/W-0 SEVTDIR(1) bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown PxSECMP: Special Event Compare Register R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<14:8>(2) R/W-0 R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<7:0>(2) R/W-0 R/W-0 R/W-0 bit 0

SEVTDIR: Special Event Trigger Time Base Direction bit(1) 1 = Special Event Trigger will occur when the PWM time base is counting down 0 = Special Event Trigger will occur when the PWM time base is counting up SEVTCMP <14:0>: Special Event Compare Value bits(2) SEVTDIR is compared with the PTDIR bit (PxTMR<15>) to generate the Special Event Trigger. SEVTCMP<14:0> is compared with the PTMR bit (PxTMR<14:0>) to generate the Special Event Trigger.

bit 14-0 Note 1: 2:

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Register 14-5: U-0 bit 15 R/W-y(1) PEN4H bit 7 Legend: R = Readable bit -n = Value at POR PWMxCON1: PWM Control Register 1 U-0 U-0 U-0 R/W-0 PMOD4 R/W-0 PMOD3 R/W-0 PMOD2 R/W-0 PMOD1 bit 8 R/W-y(1) PEN1L bit 0

R/W-y(1) PEN3H

R/W-y(1) PEN2H

R/W-y(1) PEN1H

R/W-y(1) PEN4L

R/W-y(1) PEN3L

R/W-y(1) PEN2L

y = Bit depends on configuration W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as 0 bit 11-8 PMOD4:PMOD1: PWM I/O Pair Mode bits 1 = PWM I/O pin pair is in Independent Output mode 0 = PWM I/O pin pair is in Complementary Output mode PEN4H:PEN1L: PWMxHy I/O Enable bits(1) 1 = PWMxHy(2,3) pin is enabled for PWM output 0 = PWMxHy(2,3) pin disabled; I/O pin becomes general purpose I/O The Reset condition of the PEN4H:PEN1H and PEN4L:PEN1L bits depend on the value of the PWMPIN device configuration bit in the FPOR register. When PWMPIN is set to 0, Reset values are 1 and when PWMPIN is set to 1, Reset values are 0. The letter x refers to the MCPWM module number. The letter y refers to the MCPWM Duty Cycle register number. In devices where the PWMLOCK configuration bit is present in the FOSCSEL configuration register, the PWMLOCK register can be write-protected. If the PWMLOCK bit (FOSCSEL<6>) is asserted (PWMLOCK = 1), the PWMxCON1 register is writable only after the proper sequence is written to the PWMxKEY register. If the PWMLOCK bit (FOSCSEL<6>) is deasserted (PWMLOCK = 0), the PWMxCON1 register is writable at any times. For more information on the unlock sequence, refer to 14.16.5 Write Protected Registers.

bit 7-0

Note 1:

2: 3: Note:

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Register 14-6: U-0 bit 15 U-0 bit 7 Legend: R = Readable bit -n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown PWMxCON2: PWM Control Register 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 SEVOPS<3:0> R/W-0 bit 8 U-0 U-0 U-0 U-0 R/W-0 IUE R/W-0 OSYNC R/W-0 UDIS bit 0

bit 15-12 Unimplemented: Read as 0 bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits 1111 = 1:16 postscale 0001 = 1:2 postscale 0000 = 1:1 postscale Unimplemented: Read as 0 IUE: Immediate Update Enable bit 1 = Updates to the active PxDCy(1,2) registers are immediate 0 = Updates to the active PxDCy(1,2) registers are synchronized to the PWM time base OSYNC: Output Override Synchronization bit 1 = Output overrides through the PxOVDCON(1) register are synchronized to the PWM time base 0 = Output overrides through the PxOVDCON(1) register occur on the next TCY boundary UDIS: PWM Update Disable bit 1 = Updates from duty cycle and period buffer registers are disabled 0 = Updates from duty cycle and period buffer registers are enabled The letter x refers to the MCPWM module number. The letter y refers to the MCPWM Duty Cycle register number.

bit 7-3 bit 2

bit 1

bit 0

Note 1: 2:

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Register 14-7: PxDTCON1: Dead Time Control Register 1 R/W-0 R/W-0 R/W-0 R/W-0 DTB<5:0> R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 DTA<5:0> R/W-0 R/W-0 bit 0

R/W-0 R/W-0 DTBPS<1:0> bit 15 R/W-0 R/W-0 DTAPS<1:0> bit 7 Legend: R = Readable bit -n = Value at POR

W = Writable bit 1 = Bit is set

U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown

bit 15-14 DTBPS<1:0>: Dead Time Unit B Prescale Select bits 11 = Clock period for Dead Time Unit B is 8 TCY 10 = Clock period for Dead Time Unit B is 4 TCY 01 = Clock period for Dead Time Unit B is 2 TCY 00 = Clock period for Dead Time Unit B is TCY bit 13-8 bit 7-6 DTB<5:0>: Unsigned 6-bit Dead Time Value bits for Dead Time Unit B DTAPS<1:0>: Dead Time Unit A Prescale Select bits 11 = Clock period for Dead Time Unit A is 8 TCY 10 = Clock period for Dead Time Unit A is 4 TCY 01 = Clock period for Dead Time Unit A is 2 TCY 00 = Clock period for Dead Time Unit A is TCY DTA<5:0>: Unsigned 6-bit Dead Time Value bits for Dead Time Unit A

bit 5-0

Register 14-8: U-0 bit 15 R/W-0 DTS4A bit 7 Legend: R = Readable bit

PxDTCON2: Dead Time Control Register 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 8

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R/W-0 DTS4I

R/W-0 DTS3A

R/W-0 DTS3I

R/W-0 DTS2A

R/W-0 DTS2I

R/W-0 DTS1A

R/W-0 DTS1I bit 0

W = Writable bit 1 = Bit is set

U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown

-n = Value at POR bit 15-8 bit 7-0

Unimplemented: Read as 0 DTS4A:DTS1I: Dead Time Select bits for PWM Signal Going Active 1 = Dead time provided from Dead Time Unit B 0 = Dead time provided from Dead Time Unit A

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Register 14-9: R/W-0 FAOV4H bit 15 R/W-0 FLTAM bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 PxFLTACON: Fault A Control Register R/W-0 FAOV4L R/W-0 FAOV3H R/W-0 FAOV3L R/W-0 FAOV2H R/W-0 FAOV2L R/W-0 FAOV1H R/W-0 FAOV1L bit 8 R/W-y(1) FAEN1(2) bit 0

U-0

U-0

U-0

R/W-y(1) FAEN4(2)

R/W-y(1) FAEN3(2)

R/W-y(1) FAEN2(2)

y = Bit depends on configuration W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown

FAOV4H:FAOV1L: Fault Input A PWM Override Value bits 1 = PWM output pin is driven Active on an external fault input event 0 = PWM output pin is driven Inactive on an external fault input event FLTAM: Fault A Mode bit 1 = Fault A input pin functions in Cycle-by-Cycle mode 0 = Fault A input pin latches all control pins to the programmed states in PxFLTACON<15:8> Unimplemented: Read as 0 FAEN4:FAEN1: Fault Input A Enable bit(1,2) 1 = PWMxHy/PWMxLy(3,4) pin pair is controlled by Fault Input A 0 = PWMxHy/PWMxLy(3,4) pin pair is not controlled by Fault Input A In devices where the PWMLOCK bit is present in the FOSCSEL configuration register, the Reset value for this bit is 1. In all other configurations, the Reset value for this bit is 0. Refer to the Motor Control PWM chapter in the specific device data sheet for more information. The fault pin A has priority over fault pin B, if enabled. The letter x refers to the MCPWM module number. The letter y refers to the MCPWM Duty Cycle register number. In devices where the PWMLOCK bit is present in the FOSCSEL<6> configuration register, the PWMLOCK register can be write-protected. If the PWMLOCK bit (FOSCSEL<6>) is asserted (PWMLOCK = 1), the PxFLTACON register is writable only after the proper sequence is written to the PWMxKEY register. If the PWMLOCK bit (FOSCSEL<6>) is deasserted (PWMLOCK = 0), the PxFLTACON register is writable at any time. For more information on the unlock sequence, refer to 14.16.5 Write Protected Registers.

bit 7

bit 6-4 bit 3-0

Note 1:

2: 3: 4: Note:

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Register 14-10: PxFLTBCON: Fault B Control Register R/W-0 FBOV4H bit 15 R/W-0 FLTBM bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 R/W-0 FBOV4L R/W-0 FBOV3H R/W-0 FBOV3L R/W-0 FBOV2H R/W-0 FBOV2L R/W-0 FBOV1H R/W-0 FBOV1L bit 8 R/W-y(1) FBEN1(2) bit 0

U-0

U-0

U-0

R/W-y(1) FBEN4(2)

R/W-y(1) FBEN3(2)

R/W-y(1) FBEN2(2)

y = Bit depends on configuration W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown

FBOV4H:FBOV1L: Fault Input B PWM Override Value bits 1 = PWM output pin is driven Active on an external fault input event 0 = PWM output pin is driven Inactive on an external fault input event FLTBM: Fault B Mode bit 1 = Fault B input pin functions in Cycle-by-Cycle mode 0 = Fault B input pin latches all control pins to the programmed states in PxFLTBCON<15:8> Unimplemented: Read as 0 FBEN4:FBEN1: Fault Input B Enable bit(1,2) 1 = PWMxHy/PWMxLy(3,4) pin pair is controlled by Fault Input B 0 = PWMxHy/PWMxLy(3,4) pin pair is not controlled by Fault Input B In devices where the PWMLOCK configuration bit is present in the FOSCSEL configuration register, the Reset value for this bit is 1. In all other configurations, the Reset value for this bit is 0. Refer to the Motor Control PWM chapter in the specific device data sheet for more information. Fault pin A has priority over fault pin B, if enabled. The letter x refers to the MCPWM module number. The letter y refers to the MCPWM duty cycle generator number In devices where the PWMLOCK configuration bit is present in the FOSCSEL configuration register, the PWMLOCK register can be write-protected. If the PWMLOCK bit (FOSCSEL<6>) is asserted (PWMLOCK = 1), the PxFLTACON register is writable only after the sequence is written to the PWMxKEY register. If the PWMLOCK bit (FOSCSEL<6>) is deasserted (PWMLOCK = 0), the PxFLTACON register is writable at any time. For more information on the unlock sequence, refer to 14.16.5 Write Protected Registers.

bit 7

bit 6-4 bit 3-0

Note 1:

2: 3: 4: Note:

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Register 14-11: PxOVDCON: Override Control Register R/W-1 POVD4H bit 15 R/W-0 POUT4H bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown R/W-1 POVD4L R/W-1 POVD3H R/W-1 POVD3L R/W-1 POVD2H R/W-1 POVD2L R/W-1 POVD1H R/W-1 POVD1L bit 8 R/W-0 POUT1L bit 0

R/W-0 POUT4L

R/W-0 POUT3H

R/W-0 POUT3L

R/W-0 POUT2H

R/W-0 POUT2L

R/W-0 POUT1H

POVD4H:POVD1L: PWM Output Override bits 1 = Output on PWMxHy/PWMxLy(1,2) I/O pin is controlled by the PWM generator 0 = Output on PWMxHy/PWMxLy(1,2) I/O pin is driven, controlled by the value in the corresponding POUTyH/POUTyL(2) bit POUT4H:POUT1L: PWM Manual Output bits 1 = PWMxHy/PWMxLy I/O pin is driven Active when the corresponding POVDyH/POVDyL(2) bit is cleared 0 = PWMxHy/PWMxLy I/O pin is driven Inactive when the corresponding POVDyH/POVDyL(2) bit is cleared The letter x refers to the MCPWM module number. The letter y refers to the MCPWM duty cycle generator number.

bit 7-0

Note 1: 2:

Register 14-12: PxDC1: PWM Duty Cycle Register 1 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 PxDC1<7:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxDC1<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0

PxDC1<15:0>: PWM Duty Cycle 1 Value bits

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Register 14-13: PxDC2: PWM Duty Cycle Register 2 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 PxDC2<7:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxDC2<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0

PxDC2<15:0>: PWM Duty Cycle 2 Value bits

Register 14-14: PxDC3: PWM Duty Cycle Register 3 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 PxDC3<7:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxDC3<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0

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PxDC3<15:0>: PWM Duty Cycle 3 Value bits

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Register 14-15: PxDC4: PWM Duty Cycle Register 4 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 PxDC4<7:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxDC4<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0

PxDC4<15:0>: PWM Duty Cycle 4 Value bits

Register 14-16: PWMxKEY: PWM Unlock Register R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 Note 1: W = Writable bit 1 = Bit is set U = Unimplemented, read as 0 0 = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 PWMKEY<7:0>(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWMKEY<15:8>(1) R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0

PWMxKEY<15:0>: PWM Unlock bits(1) If the PWMLOCK configuration bit is asserted (PWMLOCK = 1), the PWMxCON1, PxFLTACON and PxFLTBCON registers are writable only after the proper sequence is written to the PWMxKEY register. If the PWMLOCK configuration bit is deasserted (PWMLOCK = 0), the PWMxCON1, PxFLTACON and PxFLTBCON registers are writable at any time. For more information on the unlock sequence, refer to 14.16.5 Write Protected Registers. This register is implemented only in devices where the PWMLOCK configuration bit is present in the FOSCSEL configuration register.

Note:

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Register 14-17: FPOR: POR Device Configuration Register U-1 bit 23 U-1 bit 15 R/P PWMPIN bit 7 Legend: R = Readable bit -n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown R/P HPOL R/P LPOL R/P ALTI2C R/P BOREN R/P R/P FPWRT<2:0> bit0 R/P U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 bit 16 U-1 bit 8

P = Programmable configuration bit bit 23-8 bit 7 Unimplemented: Read as 1 PWMPIN: Motor Control PWM Module Pin Mode bit 1 = PWM module pins controlled by the PORT register at device Reset (tri-stated) until the PTEN bit is set 0 = PWM module pins controlled by the PWM module at device Reset HPOL: Motor Control PWM High-side Polarity bit 1 = MCPWM module high-side output pins have active-high output polarity 0 = MCPWM module high-side output pins have active-low output polarity LPOL: Motor Control PWM Low-side Polarity bit 1 = MCPWM module low-side output pins have active-high output polarity 0 = MCPWM module low-side output pins have active-low output polarity These bits are not used by the MCPWM module. For more information, refer to Section 25. Device Configuration (DS70194).

bit 6

bit 5

bit 4-0

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Register 14-18: FOSCSEL: Oscillator Source Selection Register R-x IESO bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 P = Programmable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown R-x PWMLOCK U-0 U-0 U-0 R-x R-x FNOSC<2:0> bit 0 R-x

IESO: Not used by the MCPWM module. Refer to the Special Features chapter in the specific device data sheet for more information. PWMLOCK: Motor Control PWM Unlock bit 1 = MCPWM module registers, PWMxCON1, PxFLTACON and PxFLTBCON, are write-protected 0 = MCPWM module registers are not write-protected Unimplemented: Read as 0 These bits are not used by the MCPWM module. Refer to the Special Features chapter in the specific device data sheet for more information.

bit 5-3 bit 2-0

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14.6 MCPWM MODULE ARCHITECTURE OVERVIEW
Figure 14-1 illustrates a block diagram of the MCPWM module for dsPIC33F/PIC24H devices. Figure 14-1: Block Diagram of the MCPWM Module

REGISTERS PX TCON PWM Time Base Control

PWMxCON1 PWM Enable and Mode Selection PWMxCON2

PxDTCON1 PWM Dead Time Control PXDTCON2

16-bit DATA BUS

PXFLTACON Fault Pin Control PXFLTBCON

PXOVDCON

Manual Override Control External Fault Signals

PWMXKEY

PWM Register Lock Control

FLTxA FLTxB Dead Time Generator and Override Control PWMXHY Driver PWMXLY PWM Output

PXDCY Buffer

PXDCY Register PWM Duty Cycle

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Motor Control PWM

PXTMR

PXTPER Buffer

PXTPER Register PWM Period

PWM Timer Reset/Count Output

PXSECMP SEVTDIR PTDIR

Special 1:1 Event Trigger Postscaler 1:16

Special Event Trigger for Analog-to-Digital Conversions

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14.6.1 Duty Cycle

The MCPWM module has up to four PWM generators. There are four special function PWM Duty Cycle registers (PxDCy) associated with the MCPWM module to specify the duty cycle values for the PWM generators. The duty cycle gives the time for which the PWM pulses are active in a given PWM time period. Note 1: 2: The letter x refers to the MCPWM module number. The letter y refers to the MCPWM Duty Cycle register number.

14.6.2

Dead Time Generation

Dead time generation is automatically enabled when any of the PWM I/O pin pairs are operating in Complementary Output mode. As the power devices cannot switch instantaneously, some time must be provided between the turn-off event of one PWM output in a complementary pair and the turn-on event of the other transistor. There are two programmable dead time values. To increase user software flexibility, these dead times can be used in either of the two methods described below: The PWM output signals can be optimized for different turn-off times in the high-side and low-side transistors. The first dead time is inserted between the turn-off event of the lower transistor of the complementary pair and the turn-on event of the upper transistor. The second dead time is inserted between the turn-off event of the upper transistor and the turn-on event of the lower transistor. The two dead times can be assigned to individual PWM I/O pairs. This operating mode allows the MCPWM module to drive different transistor/load combinations with each complementary PWM I/O pair. There are up to two dead time generation units, A and B, that can be configured in the Dead Time Control registers, PxDTCON1 and PxDTCON2.

14.6.3

Output Override Control

The MCPWM module output override feature allows the user software to manually drive the PWM I/O pins to the specified logic states independent of the duty cycle comparison units. The PWM Output Override bits (POVD4H:POVD1L) in the Override Control register (PxOVDCON<15:8>) are useful when controlling various types of electrically commutated motors. The output override (PxOVDCON<15:8>). feature can be controlled using the POVD4H:POVD1L bits

14.6.4

Special Event Trigger

The MCPWM module has a Special Event Trigger that allows analog-to-digital conversions to be synchronized to the PWM time base. The analog-to-digital sampling and conversion time may be programmed to occur at any point within the PWM period. The Special Event Compare register (PxSECMP) specifies the special event compare value for generating the Special Event Trigger to start analog-to-digital conversion. Note: Detailed descriptions of the PWM timer, PWM time base period, output override feature and Special Event Trigger are provided in the subsequent sections.

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14.7 MCPWM MODULE OPERATING MODES
The MCPWM module can be configured for one of four modes of operation using the PWM Time Base Mode Select Control bits (PTMOD) in the PWM Time Base Control register (PxTCON<1:0>). The four operating modes are described in the following sections.

14.7.1

Free Running Mode (PTMOD<1:0> = 0b00)

In this mode, the PWM Time Base register (PxTMR) will count upward until the value in the PWM Time Base Period register (PxTPER) is matched. The PxTMR register is reset on the next input clock edge. The timer will continue counting upward and resetting until the PWM Time Base Timer Enable bit (PTEN) in the PWM Time Base Control register (PxTCON<15>) remains set.

14.7.2

Single Event Mode (PTMOD<1:0> = 0b01)

The PxTMR register will begin counting upward when the PTEN bit (PxTCON<15>) is set. When the PxTMR value matches the PxTPER register value, the PxTMR register is reset on the next input clock edge, and the PTEN bit (PxTCON<15>) is cleared by the hardware to halt the timer.

14.7.3

Continuous Up/Down Count Mode (PTMOD<1:0> = 0b10)

In this mode, the PxTMR register will count upward until the value in the PxTPER register is matched. The timer will start counting downward on the following clock edge and continue counting down until it reaches zero. The PWM Time Base Count Direction Status bit, PTDIR (PxTMR<15>) indicates the counting direction. The PTDIR bit (PxTMR<15>) is set when the timer starts counting downward.

14.7.4

Continuous Up/Down Count Mode with Interrupts for Double Update of Duty Cycle (PTMOD<1:0> = 0b11)

This mode is similar to the Continuous Up/Down Count mode, with the exception that an interrupt event is generated twice per time base: once when the PxTMR register is equal to zero and a second time when a period match occurs.

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14.8 PWM CLOCK CONTROL
The time base for the PWM pulses is provided by the 15-bit timer with prescale and postscale options, as illustrated in Figure 14-2. Figure 14-2: PWM Clock Control
Gated Period Load PWM Period Buffer PWM Period Register (PXTPER) PTEN Clock Control Logic PTMR Clock PTMOD<1:0> PWM Timer Register (PXTMR) Period Compare Period Load

Zero Match Time Base 1:1 1:4 Input Prescaler 1:16 1:64 Period Match

TCY

Zero-Detect 0

Timer Direction Control Gated Duty Cycle Update Disable (UDIS) Immediate Update Enable (IUE)

PTMOD1 Reset Up/Down Count

PTDIR Period Match 1:1

Time Base Output Postscaler

Interrupt Control

PWM Interrupt Flag (PWMxIF)

1:16

PTMOD<1:0>

14.8.1

Time Base Input Prescaler

The input clock (TCY) derived from the oscillator source can be prescaled to four possible options: 1:1, 1:4, 1:16, and 1:64. These options can be selected by using the PWM Time Base Input Clock Prescale Select bits, PTCKPS<1:0> (PxTCON<3:2>). The prescaled clock is the input to the PWM clock control logic block.

14.8.2

Clock Control Logic and Time Base

The PWM clock control logic block determines the nature of the PWM timer output, depending on the time period match, zero match and PTMOD<1:0> (PxTCON<1:0>). The time base input prescaler counter is cleared when any of the following occurs: A write to the PxTMR register A write to the PxTCON register A device Reset The PxTMR register is not cleared when PxTCON is written. The time base value of the PWM Time Base Register Count Value bits, PTMR<14:0> (PxTMR<14:0>) is compared with the contents of the PxTPER register. If a match occurs, a period match signal is generated. If the time base value of the PTMR<14:0> (PxTMR<14:0>) is zero, a zero detect signal is generated.

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14.8.3 Timer Direction Control

The timer direction control block determines the count direction. The PTDIR bit (PxTMR<15>) is a read-only bit that gives the current direction of the count. If the PTDIR bit (PxTMR<15>) is cleared, the PxTMR register is counting upward. If the PTDIR bit (PxTMR<15>) is set, the PxTMR register is counting downward. The time base is enabled or disabled by setting or clearing the PTEN bit (PxTCON<15>). The PxTMR register is not cleared when the PTEN bit (PxTCON<15>) is cleared in user software.

14.8.4

Time Base Output Postscaler

The time base output postscaler is used to optionally select one of the several possible options (1:1 to 1:16, scaling inclusive) to postscale the timer output. The interrupt control logic decides when to set the PWM Interrupt Flag, PWMxIF, for generating a PWM interrupt, depending on the postscale value. The postscaler is useful when the PWM duty cycles need not be updated every PWM cycle. The time base output postscaler counter is cleared when any of the following occurs: A write to the PxTMR register A write to the PxTCON register A device Reset The PxTMR register is not cleared when the PxTCON register is written.

14.8.5

PWM Time Period

The PxTPER register determines the counting period for the PxTMR register. The user software must write a 15-bit value into the PWM Time Base Period register (PxTPER). When the value of the PTMR bit (PxTMR<14:0>) matches the value of the PTPER bit (PxTPER<14:0>), the time base will either reset to zero or reverse the count direction on the next clock input edge. The action taken depends on the operating mode of the time base. The time base period is double-buffered to allow run-time changes of the time period of the PWM signal without any glitches. The PxTPER register serves as a buffer to the actual register, which is not accessible by the user software. The PxTPER register contents are loaded into the actual Time Base Period register at the following times: Free Running and Single Event modes: when the PxTMR register is reset to zero after a match with the PxTPER register Up/Down Count modes: when the PxTMR register is zero The value held in the PxTPER register is automatically loaded into the PxTPER register when the PWM time base is disabled (PTEN = 0). Figure 14-3 and Figure 14-4 illustrate the times when the contents of the PxTPER register are loaded into the time base period register. Figure 14-3: PWM Period Buffer Updates in Free Running Count Mode
Period Value Loaded from PxTPER Buffer Register

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PxTMR Value New PxTPER Value Old PxTPER Value

New Value Written to PxTPER Buffer

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Equation 14-1 provides the formula to determine the PWM period for Free Running mode. Equation 14-2 provides the formula to determine the PWM period for Up/Down Count mode. Equation 14-1: PWM Period Calculation for Free Running Count Mode (PTMOD = 00 or 01) F CY -1 PxTPER = -------------------------------------------------------------------F PWM PxTMR Prescaler Where, FCY = Clock Frequency FPWM = PWM Frequency PXTMR Prescaler = PWM Prescaler Example: FCY = 20 MHz FPWM = 20,000 Hz PxTMR Prescaler = 1:1 000 000 PxTPER = 20 -----------------------------1 20 000 1 PxTPER = 1000 1 PxTPER = 999

Figure 14-4:

PWM Period Buffer Updates in Up/Down Count Modes

Period Value Loaded from PxTPER Buffer Register

New PxTPER Value PxTMR Value Old PxTPER Value

New Value Written to PxTPER Buffer

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Equation 14-2: PWM Period Calculation in Up/Down Count Modes (PTMOD = 10 or 11) F CY -1 PxTPER = ----------------------------------------------------------------------------F PWM PxTMR Prescaler 2 Where, FCY = Clock Frequency FPWM = PWM Frequency PXTMR Prescaler = PWM Prescaler Example: FCY = 20 MHz FPWM = 20,000 Hz PxTMR Prescaler = 1:1 20 000 000 - 1 PxTPER = ----------------------------------20 000 1 2 PxTPER = 500 1 PxTPER = 499

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14.9 TIME BASE INTERRUPTS
The generation of PWM interrupts depends on the mode of operation selected by the PTMOD<1:0> bits (PxTCON<1:0>), and the time base output postscaler selected using the PWM Time Base Output Postscale Select bits, PTOPS<3:0> (PxTCON<7:4>). The interrupt generation for each of the operating modes is described in the following sections.

14.9.1

Free Running Mode

An interrupt event is generated when the PxTMR register is reset to 0 due to a match with the PxTPER register. The postscaler selection bits can be used in Free Running mode, to reduce the frequency of the interrupt events.

14.9.2

Single Event Mode

An interrupt event is generated when the PxTMR register is reset to 0 due to a match with the PxTPER register. The PTEN bit (PxTCON<15>) is also cleared to stop further PxTMR register increments. The postscaler selection bits have no effect in Single Event mode.

14.9.3

Up/Down Count Mode

An interrupt event is generated each time the value of the PxTMR register is equal to zero and the PWM time base begins to count upward. The postscale selection can be used to reduce the frequency of interrupt events in Up/Down Count mode.

14.9.4

Up/Down Count Mode with Double Update of Duty Cycle

An interrupt event is generated each time the PxTMR register is equal to zero and each time a period match occurs. The postscale selection has no effect in Up/Down Count mode with Double Update of Duty Cycle. This mode allows the control loop bandwidth to be doubled because the PWM duty cycles can be updated twice per period. Every rising and falling edge of the PWM signal can be controlled using Double Update mode. On generation of a PWM interrupt, the PWM Interrupt Flag (PWMIF) is set in the corresponding IFSx register. Note: For more informations refer to the Interrupts chapter in the specific device data sheet, or refer to Section 41. Interrupts (Part IV) (DS70300) in the dsPIC33F/PIC24H Family Reference Manual.

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14.10 PWM OUTPUT STATE CONTROL
The PWM High and Low I/O Enable bits (PENyH and PENyL) in the PWM Control Register 1 (PWMxCON1<7:0>) enable each PWM output pin for use by the MCPWM module. When a pin is enabled for the PWM output, the PORT and TRIS registers controlling the pin are disabled. Note: The letter y refers to the MCPWM duty cycle generator number.

In addition to the PENyH and PENyL control bits, three device Configuration bits in the POR Device Configuration register (FPOR) provide PWM output pin control. This register contains the following configuration bits: MCPWM High-side Drivers PWMyH Polarity bit (HPOL) MCPWM Low-side Drivers PWMyL Polarity bit (LPOL) MCPWM Drivers Initialization bit (PWMPIN) These three configuration bits work in conjunction with the PENxH and PENxL bits located in the PWMxCON1 register. These configuration bits ensure that the PWM pins are in the correct states after a device Reset.

14.10.1 Output Polarity Control

The polarity of the PWM I/O pins is set during device programming using the HPOL (FPOR<6>) and LPOL (FPOR<6>) configuration bits. The HPOL bit (FPOR<6>) sets the output polarity for the high-side PWM outputs, PWMxH1:PWMxH4. The LPOL bit (FPOR<6>) sets the output polarity for the low-side PWM outputs, PWMxL1:PWMxL4. If the polarity configuration bit is set to 1, the corresponding PWM I/O pins will have active-high output polarity. If the polarity configuration bit is set to 0, the corresponding PWM pins will have active-low polarity.

14.10.2 PWM Output Pin Reset States

The Motor Control PWM Module Pin Mode configuration bit, PWMPIN (FPOR<7>) determines the behavior of the PWM output pins on a device Reset, and can be used to eliminate external pull-up/pull-down resistors connected to the devices controlled by the MCPWM module. If the PWMPIN bit (FPOR<7>) is set to 1, the PENyH and PENyL control bits will be cleared on a device Reset. Consequently, all PWM outputs are tri-stated and controlled by the corresponding PORT and TRIS registers. If the PWMPIN bit (FPOR<7>) is set to 0, the PENyH and PENyL control bits are set on a device Reset. All PWM pins are enabled for PWM output at the device Reset, and are at their inactive states as defined by the HPOL bit (FPOR<6>) and the LPOL bit (FPOR<6>). Note: The letter y refers to the MCPWM duty cycle generator number.

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14.11 PWM OUTPUT MODES
This section describes the PWM output modes.

14.11.1 Single Event PWM Operation

The MCPWM module produces single pulse outputs when the PWM time base is configured for Single Event mode (PTMOD<1:0> = 01). This mode of operation is useful for driving certain types of electronically commutated motors, such as high-speed switched reluctance motor operation. Only edge-aligned outputs can be produced in Single Event mode. In Single Event mode, the PWM I/O pin(s) are driven to the active state when the PTEN bit (PxTCON<15>) is set. When a match with a duty cycle register occurs, the PWM I/O pin is driven to the inactive state. When a match with the PxTPER register occurs, the PxTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit (PxTCON<15>) is cleared and an interrupt is generated. Operation of the MCPWM module stops until the PTEN bit (PxTCON<15>) is set again in user software. Figure 14-5 illustrates the operation of single event PWM. Figure 14-5: Single Event PWM Operation
PTEN Bit Set by the User Software PTEN Bit Cleared by Hardware PXTPER PXDC1 PXDC2

PTEN PWMXH2 PWMXH1

PWMXIF

PWMXIF Cleared in the User Software

14.11.2 Edge-aligned PWM

The MCPWM module produces edge-aligned PWM signals when the PWM time base is operating in Free Running mode. The output signal for a given PWM channel has a period specified by the value loaded in the PxTPER register, and a duty cycle specified by the specific PxDCy register (see Figure 14-6). Assuming a non-zero duty cycle and no immediate updates enabled (IUE = 0), the outputs of all enabled PWM generators will be driven active at the beginning of the PWM period (PxTMR = 0). Each PWM output will be driven inactive when the value of PxTMR matches the duty cycle value of the PWM generator. If the value in the PxDCy register is zero, the output on the corresponding PWM pin is inactive for the entire PWM period. In addition, the output on the PWM pin is active for the entire PWM period if the value in the PxDCy register is greater than the value held in the PxTPER register. If immediate updates are enabled (IUE = 1), the new duty cycle value will be loaded when the new value is written to any active PxDCy register.

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Figure 14-6: Edge-aligned PWM
New Duty Cycle Loaded from PXDCY PXTPER PXDC1 PxTMR Value PXDC2 0 PWMXH1 Duty Cycle

PWMXH2 Period

14.11.3 Center-aligned PWM

The MCPWM module produces center-aligned PWM signals when the PWM time base is configured in one of the two Up/Down Count modes (PTMOD<1:0> = 1x). The PWM compare output is driven to the active state when the value of the duty cycle register matches the value of PxTMR and the PWM time base is counting downward (PTDIR = 1). The PWM compare output is driven to the inactive state when the PWM time base is counting upward (PTDIR = 0) and the value in the PxTMR register matches the duty cycle value. If the value in a particular duty cycle register is zero, the output on the corresponding PWM pin is inactive for the entire PWM period. In addition, the output on the PWM pin is active for the entire PWM period if the value in the duty cycle register is greater than the value in the PxTPER register. Figure 14-7 illustrates the operation of the center-aligned PWM. Figure 14-7: Center-aligned PWM
Period/2 PXTPER PXDC1 PXDC2 0 PWMXH1 PWMXH2 PXDC2 Value Period PXTMR Value

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14.11.4 Complementary PWM Output Mode
Complementary PWM Output mode is used to drive inverter loads similar to the one illustrated in Figure 14-8. This inverter topology is typical for ACIM and BLDC applications. In Complementary PWM Output mode, a pair of PWM outputs cannot be active simultaneously. Each PWM channel and output pin pair is internally configured as illustrated in Figure 14-9. A dead time can be optionally inserted during device switching, making both outputs inactive for a short period. For more information, refer to 14.16 Special Features of the MCPWM Module. Figure 14-8: Typical Load for Complementary PWM Outputs
+V 3-Phase Load

1H

2H

3H

1L

2L

3L

Complementary PWM Output mode is selected for each PWM I/O pin pair by clearing the PWM I/O Pair Mode bit (PMOD) in the PWM Control Register 1 (PWMxCON1<11:8>). The PWM I/O pins are set to Complementary PWM Output mode by default on a device Reset. Figure 14-9: PWM Channel Block Diagram, Complementary PWM Output Mode

PWM Generator Dead Time Generator Override and Fault Logic

PWMXH

PWMXL

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14.11.5 Independent PWM Output Mode
Independent PWM Output mode is useful for driving loads, as illustrated in Figure 14-10. A specific PWM output pair is in Independent PWM Output mode when the corresponding PWM I/O Pair Mode bit (PMOD) in the PWM Control Register 1 (PWMxCON1<11:8>) is set. The dead time generators are disabled in Independent PWM Output mode, and there are no restrictions on the state of the pins for a given output pin pair. Figure 14-11 illustrates the PWM block diagram for one output pin pair Independent PWM Output mode. Figure 14-10: Asymmetric Inverter Load Using Independent PWM Output Mode
+V

1H

1L

Figure 14-11:

PWM Block Diagram for One Output Pin Pair Independent PWM Output Mode

PWM Generator

Override and Fault Logic

PWMxH

PWMxL

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14.12 DUTY CYCLE REGISTER BUFFERING
The four PWM Duty Cycle registers, PxDC1 through PxDC4, are buffered to allow glitchless updates of the PWM outputs. For each generator, there is a PxDCy register (buffer register) that is accessible by the user software and a non-memory mapped Duty Cycle register that holds the actual compare value. The PWM duty cycle is updated with the value in the PxDCy register at specific times in the PWM period to avoid glitches in the PWM output signal. When the PWM time base is operating in Free Running or Single Event mode (PTMOD<1:0> = 0x), the PWM duty cycle is updated whenever a match with the PxTPER register occurs and PxTMR is reset to 0. Note: Any write to the PxDCy registers immediately updates the duty cycle when the PWM time base is disabled (PTEN = 0). This allows a duty cycle change to take effect before PWM signal generation is enabled.

When the PWM time base is operating in Up/Down Count mode (PTMOD<1:0> = 10), duty cycles are updated when the value of the PxTMR register is zero and the PWM time base begins to count upward. Figure 14-12 indicates the times when the duty cycle updates occur for Up/Down Count mode. When the PWM time base is in Up/Down Count mode with double updates (PTMOD<1:0> = 11), duty cycles are updated when the value of the PxTMR register is zero and when the value of the PxTMR register matches the value in the PxTPER register. Figure 14-12 and Figure 14-13 indicate the times when the duty cycle updates occur for Up/Down Count mode of the PWM time base. Figure 14-12: Duty Cycle Update Times in Up/Down Count Mode
Duty Cycle Value Loaded from PXDCY Register, CPU Interrupted

PWM Output

PXTMR Value

New Value Written to PXDCY Register

Figure 14-13: Duty Cycle Update Times in Up/Down Count Mode with Double Updates
Duty Cycle Value Loaded from PXDCY Register, CPU Interrupted

PWM Output

PXTMR Value

New Values Written to PXDCY Register

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14.12.1 Immediate Update of PWM Duty Cycle
The Immediate Update Enable bit (IUE) in the PWM Control Register 2 (PWMxCON2<2>) provides an option for updating the duty cycle values immediately after a write to the duty cycle registers. This feature eliminates waiting for the end of the time base period to update the duty cycle values. If the IUE bit (PWMxCON2<2>) is set, an immediate update of the duty cycle is enabled. If the IUE bit (PWMxCON2<2>) is cleared, immediate update of the duty cycle is disabled. The following three cases are possible when immediate update is enabled: Case 1: If the PWM output is active at the time the new duty cycle is written and the new duty cycle is greater than the current time base value, the PWM pulse width is increased. Case 2: If the PWM output is active at the time the new duty cycle is written and the new duty cycle is less than the current time base value, the PWM pulse width is reduced. Case 3: If the PWM output is inactive at the time the new duty cycle is written and the new duty cycle is greater than the current time base value, the PWM output becomes active immediately and remains active for the newly written duty cycle value. Figure 14-14 illustrates the above mentioned cases. Figure 14-14: Duty Cycle Update Times When Immediate Updates are Enabled (IUE = 1)

New Values Written to PXDCY Register

Latest Duty Cycle Value Written to PXDCY

50%

90%

10%

90%

PWM Output Case 2 Case 3

Case 1

PXTMR Value

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14.13 PWM DUTY CYCLE RESOLUTION
In the MCPWM module, the effective resolution for the generated PWM pulses is a function of the PWM frequency (or period) and the device operating frequency. The maximum resolution (in bits) for a selected device oscillator and PWM frequency can be determined using the formula shown in Equation 14-3. Equation 14-3: PWM Resolution 2 F CY PWM Resolution = log 2 ------------- F PWM Where, FPWM = PWM switching frequency FCY = Device operating frequency

Table 14-1 provides the PWM resolutions and PWM frequencies for different clock frequencies and PxTPER values. The PWM frequencies provided in Table 14-1 are for edge-aligned (Free Running PxTMR) PWM mode. For center-aligned modes (Up/Down PxTMR mode), the PWM frequencies are half the values in Table 14-1, as indicated in Table 14-2. Table 14-1: Example of PWM Frequencies and Resolutions, 1:1 Prescaler, Edge-aligned PWM PxTPER Value 0x7FFE 0x3FE 0x7FFE 0x1FE 0x7FFE 0xFE 0x7FFE 0x7E PXDCY Value for 100% 0xFFFE 0x7FE 0xFFFE 0x3FE 0xFFFE 0x1FE 0xFFFE 0xFE PWM Resolution 16 bits 11 bits 16 bits 10 bits 16 bits 9 bits 16 bits 8 bits PWM Frequency (FPWM) 1.22 kHz 39.1 kHz 610 Hz 39.1 kHz 305 Hz 39.1 kHz 153 Hz 39.1 kHz

TCY (FCY) 25 ns (40 MHz) 25 ns (40 MHz) 50 ns (20 MHz) 50 ns (20 MHz) 100 ns (10 MHz) 100 ns (10 MHz) 200 ns (5 MHz) 200 ns (5 MHz) Table 14-2:

Example of PWM Frequencies and Resolutions, 1:1 Prescaler, Center-aligned PWM PxTPER Value 0x7FFE 0x3FFE 0x7FFE 0x1FFE 0x7FFE 0xFFE 0x7FFE 0x7FE PXDCY Value for 100% 0xFFFE 0x7FFE 0xFFFE 0x3FFE 0xFFFE 0x1F FE 0xFFFE 0xFFE PWM Resolution 16 bits 15 bits 16 bits 14 bits 16 bits 13 bits 16 bits 12 bits PWM Frequency 610 Hz 1.22 kHz 305 Hz 1.22 kHz 153 Hz 1.22 kHz 76.3 Hz 1.22 kHz

TCY (FCY) 25 ns (40 MHz) 25 ns (40 MHz) 50 ns (20 MHz) 50 ns (20 MHz) 100 ns (10 MHz) 100 ns (10 MHz) 200 ns (5 MHz) 200 ns (5 MHz) Note:

100% duty cycle cannot be accomplished when PTPER = 0x7FFF. Maximum duty cycle in this scenario is 100 percent minus one-half TCY.

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The MCPWM module can produce PWM signal edges with TCY/2 resolution. PxTMR increments every TCY with a 1:1 prescaler. To achieve TCY/2 edge resolution, PxDCy<15:1> is compared to the PxTMR<14:0> to determine a duty cycle match. The value in PxDCy<0> determines whether the PWM signal edge will occur at the TCY or the TCY/2 boundary. When a 1:4, 1:16 or 1:64 prescaler is used with the PWM time base, the PxDCy<0> is compared to the Most Significant bit (MSb) of the prescaler counter clock to determine when the PWM edge should occur. Figure 14-15 illustrates the PxTMR and PxDCy resolutions. The PxTMR resolution is TCY, and the PxDCy resolution is TCY/2 for 1:1 prescaler selection. Figure 14-16 illustrates the duty cycle comparison logic. Figure 14-15: PXTMR and PXDCY Resolution Timing Diagram, Free Running Mode and 1:1 Prescaler Selection
TCY

PXTPER = 10

TCY

PxTMR

PXDCY = 14 PXDCY = 15

TCY/2

Figure 14-16: Duty Cycle Comparison Logic

14 PXTMR 15 0 N-bit Prescaler N 2 1 TCY

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PWM Edge Event

15-bit Comparison 15 15 PXDCY 1 0 1-bit Comparison

Edge Logic

Note: PXDCY<0> is compared to the FOSC/2 signal when the prescaler is 1:1.

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14.14 PWM DEAD TIME CONTROL
Each complementary output pair for the MCPWM module has a 6-bit down counter that is used to produce the dead time insertion. As illustrated in Figure 14-17, each dead time unit has a rising and falling edge detector connected to the duty cycle comparison output. One of the two possible dead times is loaded into the timer on the detected PWM edge event. Depending on whether the edge is rising or falling, one of the transitions on the complementary outputs is delayed until the timer counts down to zero. Figure 14-18 illustrates a timing diagram indicating the dead time insertion for one pair of PWM outputs. The use of two different dead times for the rising and falling edge events has been exaggerated in the Figure 14-18 for clarity. Figure 14-17: Dead Time Unit Block Diagram for One Output Pin Pair
Zero Compare

TCY

Prescaler

Clock Control

6-bit Down Counter High-side PWM Signal to Output Pin Low-side PWM Signal to Output Pin Dead Time Select Logic

Dead Time A Dead Time B

PWM Generator Input

Figure 14-18: Dead Time Insertion Diagram

PWM Generator

PWMXHY Dead Time = 0 PWMXLY

PWMXHY Non-zero Dead Time

PWMXLY

Time Selected by DTSXA Bit (A or B)

Time Selected by DTSXI Bit (A or B)

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14.14.1 Dead Time Assignment
The Dead Time Control Register 2 (PxDTCON2) contains control bits that allow the two programmable dead times to be assigned to each of the complementary outputs. There are two dead time assignment control bits for each of the complementary outputs. For example, the Dead Time Select for PWM1 Signal Going Active control bit, DTS1A (PxDTCON2<1>), and the Dead Time Select for PWM1 Signal Going Inactive control bit, DTS1I (PxDTCON2<0>), select the dead times to be used for the PWMxH1/PWMxL1 complementary output pair. The pair of dead time selection control bits are referred to as the dead-time-select-active and dead-time-select-inactive control bits, respectively. The function of each bit in a pair is as follows: The DTSxA control bit selects the dead time that is to be inserted before the high-side output is driven active. The DTSxI control bit selects the dead time that is to be inserted before the low-side PWM output is driven active. Table 14-3 summarizes the function of each dead time selection control bit. Table 14-3: Bit DTS1A DTS1I DTS2A DTS2I DTS3A DTS3I DTS4A DTS4I Dead Time Selection Bits Function Selects PWMxH1/PWMxL1 dead time inserted before PWMxH1 is driven active Selects PWMxH1/PWMxL1 dead time inserted before PWMxL1 is driven active Selects PWMxH2/PWMxL2 dead time inserted before PWMxH2 is driven active Selects PWMxH2/PWMxL2 dead time inserted before PWMxL2 is driven active Selects PWMxH3/PWMxL3 dead time inserted before PWMxH3 is driven active Selects PWMxH3/PWMxL3 dead time inserted before PWMxL3 is driven active Selects PWMxH4/PWMxL4 dead time inserted before PWMxH4 is driven active Selects PWMxH4/PWMxL4 dead time inserted before PWMxL4 is driven active

14.14.2 Dead Time Ranges

Dead Time Unit A and Dead Time Unit B are set by selecting an input clock prescaler value and a 6-bit unsigned dead time count value. Four input clock prescaler selections have been provided to allow suitable range of dead times based on the device operating frequency. The clock prescaler option can be selected independently for each of the two dead time values. The dead time clock prescaler values are selected using the Dead Time Unit A Prescale Select bits (DTAPS<1:0>) in the Dead Time Control Register 1 (PxDTCON1<15:14>), and the Dead Time Unit B Prescale Select bits, DTBPS<1:0> (PxDTCON1<7:6>) SFR. The following clock prescaler options can be selected for each of the dead time values: TCY 2 TCY 4 TCY 8 TCY

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Equation 14-4 provides the formula for dead time calculation. Equation 14-4: Dead Time Calculation Dead Time DT = ------------------------------------------------------Prescale Value TCY Note: Dead Time (DT) is the DTA<5:0> or DTB<5:0> register value.

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Table 14-4 provides an example of the dead time ranges as a function of the selected input clock prescaler and the device operating frequency. Table 14-4: TCY (FCY) 25 ns (40 MHz) 25 ns (40 MHz) 50 ns (20 MHz) 100 ns (10 MHz) 100 ns (10 MHz) Example Dead Time Ranges Prescaler Selection 1 TCY 4 TCY 4 TCY 2 TCY 1 TCY Resolution 25 ns 100 ns 200 ns 200 ns 100 ns Dead Time Range 25 ns 1.6 s 100 ns 7 s 200 ns 12 s 200 ns 12 s 100 ns 6 s

14.14.3 Dead Time Distortion

For short PWM duty cycles, the ratio of dead time to the active PWM time can become large. In an extreme case, when the duty cycle is less than or equal to the programmed duty cycle, no PWM pulse will be generated. In these cases, the inserted dead time introduces distortion into waveforms produced by the MCPWM module. User software can minimize dead time distortion by keeping the PWM duty cycle at least three times larger than the dead time. Dead time distortion can also be corrected by other techniques, such as closed loop current control. A similar effect occurs for duty cycles near 100%. The maximum duty cycle used in the application should be selected such that the minimum inactive time of the PWM signal is at least three times larger than the dead time. Example 14-1 demonstrates how to configure the MCPWM module. Example 14-2 demonstrates how the PWM Output mode is selected. Example 14-3 demonstrates how to configure the dead time. Example 14-4 demonstrates how to configure the I/O pin for the MCPWM module. Example 14-5 demonstrates how to configure the duty cycle for the MCPWM module. Example 14-6 demonstrates the enabling of the MCPWM module. Example 14-1: MCPWM Module Operating Mode and Time Selection

/* Configuration register FPOR */ /* High and Low switches set to active-high state */ _FPOR(RST_PWMPIN & PWMxH_ACT_HI & PWMxL_ACT_HI) /* PWM time base operates in a Free Running mode */ P1TCONbits.PTMOD = 0b00; /* PWM time base input clock period is TCY (1:1 prescale) */ /* PWM time base output post scale is 1:1 */ P1TCONbits.PTCKPS = 0b00; P1TCONbits.PTOPS = 0b00; /* /* /* /* Choose PWM time period based on input clock selected */ Refer to Equation 14-1 */ PWM switching frequency is 20 kHz */ FCY is 20 MHz */

P1TPER = 999;

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Example 14-2: MCPWM Module Output Mode Selection
/* PWM I/O pairs 1 to 3 are in complementary mode */ /* PWM pins are enabled for PWM output */ PWM1CON1bits.PMOD1 PWM1CON1bits.PMOD2 PWM1CON1bits.PMOD3 PWM1CON1bits.PEN1H PWM1CON1bits.PEN2H PWM1CON1bits.PEN3H PWM1CON1bits.PEN1L PWM1CON1bits.PEN2L PWM1CON1bits.PEN3L = = = = = = = = = 0; 0; 0; 1; 1; 1; 1; 1; 1;

/* Immediate update of PWM enabled */ PWM1CON2bits.IUE = 1;

Example 14-3:

Dead Time Insertion (Complementary PWM Output Mode Only)

/* Clock period for Dead Time Unit A is TcY */ /* Clock period for Dead Time Unit B is TcY */ P1DTCON1bits.DTAPS = 0b00; P1DTCON1bits.DTBPS = 0b00; /* Dead time value for Dead Time Unit A */ /* Dead time value for Dead Time Unit B */ P1DTCON1bits.DTA = 10; P1DTCON1bits.DTB = 20; /* Dead Time Unit selection for PWM signals */ /* Dead Time Unit A selected for PWM active transitions */ /* Dead Time Unit B selected for PWM inactive transitions */ P1DTCON2bits.DTS3A = 0; P1DTCON2bits.DTS2A = 0; P1DTCON2bits.DTS1A = 0; P1DTCON2bits.DTS3I = 1; P1DTCON2bits.DTS2I = 1; P1DTCON2bits.DTS1I = 1;

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Example 14-4:

MCPWM Module I/O Pin Control

/* PWM I/O pin controlled by PWM Generator */ P1OVDCONbits.POVD3H P1OVDCONbits.POVD2H P1OVDCONbits.POVD1H P1OVDCONbits.POVD3L P1OVDCONbits.POVD2L P1OVDCONbits.POVD1L = = = = = = 1; 1; 1; 1; 1; 1;

Example 14-5:

MCPWM Module Duty Cycle Initialization

/* Initialize duty cycle values for PWM1, PWM2 and PWM3 signals */ P1DC1 = 200; P1DC2 = 200; P1DC3 = 200;

Example 14-6:

Enabling PWM Pulse Generation

P1TCONbits.PTEN = 1;

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14.15 PWM FAULT HANDLING
There are two fault pins, FLTxA and FLTxB, associated with the MCPWM module. When asserted, these pins can optionally drive each of the PWM I/O pins to a defined state. This action takes place without user software intervention, so fault events can be managed quickly. These fault pins can have other multiplexed functions depending on the dsPIC33F/PIC24H device. When used as a fault input, each fault pin is readable using its corresponding PORT register. The FLTxA and FLTxB pins function as active low inputs so that it is easy to inclusively OR many sources to the same input through an external pull-up resistor. When not used with the MCPWM module, these pins can be used as general purpose I/O or for another multiplexed function. Each fault pin has its own Interrupt Vector, Interrupt Flag bit, Interrupt Enable bit and Interrupt Priority bits. The function of the FLTxA pin is controlled by the Fault A Control register (PxFLTACON), and the function of the FLTxB pin is controlled by the Fault B Control register (PxFLTBCON).

14.15.1 Fault Pin Enable Bits

The PxFLTACON and PxFLTBCON registers each have four Fault Input Enable bits, FAEN1 through FAEN4 and FBEN1 through FBEN4, that determine whether a particular pair of PWM I/O pins is to be controlled by the fault input pin. To enable a specific PWM I/O pin pair for fault overrides, the corresponding bit should be set in the PxFLTACON or PxFLTBCON register. If all enable bits are cleared in the PxFLTACON or PxFLTBCON registers, that fault input pin has no effect on the MCPWM module and no fault interrupts are produced.

14.15.2 Fault States

The SFRs, PxFLTACON and PxFLTBCON, each have eight bits that determine the state of each PWM I/O pin when the fault input pin becomes active. When these bits are cleared, the PWM I/O pin is driven to the inactive state. If the bit is set, the PWM I/O pin is driven to the active state. The active and inactive states are referenced to the polarity defined for each PWM I/O pin set by the HPOL bit (FPOR<6>) and the LPOL bit (FPOR<6>). A special case exists when a MCPWM module I/O pair is in Complementary PWM Output mode and both pins are programmed to be active on a Fault condition. The high-side pin will always have priority in Complementary PWM Output mode, so that both I/O pins cannot be driven active simultaneously.

14.15.3 Fault Input Modes

Each of the fault input pins has two modes of operation: Latched Mode: When the fault pin is driven low, the PWM outputs go to the states defined in the PxFLTACON and PxFLTBCON registers. The PWM outputs remain in this state until the fault pin is driven high and the corresponding interrupt flag (FLTxAIF or FLTxBIF) has been cleared in software. When both of these actions have occurred, the PWM outputs return to normal operation at the beginning of the next PWM period or half-period boundary regardless of the IUE bit (PWMxCON2<2>) value. If the interrupt flag is cleared before the Fault condition ends, the MCPWM module waits until the fault pin is no longer asserted to restore the outputs. Cycle-by-Cycle Mode: When the fault input pin is driven low, the PWM outputs remain in the defined Fault states for as long as the fault pin is held low. After the fault pin is driven high, the PWM outputs return to normal operation at the beginning of the following PWM period (or half-period boundary in center-aligned modes) even when immediate updates are enabled. The operating mode for each fault input pin is selected using the Fault A Mode bit, FLTAM (PxFLTACON<7), and the Fault B Mode bit, FLTBM (PxFLTBCON<7>).

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14.15.3.1 ENTRY INTO A FAULT CONDITION
When a fault pin is enabled and driven low, the PWM pins are immediately driven to their programmed Fault states regardless of the values in the PxDCy and PxOVDCON registers. The fault action has priority over all other PWM control registers.

14.15.3.2 EXIT FROM A FAULT CONDITION

A Fault condition must be cleared by the external circuitry driving the fault input pin high and clearing the fault interrupt flag (Latched mode only). After the fault pin condition has been cleared, the MCPWM module restores the PWM output signals on the next PWM period or half-period boundary. For edge-aligned PWM generation, the PWM outputs are restored when PxTMR = 0. For center-aligned PWM generation, the PWM outputs are restored when PxTMR = 0 or PxTMR = PxTPER, whichever event occurs first. An exception to these rules occurs when the PWM time base is disabled (PTEN = 0). If the PWM time base is disabled, the MCPWM module restores the PWM output signals immediately after the Fault condition has been cleared.

14.15.4 Fault Pin Priority

If both fault input pins have been assigned to control a specific pair of PWM pins, the Fault states programmed for the FLTxA input pin will take priority over the FLTxB input pin. One of the two actions will take place when the Fault A condition has been cleared. If the FLTxB input is still asserted, the PWM outputs will return to the states programmed in the PxFLTBCON register on the next period or half-period boundary. If the FLTxB input is not asserted, the PWM outputs will return to normal operation on the next period or half-period boundary. Note: When the FLTxA pin is programmed for Latched mode, the PWM outputs will not return to the Fault B states or normal operation until the Fault A interrupt flag has been cleared and the FLTxA pin is deasserted.

14.15.5 Fault Pin Software Control

Each of the fault pins can be controlled manually in the user software. Since each fault input is shared with a PORT I/O pin, the PORT pin can be configured as an output by clearing the corresponding bit of the TRIS register. When the corresponding bit of the PORT register for the pin is cleared, the fault input is activated. Note: Caution should be exercised when controlling the fault inputs in the user software. If the corresponding bit of the TRIS register for the fault pin is cleared, the fault input cannot be driven externally.

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14.15.6 Fault Timing Examples
Figure 14-19 through Figure 14-21 illustrate examples of the PWM fault timing. Figure 14-19: Example Fault Timing, Cycle-by-Cycle Mode
PWM Period

PxTMR Case 1: PWM FLTxA Case 2: PWM FLTxA Case 3: PWM FLTxA Note: Arrows indicate the time when normal PWM operation is restored. Duty Cycle = 100% Fault State Duty Cycle = 50% Fault State Duty Cycle = 50% Fault State

Figure 14-20: Example Fault Timing, Latched Mode

PxTMR Return to Normal Operation Fault State

Duty Cycle = 50% PWM FLTXA FLTXAIF Fault Condition Ends

Interrupt Flag Cleared in User Software

Figure 14-21: Example Fault Timing, Cycle-by-Cycle Mode, Priority Operation

PXTMR Return to Normal Operation Fault State B

Duty Cycle = 50% PWM FLTXA FLTXB Fault State B Fault State A

Return to Fault State B

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14.16 SPECIAL FEATURES OF THE MCPWM MODULE
The following special features are available in the MCPWM module: 14.16.1 PWM Output Override 14.16.2 Special Event Trigger 14.16.3 PWM Update Lockout 14.16.4 Device Emulation 14.16.5 Write Protected Registers

14.16.1 PWM Output Override

The PWM output override bits allow the PWM I/O pins to be manually driven to specified logic states, independent of the duty cycle comparison units. The PWM override bits are useful when controlling various types of electrically commutated motors. Figure 14-22 illustrates a block diagram of the PWM output override control. Figure 14-22: Output Override Control
Dead Time A Dead Time B

PXOVDCON <POUT4H:POUT1L> Output Override Logic PXOVDCON <POVD4H:POVD1L> Dead Time Control Logic

PWMXH1 PWMXL1 PWMXH2 PWMXL2 PWMXH3 PWMXL3 PWMXH4 PWMXL4

Fault Logic

FLTxA/FLTxB

PWM Time Base PWMXCON1 <PMOD4:PMOD1> PWMXCON1 <PEN4H:PEN1L>

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All control bits associated with the PWM output override function are in the PxOVDCON register. The upper half of the PxOVDCON register contains eight PWM Output Override bits (POVDx) that determine which PWM I/O pins will be overridden. The lower half of the PxOVDCON register contains eight PWM Manual Output bits (POUTx) that determine the state of the PWM I/O pin when it is overridden with the POVDx bit. The POVD4H:POVD1L bits (PxOVDCON<15:8>) are active-low control bits. When the POVD4H:POVD1L bits (PxOVDCON<15:8>) are set, the corresponding POUTx bit has no effect on the PWM output. When one of the POVD4H:POVD1L bits (PxOVDCON<15:8>) is cleared, the output on the corresponding PWM I/O pin is determined by the state of the corresponding POUT4H:POUT1L bits (PxOVDCON<7:0>). When the POUT4H:POUT1L bits (PxOVDCON<7:0>) are set, the PWM pin is driven to its active state. When the POUT4H:POUT1L bits (PxOVDCON<7:0>) are cleared, the PWM pin is driven to its inactive state. Example 14-7 demonstrates the PWM Output Override feature.

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Example 14-7: Code for Using the MCPWM Output Override Feature
/* Output Override Synchronization */ /* Output overrides via the P1OVDCON register are synchronized to the PWM */ /* time base by setting the OSYNC bit */ PWM1CON2bits.OSYNC = 1; /* Override control register configuration */ /* Output on the PWMxHy and PWMxLy I/O pins are controlled by the */ /* corresponding POUTx bits in the PxOVDCON register */ P1OVDCONbits.POVD3H P1OVDCONbits.POVD2H P1OVDCONbits.POVD1H P1OVDCONbits.POVD3L P1OVDCONbits.POVD2L P1OVDCONbits.POVD1L = = = = = = 0; 0; 0; 0; 0; 0;

/* PWM I/O pins are driven to active state by setting the corresponding bit */ P1OVDCONbits.POUT3H P1OVDCONbits.POUT2H P1OVDCONbits.POUT1H P1OVDCONbits.POUT3L P1OVDCONbits.POUT2L P1OVDCONbits.POUT1L = = = = = = 1; 1; 1; 1; 1; 1;

14.16.1.1 OVERRIDE CONTROL FOR COMPLEMENTARY OUTPUT MODE

The MCPWM module does not allow certain overrides when a pair of PWM I/O pins are operating in Complementary PWM Output mode (PMODx = 0). The MCPWM module does not allow both pins in the output pair to become active simultaneously. The high-side pin in each output pair always takes priority. Note: Dead time insertion is still performed when PWM channels are overridden manually.

14.16.1.2 OVERRIDE SYNCHRONIZATION

If the Output Override Synchronization bit (OSYNC = 1) (PWMxCON2<1>) is set, all output overrides performed using the PxOVDCON register will be synchronized to the PWM time base. Synchronous output overrides will occur at the following times: Edge-aligned mode when the PxTMR register is zero Center-aligned modes when the PxTMR register is zero When the value of the PxTMR register matches the PxTPER register The override synchronization function, when enabled, can be used to avoid unwanted narrow pulses on the PWM output pins.

14.16.1.3 OUTPUT OVERRIDE EXAMPLES

Figure 14-23 illustrates an example of a waveform that might be generated using the PWM Output Override feature. This figure also illustrates a six step commutation sequence for a BLDC motor. The motor is driven through a 3-phase inverter, as illustrated in Figure 14-24. When the appropriate rotor position is detected, the PWM outputs are switched to the next commutation state in the sequence. In Figure 14-23, the PWM outputs are driven to specific logic states. The PxOVDCON register values used to generate the signals in Figure 14-23 are provided in Table 14-5. The PWM duty cycle registers can be used in conjunction with the PxOVDCON register. The duty cycle registers control the current delivered to the load, and the PxOVDCON register controls the commutation. Such an example is illustrated in Figure 14-24. The PxOVDCON register values used to generate the signals in Figure 14-24 are provided in Table 14-6.

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Table 14-5: State 1 2 3 4 5 6 PWM Output Override Example 1 PxOVDCON<15:8> b00000000 b00000000 b00000000 b00000000 b00000000 b00000000 PxOVDCON<7:0> b00100100 b00100001 b00001001 b00011000 b00010010 b00000110

Figure 14-23: PWM Output Override Example 1

STATE 1 PWMXH3 PWMXL3 PWMXH2 PWMXL2 PWMXH1 PWMXL1 2 3 4 5 6

Note:

Switching times between states 1 through 6 are controlled by the user software. The state switch is controlled by writing a new value to the PxOVDCON register.

Table 14-6: State 1 2 3 4

PWM Output Override Example 2 PxOVDCON<15:8> b11000011 b11110000 b00111100 b00001111 PxOVDCON<7:0> b00000000 b00000000 b00000000 b00000000

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Figure 14-24: PWM Output Override Example 2
STATE

PWMXH4 PWMXL4 PWMXH3 PWMXL3 PWMXH2 PWMXL2 PWMXH1

PWMXL1 Note: Switching times between states 1 through 4 are controlled by the user software. The state switch is controlled by writing a new value to PxOVDCON. The PWM outputs are operated in the independent mode for this example.

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Section 14. Motor Control PWM

14.16.2 Special Event Trigger
The MCPWM module has a Special Event Trigger that allows analog-to-digital conversions to be synchronized to the PWM time base. The analog-to-digital sampling and conversion time can be programmed to occur at any point within the PWM period. The Special Event Trigger can minimize the delay between the time the analog-to-digital conversion results are acquired and the time the duty cycle value is updated. The PWM Special Event Trigger has one SFR (PxSECMP) and four postscaler control bits, SEVOPS<3:0> (PWMxCON2<11:8>), to control its operation. The PxTMR register value for which a Special Event Trigger should occur is loaded into the Special Event Compare register, PxSECMP. When the PWM time base is in Up/Down Count mode, an additional control bit is required to specify the counting phase for the Special Event Trigger. The count phase is selected using the Special Event Trigger Time Base Direction bit, SEVTDIR, in the MSb of the (PxSECMP<15>) register. If the SEVTDIR bit (PxSECMP<15>) is cleared, the Special Event Trigger will occur on the upward counting cycle of the PWM time base. If the SEVTDIR bit (PxSECMP<15>) is set, the Special Event Trigger will occur on the downward count cycle of the PWM time base. The SEVTDIR bit (PxSECMP<15>) has no effect unless the PWM time base is configured for Up/Down Count mode. Example 14-8 demonstrates how to trigger an analog-to-digital conversion based on MCPWM special event generation. Example 14-8: Triggering ADC Based on MCPWM Special Event Generation

/* Select Special Event time base direction such that trigger will occur */ /* when PWM time base is counting downwards */ P1SECMPbits.SEVTDIR = 1; /* Select PWM Special Event Trigger Output Postscale value to 1:1 */ PWM1CON2bits.SEVOPS = 0b0000; /* Assign special event compare value */ P1SECMPbits.SEVTCMP = 100; /* Choose ADC1 trigger source such that MCPWM1 module stops sampling and */ /* starts conversion */ AD1CON1bits.SSRC = 0b011;

14
Motor Control PWM

14.16.2.1 SPECIAL EVENT TRIGGER ENABLE

The MCPWM module always produces the Special Event Trigger signal. This signal may optionally be used by the Analog-to-Digital Converter (ADC) module. For more information on using the Special Event Trigger, refer to the Analog-to-Digital Converter (ADC) chapter in the specific device data sheet, and refer to Section 16. Analog-to-Digital Converter (ADC) (DS70183) in the dsPIC33F/PIC24H Family Reference Manual.

14.16.2.2 SPECIAL EVENT TRIGGER POSTSCALER

The PWM Special Event Trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is useful when synchronized analog-to-digital conversions do not need to be performed during every PWM cycle. The postscaler is configured by writing the SEVOPS<3:0> control bits (PWMxCON2<11:8>) SFR. The special event output postscaler is cleared on the following events: Any write to the PxSECMP register Any device Reset

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14.16.3 PWM Update Lockout
In some applications, it is important that all duty cycle and period registers be written before the new values take effect. The update disable feature allows the user software to specify when new duty cycle and period values can be used by the MCPWM module. The PWM Update Lockout feature is enabled by setting the PWM Update Disable bit, UDIS (PWMxCON2<0>). The UDIS bit (PWMxCON2<0>) affects all duty cycle registers, PxDC1 through PxDC4, and the PWM time base period buffer, PxTPER. To execute an update lockout, perform the following steps: 1. 2. 3. Set the UDIS bit (PWMxCON2<0>). Write all duty cycle registers and PxTPER, if applicable. Clear the UDIS bit (PWMxCON2<0>) to re-enable updates. Note: Immediate updates must be disabled (IUE = 0) to use the PWM Update Lockout feature.

14.16.4 Device Emulation

The MCPWM module has a special feature to support the debugging environment. All enabled PWM pins can be optionally tri-stated when the hardware emulator or debugger device is halted to examine memory contents. Install pull-up and pull-down resistors to ensure that the PWM outputs are driven to the correct state when device execution is halted. The function of the PWM output pins at a device Reset and the output pin polarity is determined by three device Configuration bits (see 14.10 PWM Output State Control). Use a hardware debugger or emulation tool to change the values of these device Configuration bits. For more information, refer to the MPLAB IDE Users Guide with MPLAB Editor and MPLAB SIM Simulator (DS51519).

14.16.5 Write Protected Registers

The write-protect feature is implemented only in devices where the Motor Control PWM Unlock configuration bit (PWMLOCK) is present in the Oscillator Source Selection register (FOSCSEL<6>). If the PWMLOCK bit (FOSCSEL<6>) is not implemented, the PWMxCON1, PxFLTACON and PxFLTBCON register may be written without restrictions. If the PWMLOCK bit (FOSCSEL<6>) is asserted (PWMLOCK = 1), the PWMxCON1, PxFLTACON and PxFLTBCON registers are write-protected. To gain write access to these locked registers, user must write two consecutive values of (0xABCD and 0x4321) to the PWM Unlock register (PWMxKEY) to perform the unlock operation. The write access to the PWMxCON1, PxFLTACON or PxFLTBCON registers must be the next SFR access following the unlock process. There can be no other SFR accesses during the unlock process and subsequent write access. To write to all registers, the PWMxCON1, PxFLTACON and the PxFLTBCON registers require three unlock operations. If the PWMLOCK bit (FOSCSEL<6>) is deasserted (PWMLOCK = 0), the PWMKEY functionality is disabled, and the PWMxCON1, PxFLTACON and PxFLTBCON registers may be written without restrictions.

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Section 14. Motor Control PWM

14.17 OPERATION IN POWER-SAVING MODES
14.17.1 PWM Operation in Sleep Mode
When the device enters Sleep mode, the system clock is disabled. Since the clock for the PWM time base is derived from the system clock source (TCY), that clock will also be disabled. All enabled PWM output pins will be frozen in the output states that were in effect prior to entering Sleep mode. If the MCPWM module is used to control a load in a power application, the MCPWM module outputs must be placed into a safe state before executing the PWRSAV instruction. Depending on the user software, the load may begin to consume excessive current when the PWM outputs are frozen in a particular output state. For example, the PxOVDCON register can be used to manually turn off the PWM output pins, as shown in Example 14-9. Example 14-9: Manually Placing PWM Pins Into an Inactive State

; This code example drives all PWM1 pins to the inactive state ; before executing the PWRSAV instruction. CLR PWRSAV SETM.B P1OVDCON #0 P1OVDCONH ; Force all PWM outputs inactive ; Put the device in Sleep mode ; Set POVD bits when device wakes

The Fault A and Fault B input pins, if enabled to control the PWM pins through the PxFLTACON and PxFLTBCON registers, continue to function normally when the device is in Sleep mode. If one of the fault pins is driven low while the device is in Sleep mode, the PWM outputs are driven to the programmed Fault states in the PxFLTACON and PxFLTBCON registers. The fault input pins can also wake the CPU from Sleep mode. If the fault interrupt enable bit is set (FLTxAIE = 1 or FLTxBIE = 1), the device will wake-up from Sleep mode when the fault pin is driven low. If the fault pin interrupt priority is greater than the current CPU priority, program execution starts at the fault pin interrupt vector location upon wake-up. Otherwise, execution continues from the next instruction following the PWRSAV instruction.

14.17.2 PWM Operation in Idle Mode

When the controller enters Idle mode, the system clock sources remain functional and the CPU stops executing code. The MCPWM module can optionally continue to operate in Idle mode. The PWM Time Base Stop in Idle Mode bit, PTSIDL (PxTCON<13>), determines whether the MCPWM module stops in Idle mode or continues to operate normally. If PTSIDL = 0, the MCPWM module operates normally when the device enters Idle mode. The PWM time base interrupt, if enabled, can be used to wake-up the device from Idle mode. If the PWM Time Base Interrupt Enable bit (PWMxIE) in the Interrupt Enable Control register (IEC) is set (PWMxIE = 1), the device will wake-up from Idle mode when the PWM time base interrupt is generated. If the PWM time base interrupt priority is greater than the current CPU priority, program execution starts at the PWM interrupt vector location upon wake-up. Otherwise, execution will continue from the next instruction following the PWRSAV instruction. If PTSIDL = 1, the MCPWM module stops in Idle mode. If the MCPWM module is programmed to stop in Idle mode, the operation of the PWM outputs and fault input pins is the same as the operation in Sleep mode (see 14.17.1 PWM Operation in Sleep Mode).

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dsPIC33F/PIC24H Family Reference Manual

14.18

REGISTER MAPS
A summary of the registers associated with the MCPWM module are provided in Table 14-7 and Table 14-8.

Table 14-7:
Name IFS3 IFS4 IEC3 IEC4 IPC14 IPC15 IPC16 P1TCON P1TMR P1TPER P1SECMP PWM1CON1 PWM1CON2 P1DTCON1 P1DTCON2

Registers Associated with 8-Output MCPWM1 Module

Bit 15 FLT1AIF FLT1AIE PTEN PTDIR SEVTDIR PMOD4 PMOD3 SEVOPS<3:0> Dead Time B Value Register FAOV1H FAOV1L PMOD2 Bit 14 Bit 13 FLT1AIP<2:0> PTSIDL Bit 12 FLT2BIF FLT2BIE Bit 11 Bit 10 FLT2AIF FLT2AIE Bit 9 PWM1IF PWM2IF PWM1IE PWM2IE Bit 8 Bit 7 Bit 6 Bit 5 PWM1IP<2:0> Bit 4 Bit 3 PTCKPS<1:0> Bit 2 Bit 1 FLT1BIP<2:0> PTMOD<1:0> Bit 0 FLT1BIF FLT1BIE Value on Reset 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0100 0000 0100 0000 0000 0000 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 PEN1H DTS3I PEN4L DTS2A FAEN4 FBEN4 PEN3L IUE DTS2I FAEN3 FBEN3 PEN2L OSYNC DTS1A FAEN2 FBEN2 PEN1L UDIS DTS1I FAEN1 FBEN1 0000 0000 yyyy yyyy(1) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 yyyy(2) 0000 0000 0000 yyyy(2) 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DTS3A PEN2H

PTOPS<3:0>

PWM Time Base Register PWM Time Base Period Register PWM Special Event Compare Register PMOD1 PEN4H DTS4A FLTAM FLTBM PEN3H DTS4I

DTBPS<1:0>

DTAPS<1:0>

Dead Time A Value Register

P1FLTACON FAOV4H FAOV4L FAOV3H FAOV3L FAOV2H FAOV2L

P1FLTBCON FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L P1DC1 P1DC2 P1DC3 P1DC4 PWM1KEY(3)

P1OVDCON POVD4H POVD4L POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L POUT4H POUT4L POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L PWM Duty Cycle 1 Register PWM Duty Cycle 2 Register PWM Duty Cycle 3 Register PWM Duty Cycle 4 Register PWMKEY<15:0>

Legend: y = bit depends on configuration, u = uninitialized bit, = unimplemented, read as 0. Note 1: The Reset condition of the PEN4H:PEN1H and PEN4L:PEN1L bits depends on the value of the PWMPIN bit (FPOR<7>). When PWMPIN is set to 0, Reset values are 1. When PWMPIN is set to 1, Reset values are 0. 2: In devices where the PWMLOCK configuration bit is present in the FOSCSEL configuration register, the reset value for the FAEN4:FAEN1 and FBEN4:FBEN1 bits is 1. In all other configurations, the reset value for these bits is 0. Refer to the specific device data sheet for more information. 3: This register is implemented only in devices where the PWMLOCK configuration bit is present in the FOSCSEL configuration register. Refer to the specific device data sheet for availability.

Motor Control PWM

2007-2012 Microchip Technology Inc. DS70187E-page 14-51

Table 14-8:
SFR Name IFS3 IFS4 IEC3 IEC4 IPC18 IPC19 P2TCON P2TMR P2TPER P2SECMP PWM2CON1 PWM2CON2 P2DTCON1 P2DTCON2 P2FLTACON P2OVDCON P2DC1

Registers Associated with 2-Output MCPWM2 Module

Bit 15 FLT1AIF FLT1AIE PTEN PTDIR SEVTDIR Bit 14 Bit 13 PTSIDL Bit 12 FLT2BIF FLT2BIE Bit 11 Bit 10 FLT2AIF FLT2AIE Bit 9 PWM1IF PWM2IF PWM1IE PWM2IE Bit 8 Bit 7 Bit 6 Bit 5 PWM2IP<2:0> Bit 4 Bit 3 PTCKPS<1:0> Bit 2 Bit 1 FLT2BIP<2:0> PTMOD<1:0> Bit 0 FLT1BIF FLT1BIE Value on Reset 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0100 0100 0000 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PEN1H IUE DTA<5:0> DTS1A POUT1H DTS1I FAEN1 POUT1L OSYNC PEN1L UDIS 0000 0000 000y 000y(1) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000y(2) 1111 1111 0000 0000 0000 0000 0000 0000

FLT2AIP<2:0>

PTOPS<3:0>

PWM Timer Count Value Register PWM Time Base Period Register PWM Special Event Compare Register PMOD1

SEVOPS<3:0> DTB<5:0>

DTBPS<1:0>

DTAPS<1:0> FAOV1H FAOV1L FLTAM

POVD1H POVD1L

PWM Duty Cycle 1 Register

Section 14. Motor Control PWM

Legend: y = bit depends on configuration, u = uninitialized bit, = unimplemented, read as 0 Note 1: The Reset condition of the PEN1H and PEN1L bits depends on the value of the PWMPIN bit (FPOR<7>). When PWMPIN is set to 0, Reset values are 1. When PWMPIN is set to 1, Reset values are 0. 2: In devices where the PWMLOCK configuration bit is present in the FOSCSEL configuration register, the reset value for FAEN1 bit is 1. In all other configurations, the reset value for this bit is 0. Refer to the specific device data sheet for more information.

14

dsPIC33F/PIC24H Family Reference Manual

14.19 RELATED APPLICATION NOTES
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC33F/PIC24H product family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Motor Control PWM module include the following: Title Using the dsPIC30F for Sensorless BLDC Control Using the dsPIC30F for Vector Control of an ACIM Sensored BLDC Motor Control Using dsPIC30F2010 An Introduction to AC Induction Motor Control Using the dsPIC30F MCU Sinusoidal Control of PMSM Motors with dsPIC30F DSC Sensorless Field Oriented Control of PMSM Motors Sensorless BLDC Control with Back-EMF Filtering Power Factor Correction in Power Conversion Applications Using the dsPIC DSC Sensorless BLDC Control with Back-EMF Filtering Using a Majority Function Sensorless Field Oriented Control (FOC) of an AC Induction Motor (ACIM) Sensorless Field Oriented Control (FOC) of an AC Induction Motor (ACIM) Using Field Weakening Integrated Power Factor Correction (PFC) and Sensorless Field Oriented Control (FOC) System Getting Started with the BLDC Motors and dsPIC30F Devices Measuring Speed and Position with the QEI Module Driving ACIM with the dsPIC DSC MCPWM Module Using the dsPIC30F Sensorless Motor Tuning Interface Note:

Application Note # AN901 AN908 AN957 AN984 AN1017 AN1078 AN1083 AN1106 AN1160 AN1162 AN1206 AN1208 GS001 GS002 GS004 GS005

Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the dsPIC33F/PIC24H family of devices.

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Section 14. Motor Control PWM

14.20 REVISION HISTORY
Revision A (February 2007)
This is the initial released version of the document

Revision B (February 2007)

Minor edits throughout document

Revision C (September 2008)

This revision incorporates the following updates: Notes: - Added a note on maximum duty cycle achievable in 14.13 PWM Duty Cycle Resolution. This update has been referred from Section 15. Motor Control PWM (DS70062) of the dsPIC30F Family Reference Manual (DS70046) Registers: - The table description and bit description for bits 0 through 4 have been corrected in the FPOR: POR Device Configuration Register (see Register 14-17) Sections: - Updated the reference to BOR and POR Device Configuration register (FBORPOR) as POR Device Configuration (FPOR) in 14.10 PWM Output State Control (see second paragraph) - All references to FBORPOR have been updated as FPOR Tables: - Updated the PxTPER value and PxDCy value for 100% in Table 14-1 and Table 14-2. This update has been referred from Section 15. Motor Control PWM (DS70062) of the dsPIC30F Family Reference Manual (DS70046) Additional minor corrections such as language and formatting updates have been incorporated throughout the document

Revision D (July 2010)

This revision incorporates the following updates: Updated the Notes in the PWM Control Register 1 and the Fault A Control Register (see Register 14-5 and Register 14-9) Added the PWM Unlock Register and the Oscillator Source Selection Register (see Register 14-16 and Register 14-18) Added new section 14.16.5 Write Protected Registers Updated the Notes in the register maps (see Table 14.18 and Table 14-8)

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Motor Control PWM

Revision E (September 2012)

This revision incorporates the following updates: The term PWMKEY is updated to PWMxKEY in: - Figure 14-1 - Note 1 in Register 14-5, Register 14-9, Register 14-10 and Register 14-16 - Second paragraph in section 14.16.5 Write Protected Registers - Section 14.18 Register Maps Added the section 14.18 Register Maps and moved the Table 14-7 and Table 14-8 into this section Minor changes to text and formatting were incorporated throughout the document

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dsPIC33F/PIC24H Family Reference Manual

NOTES:

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Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2007-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.

ISBN: 978-1-62076-524-1

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISO/TS 16949 ==
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Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Companys quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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