24AA64/24LC64

64K I2CCMOS Serial EEPROM

DEVICE SELECTION TABLE
Part Number 24AA64 24LC64

PACKAGE TYPE
Temp Ranges C I, E
A2 Vss
3 4

Vcc Range 1.8-5.5V 2.5-5.5V

Max Clock Frequency 400 kHz

8-LEAD PDIP A0 A1
1 8

Vcc WP SCL SDA

24xx64

7 6 5

400 kHz

100 kHz for Vcc < 2.5V.

FEATURES
Low power CMOS technology - Maximum write current 3 mA at 5.5V - Maximum read current 400 A at 5.5V - Standby current 100 nA typical at 5.5V 2-wire serial interface bus, I2C compatible Cascadable for up to eight devices Self-timed ERASE/WRITE cycle 32-byte page or byte write modes available 5 ms max write cycle time Hardware write protect for entire array Output slope control to eliminate ground bounce Schmitt trigger inputs for noise suppression 1,000,000 erase/write cycles guaranteed Electrostatic discharge protection > 4000V Data retention > 200 years 8-pin PDIP, SOIC (150 and 208 mil) and TSSOP packages Temperature ranges: - Commercial (C): 0 to 70C - Industrial (I): -40C to +85C - Automotive (E) -40C to +125C

8-LEAD SOIC A0 A1 A2 Vss 1 8 Vcc WP SCL SDA

24xx64

2 3 4

7 6 5

8-LEAD TSSOP WP Vcc A0 A1 1 2 3 4 8 7 6 5 SCL SDA Vss A2

24xx64

BLOCK DIAGRAM
A0 A1 A2 WP
HV GENERATOR

DESCRIPTION
The Microchip Technology Inc. 24AA64/24LC64 (24xx64*) is a 8K x 8 (64K bit) Serial Electrically Erasable PROM capable of operation across a broad voltage range (1.8V to 5.5V). It has been developed for advanced, low power applications such as personal communications or data acquisition. This device also has a page-write capability of up to 32 bytes of data. This device is capable of both random and sequential reads up to the 64K boundary. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space. This device is available in the standard 8-pin plastic DIP, 8-pin SOIC (150 and 208 mil), and 8-pin TSSOP.
I/O CONTROL LOGIC MEMORY CONTROL LOGIC XDEC EEPROM ARRAY PAGE LATCHES

I/O

SCL
YDEC

SDA VCC VSS

SENSE AMP R/W CONTROL

I2C is a trademark of Philips Corporation.

*24xx64 is used in this document as a generic part number for the 24AA64/24LC64 devices.

2000 Microchip Technology Inc.

DS21189D-page 1

24AA64/24LC64
1.0
1.1

ELECTRICAL CHARACTERISTICS
Maximum Ratings*

TABLE 1-1
Name A0,A1,A2 VSS SDA SCL WP VCC

PIN FUNCTION TABLE

Function User Configurable Chip Selects Ground Serial Data Serial Clock Write Protect Input +1.8 to 5.5V (24AA64) +2.5 to 5.5V (24LC64)

Vcc .................................................................................................7.0V All inputs and outputs w.r.t. Vss .............................. -0.6V to Vcc +1.0V Storage temperature ...................................................-65C to +150C Ambient temp. with power applied ..............................-65C to +125C Soldering temperature of leads (10 seconds) ........................... +300C ESD protection on all pins ................................................................. 4 kV *Notice: Stresses above those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-2

DC CHARACTERISTICS
Tamb = 0C to +70C Tamb = -40C to +85C Tamb = -40C to 125C Units Conditions

All parameters apply across the rec- Commercial (C): VCC = +1.8V to 5.5V ommended operating ranges unless Industrial (I): VCC = +2.5V to 5.5V otherwise noted. Automotive (E): VCC = +2.5V to 5.5V Parameter A0, A1, A2, SCL, SDA, and WP pins: High level input voltage Low level input voltage Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Symbol Min Max

VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Write ICC Read ICCS

0.7 VCC 0.05 VCC -10 -10

0.3 VCC 0.2 VCC 0.40 10 10 10 3 400 1

V V V V V A A pF mA A A

VCC 2.5V VCC < 2.5V VCC > 2.5V (Note) IOL = 3.0 mA @ VCC = 4.5V IOL = 2.1 mA @ VCC = 2.5V VIN = Vss to VCC, WP = VSS VIN = Vss or VCC, WP = VCC VOUT = Vss to VCC VCC = 5.0V (Note) Tamb = 25C, fc= 1 MHz VCC = 5.5V VCC = 5.5V, SCL = 400 kHz SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1:

BUS TIMING DATA

TF THIGH VHYS TR

SCL

TSU:STA TLOW THD:DAT TSU:DAT TSU:STO

SDA IN

THD:STA TSP TBUF

SDA OUT

TAA

WP

(protected) (unprotected)

TSU:WP

THD:WP

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2000 Microchip Technology Inc.

24AA64/24LC64
TABLE 1-3 AC CHARACTERISTICS
Tamb = 0C to +70C Tamb = -40C to +85C Tamb = -40C to 125C
Conditions 1.8V VCC 2.5V 2.5V VCC 5.5V 1.8V VCC 2.5V 2.5V VCC 5.5V 1.8V VCC 2.5V 2.5V VCC 5.5V 1.8V VCC 2.5V 2.5V VCC 5.5V (Note 1) 1.8V VCC 2.5V 2.5V VCC 5.5V 1.8V VCC 2.5V 2.5V VCC 5.5V (Note 2) 1.8V VCC 2.5V 2.5V VCC 5.5V 1.8V VCC 2.5V 2.5V VCC 5.5V 1.8V VCC 2.5V 2.5V VCC 5.5V 1.8V VCC 2.5V 2.5V VCC 5.5V 1.8V VCC 2.5V 2.5V VCC 5.5V 1.8V VCC 2.5V 2.5V VCC 5.5V CB 100 pF (Note 1) (Notes 1 and 3) All parameters apply across the spec- Commercial (C): VCC = +1.8V to 5.5V ified operating ranges unless otherIndustrial (I): VCC = +2.5V to 5.5V wise noted. Automotive (E): VCC = +2.5V to 5.5V Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time (Note 1) SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time WP setup time WP hold time Output valid from clock (Note 2) Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance Symbol FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TSU:WP THD:WP TAA TBUF Min 4000 600 4700 1300 4000 600 4700 600 0 250 100 4000 600 4000 600 4000 1300 4700 1300 10 1M Max 100 400 1000 300 300 3500 900 250 50 5 Units kHz ns ns ns ns ns ns ns ns ns ns ns ns ns

TOF TSP TWC

ns ns ms cycles

25C, VCC = 5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchips BBS or website.

2000 Microchip Technology Inc.

DS21189D-page 3

24AA64/24LC64
2.0
2.1

PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs

4.0

BUS CHARACTERISTICS

The following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 4-1).

The A0,A1,A2 inputs are used by the 24xx64 for multiple device operation. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight devices may be connected to the same bus by using different chip select bit combinations. These inputs must be connected to either VCC or VSS.

2.2

SDA Serial Data

4.1

Bus not Busy (A)

This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an opendrain terminal, therefore, the SDA bus requires a pullup resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz) For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.

Both data and clock lines remain HIGH.

4.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

4.3

Stop Data Transfer (C)

2.3

SCL Serial Clock

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must end with a STOP condition.

This input is used to synchronize the data transfer from and to the device.

4.4

Data Valid (D)

2.4

WP

This pin can be connected to either Vss, Vcc or left floating. An internal pull-down resistor on this pin will keep the device in the unprotected state if left floating. If tied to Vss or left floating, normal memory operation is enabled (read/write the entire memory 0000-1FFF). If tied to VCC, WRITE operations are inhibited. Read operations are not affected.

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device.

3.0

FUNCTIONAL DESCRIPTION

4.5

Acknowledge

The 24xx64 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions while the 24xx64 works as a slave. Both master and slave can operate as a transmitter or receiver but the master device determines which mode is activated.

Each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24xx64 does not generate any acknowledge bits if an internal programming cycle is in progress.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24xx64) will leave the data line HIGH to enable the master to generate the STOP condition.

DS21189D-page 4

2000 Microchip Technology Inc.

24AA64/24LC64
FIGURE 4-1:
(A) SCL (B)

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(D) (D) (C) (A)

SDA

START CONDITION

ADDRESS OR DATA ACKNOWLEDGE ALLOWED VALID TO CHANGE

STOP CONDITION

FIGURE 4-2:

ACKNOWLEDGE TIMING
Acknowledge Bit

SCL

SDA

Data from transmitter

Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.

Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.

2000 Microchip Technology Inc.

DS21189D-page 5

24AA64/24LC64
5.0 DEVICE ADDRESSING
FIGURE 5-1: CONTROL BYTE FORMAT
Read/Write Bit Chip Select Bits 0 A2 A1 A0 R/W ACK

A control byte is the first byte received following the start condition from the master device (Figure 5-1). The control byte consists of a four bit control code; for the 24xx64 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the chip select bits (A2, A1, A0). The chip select bits allow the use of up to eight 24xx64 devices on the same bus and are used to select which device is accessed. The chip select bits in the control byte must correspond to the logic levels on the corresponding A2, A1, and A0 pins for the device to respond. These bits are in effect the three most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). Because only A12...A0 are used, the upper three address bits are dont care bits. The upper address bits are transferred first, followed by the less significant bits. Following the start condition, the 24xx64 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24xx64 will select a read or write operation.

Control Code S 1 0 1

Slave Address Start Bit Acknowledge Bit

5.1

Contiguous Addressing Across Multiple Devices

The chip select bits A2, A1, A0 can be used to expand the contiguous address space for up to 512K bits by adding up to eight 24xx64's on the same bus. In this case, software can use A0 of the control byte as address bit A13, A1 as address bit A14, and A2 as address bit A15. It is not possible to sequentially read across device boundaries.

FIGURE 5-2:

ADDRESS SEQUENCE BIT ASSIGNMENTS

ADDRESS HIGH BYTE ADDRESS LOW BYTE

CONTROL BYTE

A 2

A 1

A 0 R/W

A A A 12 11 10

A 9

A 8

A 7

A 0

CONTROL CODE

CHIP SELECT BITS

X = Dont Care Bit

DS21189D-page 6

2000 Microchip Technology Inc.

24AA64/24LC64
6.0
6.1

WRITE OPERATIONS
Byte Write

6.2

Page Write

Following the start condition from the master, the control code (four bits), the chip select (three bits), and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24xx64. The next byte is the least significant address byte. After receiving another acknowledge signal from the 24xx64 the master device will transmit the data word to be written into the addressed memory location. The 24xx64 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24xx64 will not generate acknowledge signals (Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written and the device will immediately accept a new command. After a byte write command, the internal address counter will point to the address location following the one that was just written.

The write control byte, word address and the first data byte are transmitted to the 24xx64 in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to 31 additional bytes which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. After receipt of each word, the five lower address pointer bits are internally incremented by one. If the master should transmit more than 32 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written and the device will immediately accept a new command.

6.3

Write Protection

The WP pin allows the user to write protect the entire array (0000-1FFF) when the pin is tied to Vcc. If tied to VSS or left floating, the write protection is disabled. The WP pin is sampled at the STOP bit for every write command (Figure 1-1) Toggling the WP pin after the STOP bit will have no effect on the execution of the write cycle.

FIGURE 6-1:

BYTE WRITE
S T A R T CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE S T O P P A C K A C K A C K

BUS ACTIVITY MASTER

DATA

SDA LINE

A A S 1 0 1 0 A 2 1 0 0 A C K

X X X

BUS ACTIVITY X = dont care bit

FIGURE 6-2:

PAGE WRITE
S T A R T S T O P P A C K A C K A C K A C K

BUS ACTIVITY MASTER SDA LINE

CONTROL BYTE

ADDRESS HIGH BYTE

ADDRESS LOW BYTE

DATA BYTE 0

DATA BYTE 31

A A A S 1 0 1 0 2 1 0 0 A C K

X X X

BUS ACTIVITY X = dont care bit

2000 Microchip Technology Inc.

DS21189D-page 7

24AA64/24LC64
7.0 ACKNOWLEDGE POLLING
FIGURE 7-1:
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for flow diagram.

ACKNOWLEDGE POLLING FLOW

Send Write Command

Send Stop Condition to Initiate Write Cycle

Send Start

Send Control Byte with R/W = 0

Did Device Acknowledge (ACK = 0)? YES Next Operation

NO

DS21189D-page 8

2000 Microchip Technology Inc.

24AA64/24LC64
8.0 READ OPERATION
8.2 Random Read
Read operations are initiated in the same way as write operations with the exception that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read, and sequential read. Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24xx64 as part of a write operation (R/W bit set to 0). After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24xx64 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition which causes the 24xx64 to discontinue transmission (Figure 8-2). After a random read command, the internal address counter will point to the address location following the one that was just read.

8.1

Current Address Read

The 24xx64 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to one, the 24xx64 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24xx64 discontinues transmission (Figure 8-1).

8.3

Sequential Read

FIGURE 8-1:
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY S T A R T

CURRENT ADDRESS READ

CONTROL BYTE DATA BYTE S T O P P A C K N O A C K

S 1 0 1 0 A AA 1 2 1 0

Sequential reads are initiated in the same way as a random read except that after the 24xx64 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. This acknowledge directs the 24xx64 to transmit the next sequentially addressed 8-bit word (Figure 8-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will generate a stop condition. To provide sequential reads the 24xx64 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 1FFF to address 0000 if the master acknowledges the byte received from the array address 1FFF.

FIGURE 8-2:
BUS ACTIVITY MASTER

RANDOM READ
S T A R T CONTROL BYTE ADDRESS HIGH BYTE XXX A C K A C K A C K ADDRESS LOW BYTE S T A R T CONTROL BYTE DATA BYTE S T O P P A C K N O A C K

SDA LINE BUS ACTIVITY

S1 0 1 0 AAA0 2 1 0

S 1 0 1 0 A A A1 2 1 0

X = Dont Care Bit

FIGURE 8-3:

SEQUENTIAL READ
CONTROL BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X S T O P P A C K A C K A C K A C K N O A C K

BUS ACTIVITY MASTER SDA LINE

BUS ACTIVITY

2000 Microchip Technology Inc.

DS21189D-page 9

24AA64/24LC64
NOTES:

DS21189D-page 10

2000 Microchip Technology Inc.

24AA64/24LC64
24xx64 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 24xx64 /P Package: Temperature Range: P SN SM ST = = = = Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body, EIAJ standard), 8-lead Plastic SOIC (208 mil Body, EIAJ standard), 8-lead TSSOP, 8-lead

Blank = 0C to +70C I = -40C to +85C E = -40C to +125C 24AA64 24AA64T 24AA64X 24AA64XT 64K bit 1.8V I2C Serial EEPROM 64K bit 1.8V I2C Serial EEPROM (Tape and Reel) 64K bit 1.8V I2C Serial EEPROM in alternate pinout (ST only) 64K bit 1.8V I2C Serial EEPROM in alternate pinout (ST only) 64K bit 2.5V I2C Serial EEPROM 64K bit 2.5V I2C Serial EEPROM (Tape and Reel) 64K bit 2.5V I2C Serial EEPROM in alternate pinout (ST only) 64K bit 2.5V I2C Serial EEPROM in alternate pinout (ST only)

Device:

24LC64 24LC64T 24LC64X 24LC64XT

Sales and Support

Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

2000 Microchip Technology Inc.

DS21189D-page 11

WORLDWIDE SALES AND SERVICE

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ASIA/PACIFIC (continued)
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Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Companys quality system processes and procedures are QS-9000 compliant for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001 certified.

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2000 Microchip Technology Inc.