Journal of the Korean Physical Society, Vol. 43, No. 1, July 2003, pp.

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Letters

Study of Gain Improvement in a Low Noise Amplier

Ju-Ho Son and Dong-Yong Kim
Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756 (Received 23 April 2003) We design a high-gain low noise amplier (LNA) by applying a 0.25 m CMOS process for Bluetooth. Using a cascade inverter, we design a one-stage amplier that uses a reference power supply without a choke inductor. An existing one-stage LNA was an improved structure having a low power gain of 10 15 dB. The designed 2.4-GHz LNA has a noise gure (NF) of 2.2 dB and a high power gain of 21 dB.
PACS numbers: 84.85 Keywords: LNA, CMOS

I. INTRODUCTION

The CMOS process, which is viewed positively because its can be used in the realization of low-cost, highly integrated RF transceivers, is desirable for small, light, lowpower, low-cost terminal equipment. Also, with this process, research on CMOS single chips for terminal equipment is actively being pursued [16]. If we take CMOS process techniques and a unity gain frequency into consideration, the realization of RF component development using the CMOS process is promising [7]. From the viewpoint of low noise amplier (LNA) development using CMOS technology, such a LNA would have a lower gain than a compound semiconductor. With the LNAs position at the front of the system, the LNAs low gain would determine the gain for whole system. Thus, we need to embody a circuit with a high gain to overcome the dierence between materials. The current one-stage LNAs have gains of 10 15 dB while compound semiconductors have gains of 15 20 dB at the rst stage. Even though the CMOS process can use two-stage amplication to get an amplication gain of 15 20 dB, that would require a complex circuit and would entail much noise [8,9]. This paper presents a circuit that amplies with onestage amplication for an amplication gain of 15 20 dB. We also present the design of 2.4 GHz LNA using 0.25 m CMOS technology, which is necessary at the front in a Bluetooth RF receiver.

The LNAs basic structure has a laminated type DC inductor and can achieve a high power gain by using cascade transistors. Although an inverter structure LNA cannot generate a sucient gain with only one-stage, a two-stage cascade with many transistors reduces the noise characteristics. For that reason, we adopt the inverter structure as shown in Fig. 1 [10]. In the case of a CMOS inverter, a small inductance is required to match the the input-output impedances, so our LNA does not use a choke-type inductor. Now, we analyze the small signal of the proposed CMOS complimentary amplifying circuit, which is composed of PMOS and NMOS components. When a small signal ows through a symmetric formation of the same-

II. DESIGN OF PROPOSED LNA

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Fig. 1. Proposed LNA. -L1-

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Journal of the Korean Physical Society, Vol. 43, No. 1, July 2003

Fig. 3. Noise characteristics and stability curves.

Fig. 2. Small-signal equivalent circuit of the LNA.

= (gm1 + gm2 )vin1 (gm1 + gm2 )(vin1 + vin2 )/2 (gm1 + gm2 ) (vin1 vin2 ) (6) = id2 . = 2 The output resistance is composed of the drain resistances of M3 and M4, so the output voltage is

sized MOS eld-eect transistors (MOSFETs) M1, M2, M3, and M4 in Fig. 1, the drain currents, id1 and id2 , have the same intensities with their sum being 0 due to their opposite signs: id1 + id2 = 0. (1)

vout =

2id1 (gm1 + gm2 )(vin1 vin2 ) . = gd3 + gd4 (gd3 + gd4 )

(7)

As a result, the proposed LNA has a voltage gain given by Av = vout (gm1 + gm2 ) . = vin1 vin2 (gd3 + gd4 ) (8)

From the small-signal equivalent signal in Fig. 2, id1 and id2 are id1 = gm2 (vin1 v3 ) + gm1 (vin1 v2 ), id2 = gm4 (vin2 v3 ) + gm3 (vin2 v2 ), (2a) (2b)

where the variables are dened in the gure. The sum of Eqs. (2a) and (2b) is id1 + id2 = gm2 (vin1 v3 ) + gm1 (vin1 v2 ) + gm4 (vin2 v3 ) + gm3 (vin2 v2 ) = 0. (3) M1, M2, M3, and M4 have the same sizes and have a symmetric structure, so the transconductances are the same, which means gm1 gm3 and gm2 gm4 . If the LNA is designed with the same component voltages v2 and v3 , we will nally get id1 + id2 = gm2 (vin1 v3 ) + gm1 (vin1 v3 ) + gm4 (vin2 v3 ) + gm3 (vin2 v3 ) = 0, where vin1 + vin2 . v3 = 2 Thus, id1 = (gm1 + gm2 )vin1 (gm1 + gm2 )v3 (5) (4)

An input-output-matched impedance is necessary for maximum power delivery, and with the theoretically matched impedance, the voltage gain Av is the same as the power gain.

III. SIMULATION RESULTS The simulation was done using a 1-poly 5-metal CMOS process and gave the components minimum noise gure (NFmin ) and designed noise gure (NF). The designed LNA had on NF of 2.2, a very low value, at the Bluetooth receivers band (2.4 2.5 GHz). Also the stability (K) had a value above 1, as shown in simulation results in Fig. 3, which means the proposed LNA is very stable. Figure 4 presents the characteristic curves of the S parameters, The gain curve S21 has a power gain of 21 dB at 2.4 2.5 GHz and corresponds to a high gain from a one-stage amplier with a cascade-structure inverter. The input-matching parameter S11 shows that the system is matched at 2 GHz, and the output-matching parameter S22 shows a value of 10 dB. Both prove that matching the input and output is necessary. With the

Study of Gain Improvement in a Low Noise Amplier Ju-Ho Son and Dong-Yong Kim

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laminated structure which could achieve a high gain of 21 dB with one-stage amplication.

REFERENCES
[1] P. K. Shaeer and T. H. Lee, in SOVC Dig. Tech. Papers (Honolulu, June, 1996), p. 32. [2] A. N. Karanicolas, in ISSCC Dig. Tech. Papers (San Francisco, Feb., 1996), p. 50. [3] R. G. Meyer and W. D. Mack, IEEE J. Solid State Cir. 29, 166 (1994). [4] D. B. M. Klaassen, in Proc. 22nd European Solid State Cir. Conference (Neuchatel, Sep., 1996), p. 40. [5] James Yung-Cheh Chang, M. S. thesis in Electrical Engineering (University of California, Los Angeles, 1992). [6] Robert Point, Michael Mendes and Willam Foley, Radio and Wireless Conference (Boston, Aug., 2002), p. 221. [7] J. Y. C. Chang, A. A. Abidi and M. Gaitan, IEEE Electron Dev. Lett. 14, 246 (1993). [8] J. C. Huang, Ro-Min Weng, Chih-Lung Hsiao and KunYi Lin, Microwave Conference (Taiwan, Dec., 2001), Vol. 3, p. 1028. [9] A. N. L. Chan, Chun Bing Guo and H. C. Luong, Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium (Sydney, May, 2001), Vol. 4, p. 890. [10] Yong-Sik Youn, Nam-Soo Kim, Jae-Hong Chang, YoungJae Lee and Hyun-Kyu Yu, Radio Frequency Integrated Circuits (RFIC) Symposium (Seattle, June, 2002), p. 271.

Fig. 4. Characteristics curve of the S parameter.

simulation results, we got a 2.2-dB noise gure: although that value which was not below 2 dB, we could get more than a 21-dB power gain.

IV. CONCLUSION This paper proposes a new-structure LNA based on silicon. We designed the LNA using a 1-poly 5-metal 0.25 m CMOS process and veried its performance through simulation. The proposed LNA had an inverter-