1.What is design hierarchy? What are its types?

Integrated circuits are quite complex in designing and fabricating, the task ismade easier by breaking the problem into design hierarchy where problem is viewed atdifferentlevels. Types of designsaresystem design, logicdesign,circuitdesign, physicaldesignandchipdesign. 2. What is IC? What are different IC layers? Integrated Circuit (ICs are microscopic electronic networks that are created in aspecial type of material called a semiconductor. !ilicon is a semiconductor which isused as a base material for ma"ority of modern electronic system. #ase or substrate,$xidelayer, !i$ % (insulating layer, metal layer (contact or via are some of IC layers. 3. What is meant by photolithography? (&ov'(ec )) *hotolithography is an important processing step involved in IC fabrication+ it isused to create patterned material layers to guide electrical signals on the chip. *hotomasking and photo etching are the two key process involved in photolithography formaking patterned materials. 4. What is RIE? (,ay'-une ). /I0 is /eactive Ion 0tching in which ioni1ed atoms of an inert gas such as argon(2r are mixed with etching assisting chemicals. The mixture is then excited with a radiofrequency (rf electric field in a manner that drives the ions'chemicals in a vertical up3down motion to etch away the surface. 5. What is feat re si!e? 4eature si1e or minimum feature si1e of an IC is the smallest dimension that canactually be transferred to a chip. ". What is meant by s bmicron and deep s bmicron? ,odern facilities can manufacture chips with minimum feature si1es smallerthan ) micron which is known as submicron technique. 2dvanced state of art fabrication plants can produce integrated circuits where the smallest feature size is less than 0.1 m wide which is called deep submicron technique. #.

$efine aspect ratio. It is the ratio between channel width (5 and channel length (6 . 2spect ratio 7 5'6 %. $ra& thesymbol of n'E( and p'E(. $E)* R(+E,(-' E.EC(R-,IC/* ,$C-++0,IC* (I-,E,1I,EERI,1 Question Bank 2. $efine threshold 3oltage. TheThresholdvoltage, 8 T for a,$! transistorcanbedefinedasthevoltageapplied between the gate and the source of the ,$! transistor below which the drain tosource current, I (! effectively drops to 1ero. Threshold voltage is the voltage at whichthe device turns on or starts conducting. 14. What is self aligned techni5 e? In the ,$!40T fabrication process, gate and n9 or p9 regions automaticallyaligned to each other which is known as self aligned technique. 11. What is C+)? *lanari1ation is mandatory in chips that use more than two or three metallayers. Themost commontechniqueisChemical3,echanical*olishing (C,* which iscapable of producing very flat surfaces. 12. What is meant bydoping? .ist someof dopants. The process of adding impurity atoms is called doping. Impurities themselvesarecalled dopants, e.g. 3arsenic andsilicon. 13. What is .$$? (&ov'(ec ). 6(( is 6ightly (oped (rain structure. This structure is used to reduce somesmall device effect due to very energetic partials called hot electrons and hot holes. 14. What are generations of Integration Circ its?

!!I (!mall !cale Integration , ,!I (,edium !caleIntegration ,6!I (6arge!caleIntegration , 86!I (8ery6arge !caleIntegration ,:6!I(:ltra6arge !caleIntegration ,;!I(;iga!caleIntegration. 15. 1i3e thebasic processfor ICfabrication. !ilicon wafer *reparation, 0pitaxial ;rowth, $xidation, *hotolithography, (iffusion, IonImplantation, Isolation technique, ,etalli1ation, 2ssembly processing < *ackaging. 1". What are the different layers in +-/ transistors? 6 (rain, !ource< ;ate 1#. 1i3e thedifferent types of C+-/ process? *3well process,&3well process, !ilicon3$n3Insulator*rocess,Twin3 tub*rocess. 1%. What are the steps in3ol3ed in t&in6t b process? Tub 4ormation, Thin3oxide Construction, !ource < (rain Implantation, Contactcut definition, ,etalli1ation. 12. What are thead3antagesof C+-/ process? 6ow power (issipation, =igh *acking density, #i directional capability, 6owInput Impedance, 6ow delay !ensitivity to load. 24. What is p ll do&n de3ice? 2 device connected so as to pull the output voltage to the lower supply voltageusually .8 is called pull down device. n,$! is good for logic >.? so it is known as pulldown device. 21. What is p ll p de3ice? 2 device connected so as to pull the output voltage to the upper supply voltage usually8 (( is called pull up device. p,$! is good for logic >)? so it is known as pull up device. 22. What are the common materials sed as mas7? *hotoresist, twin dioxide (!i$ % , *olisilicon (polycrystalline silicon , !ilicon nitrate(!i& . 23. What is /tic7 $iagram? What are its ses?

It is used to convey information through the use of color code. 2lso it is thecartoon of a chip layout. It can be drawn much easier and faster than a complex layout.These are especially important tools for layout built from large cells. 24. 1i3e the3ario s color coding sedin stic7diagram? ;reen @ n3diffusion, /ed3 polysilicon, #lue @metal, Aellow3 implant, #lack3contact areas. 25. What are design r les? (esign rules are the communication link between the designer specifyingrequirements and the fabricator who materiali1es them. (esign rules are used toproduce workable mask layouts from which the various layers in silicon will be formedor patterned. 2". What is .ambda 8 B 9 6 based design r les? Theserules populari1edby,ead and Conway arebased on asingle parameter ,which characteri1es the linear feature @ the resolution of the complete waferimplementation process and permits first order scaling. They have been widely used,particularly in the educational context and in the design of multi pro"ect chips. Inlambda based design rules, all paths in all layers will be dimensioned in units andsubsequently can be allocated an appropriate value compatible with the feature si1e ofthe fabrication process. (esign rules+ specify line widths, separations, and extensions interms of . 2#. .ist anyt&otypes of layo t design r les. (&ov'(ec .C , (&ov'(ec )) 3 rule , 3 rule. 2%. What are the ma:or types of design r les? ,a"or types of design rules are minimum feature rule, minimum spacing rule,surround rule and exact si1e rule. 22.

What is the ma; contact &idth of metal1 line &ith acti3e poly? D , (&ov'(ec )) 34. $efine yield. (,ay'-une)) 100* r TotalNumbeoddie NumberofgoY < %100* DA eY E <I1=0E/(I-,/> ). 0xplain design hierarchy with neat diagram. (&ov'(ec ). %. 0xplain in detail about photolithography and pattern transfers. (,ay'-une ). D. 5rite notes on basic ,$! transistor operation.F. 0xplain C,$! fabrication technique with neat diagram. (,ay'-une ). G. 5ith neat diagrams explain the steps involved in the p3well fabrication process. (2pril',ay .C (&ov'(ec )) H. 5ith neat diagrams explain the steps involved in the n3well fabrication process.(&ov'(ec ). I. (escribe in detail with neat sketches the Twin Tub method of C,$! fabrication. (2pril',ay .C