Direct-mapped caches

If the cache contains 2k bytes, then the k least significant bits (LSBs) are used as the index. data from address i would be stored in block i mod 2k. For example, data from memory address 11 maps to cache block 3 on the right, since 11 mod 4 = 3 and since the lowest two bits of 1011 are 11.

Memory Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Index 0 1 2 3

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Tags & Valid bits

To find data stored in the cache, we need to add tags to distinguish between different memory locations that map to the same cache block. We include a single valid bit per block to distinguish full and empty blocks.
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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Index 00 01 10 11

Tag 00 11 01 01

Valid 1 1 1 1

Data

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How big is the cache?

For a byte-addressable machine with 16-bit addresses with a cache with the following characteristics: It is direct-mapped (as discussed last time) Each block holds one byte The cache index is the four least significant bits Two questions: How many blocks does the cache hold?

How many bits of storage are required to build the cache (e.g., for the data array, tags, valid)?
COMPUTER

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How big is the cache?

For a byte-addressable machine with 16-bit addresses with a cache with the following characteristics: It is direct-mapped (as discussed last time) Each block holds one byte The cache index is the four least significant bits Two questions: How many blocks does the cache hold? 4-bit index -> 24 = 16 blocks How many bits of storage are required to build the cache (e.g., for the data array, tags, etc.)? tag size = 12 bits (16 bit address - 4 bit index) (12 tag bits + 1 valid bit + 8 data bits) x 16 blocks = 21 bits x 16 = 336 bits
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More cache organizations

Today, well explore some alternate cache organizations. How can we take advantage of spatial locality too? How can we reduce the number of potential conflicts?

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Memory System Performance

To examine the performance of a memory system, we need to focus on a couple of important factors. How long does it take to send data from the cache to the CPU? How long does it take to copy data from memory into the cache? How often do we have to access main memory? There are names for all of these variables. The hit time is how long it takes data to be sent from the cache to the processor. This is usually fast, on the order of 1-3 clock cycles. The miss penalty is the time to copy data from main memory to the cache. This often requires dozens of clock cycles (at least). The miss rate is the percentage of misses.
CPU

A little static RAM (cache)

Lots of dynamic RAM

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Average memory access time

The average memory access time, or AMAT, can then be computed. AMAT = Hit time + (Miss rate x Miss penalty) This is just averaging the amount of time for cache hits and the amount of time for cache misses. How can we improve the average memory access time of a system? Obviously, a lower AMAT is better. Miss penalties are usually much greater than hit times, so the best way to lower AMAT is to reduce the miss penalty or the miss rate. However, AMAT should only be used a general guideline. Remember that execution time is still the best performance metric.
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Performance example
Assume the cache hit ratio is 97% and the hit time is one cycle, but the miss penalty is 20 cycles. AMAT= Hit time + (Miss rate x Miss penalty) = = How can we reduce miss rate?

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Performance example
Assume the cache hit ratio is 97% and the hit time is one cycle, but the miss penalty is 20 cycles. AMAT= Hit time + (Miss rate x Miss penalty) = 1 cycle + (3% x 20 cycles) = 1.6 cycles If the cache was perfect and never missed, the AMAT would be one cycle. But even with just a 3% miss rate, the AMAT here increases 1.6 times! How can we reduce miss rate?

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Spatial locality
One-byte cache blocks dont take advantage of spatial locality, which predicts that an access to one address will be followed by an access to a nearby address. What can we do?

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Spatial locality
What we can do is make the cache block size larger than one byte.
Memory Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Here we use twobyte blocks, so we can load the cache with two bytes at a time. If we read from address 12, the data in addresses 12 and 13 would both be copied to cache block 2.
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Index 0 1 2 3

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Block addresses
Now how can we figure out where data should be placed in the cache? Its time for block addresses! If the cache block size is 2n bytes, we can conceptually split the main memory into 2n-byte chunks too. To determine the block address of a byte Byte Block address i, you can do the integer division Address Address i / 2n Our example has two-byte cache blocks, so we can think of a 16-byte main memory as an 8-block main memory instead. For instance, memory addresses 12 and 13 both correspond to block address 6, since 12 / 2 = 6 and 13 / 2 = 6.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
1998 Morgan Kaufmann Publishers

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Cache mapping
Once you know the block address, you can map it to the cache as before: find the remainder when the block address is divided by the number of cache blocks. In our example, Byte Block Address Address memory block 6 0 belongs in cache 0 1 block 2, since 2 1 6 mod 4 = 2. 3 This corresponds 4 2 5 to placing data 6 from memory 3 7 byte addresses 8 4 12 and 13 into 9 cache block 2. 10 5
11 12 13 14 15 6 7
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Index 0 1 2 3

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Data placement within a block

When we access one byte of data in memory, well copy its entire block into the cache, to hopefully take advantage of spatial locality. In our example, if a program reads from byte address 12 well load all of memory block 6 (both addresses 12 and 13) into cache block 2. Note byte address 13 corresponds to the same memory block address! So a read from address 13 will also cause memory block 6 (addresses 12 and 13) to be loaded into cache block 2. To make things simpler, byte i of a memory block is always stored in byte i of the corresponding cache block.

Byte Address 12 13

Byte 0

Cache Byte 1 Block 2

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Locating data in the cache

Lets say we have a cache with 2k blocks, each containing 2n bytes. We can determine where a byte of data belongs in this cache by looking at its address in main memory. k bits of the address will select one of the 2k cache blocks. The lowest n bits are now a block offset that decides which of the 2n bytes in the cache block will store the data.
(m-k-n) bits m-bit Address Tag k bits Index n-bit Block Offset

Our example used a 22-block cache with 21 bytes per block. Thus, memory address 13 (1101) would be stored in byte 1 of cache block 2.
1 bit 4-bit Address 1 2 bits 10 1 1-bit Block Offset

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A picture
Tag Address (4 bits) 1 Index (2 bits) 10 2 1 Block offset

Index Valid 0 1 2 3

Tag

Data

8 Mux 8

Hit COMPUTER

Data

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An exercise
Tag Address (4 bits) n Index (2 bits) nn 2 n Block offset

Index Valid 1 0 1 1 1 2 0 3

Tag 0 1 0 1 = 0xCA 0xDE 0xBE 0xFE 8 0

Data 0xFE 0xAD 0xEF 0xED 8 Mux 8 1

For the addresses below, what byte is read from the cache (or is there a miss)? 1010 1110 0001 1101

Hit
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Data

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An exercise
Tag Address (4 bits) n Index (2 bits) nn 2 n Block offset

Index Valid 1 0 1 1 1 2 0 3

Tag 0 1 0 1 = 0xCA 0xDE 0xBE 0xFE 8 0

Data 0xFE 0xAD 0xEF 0xED 8 Mux 8 1

For the addresses below, what byte is read from the cache (or is there a miss)? 1010 1110 0001 1101
(0xDE) (miss, invalid) (0xFE) (miss, bad tag)

Hit
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Data

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Using arithmetic
An equivalent way to find the right location within the cache is to use arithmetic again.
(m-k-n) bits m-bit Address Tag k bits Index n-bit Block Offset

We can find the index in two steps, as outlined earlier. Do integer division of the address by 2n to find the block address. Then mod the block address with 2k to find the index. The block offset is just the memory address mod 2n. For example, we can find address 13 in a 4-block, 2-byte per block cache. The block address is 13 / 2 = 6, so the index is then 6 mod 4 = 2. The block offset would be 13 mod 2 = 1.

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A diagram of a larger example cache

Here is a cache with 1,024 blocks of 4 bytes each, and 32-bit memory addresses.
Address (32 bits) 20 10 2 bits

Index Valid 0 1 2 3 ... ... 1022 1023 Tag

Tag

Data

8 =

8 Mux 8

Hit
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A larger example cache mapping

Where would the byte from memory address 6146 be stored in this direct-mapped 210-block cache with 22-byte blocks? We can determine this with the binary force. 6146 in binary is 00...01 1000 0000 00 10. The lowest 2 bits, 10, mean this is the second byte in its block. The next 10 bits, 1000000000, are the block number itself (512). Equivalently, you could use your arithmetic instead. The block offset is 6146 mod 4, which equals 2. The block address is 6146/4 = 1536, so the index is 1536 mod 1024, or 512.

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A larger diagram of a larger example cache mapping

Address (32 bits) 0000 .... 0001 20 1000000000 10 10 2 bits

Index Valid 0 1 2 ... 512 ... 1022 1023 Tag

Tag

Data

8 =

8 Mux 8

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Hit COMPUTER

Data
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What goes in the rest of that cache block?

The other three bytes of that cache block come from the same memory block, whose addresses must all have the same index (1000000000) and the same tag (00...01).
Address (32 bits) 0000 .... 0001 20 1000000000 10 10

Index Valid ... 512 ... Tag

Tag

Data

8 Mux 8

Hit
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The rest of that cache block

Again, byte i of a memory block is stored into byte i of the corresponding cache block. In our example, memory block 1536 consists of byte addresses 6144 to 6147. So bytes 0-3 of the cache block would contain data from address 6144, 6145, 6146 and 6147 respectively. You can also look at the lowest 2 bits of the memory address to find the block offsets. Block offset 00 01 10 11
Index Valid ... 512 ... COMPUTER Tag

Memory address 00..01 1000000000 00 00..01 1000000000 01 00..01 1000000000 10 00..01 1000000000 11
Data

Decimal 6144 6145 6146 6147

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Disadvantage of direct mapping

The direct-mapped cache is easy: indices and offsets can be computed with bit operators or simple arithmetic, because each memory address belongs in exactly one block. Memory Address But, what happens if a 0000 program uses addresses 0001 2, 6, 2, 6, 2, ?
0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Index 00 01 10 11

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Disadvantage of direct mapping

The direct-mapped cache is easy: indices and offsets can be computed with bit operators or simple arithmetic, because each memory address belongs in exactly one block. Memory Address However, this isnt really 0000 flexible. If a program uses 0001 addresses 2, 6, 2, 6, 2, ..., 0010 then each access will result 0011 in a cache miss and a load 0100 Index 0101 into cache block 2. 00 0110 This cache has four blocks, 01 0111 but direct mapping might 10 1000 11 not let us use all of them. 1001 1010 This can result in more 1011 misses than we might like. 1100
1101 1110 1111 COMPUTER

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A fully associative cache

A fully associative cache permits data to be stored in any cache block, instead of forcing each memory address into one particular block. When data is fetched from memory, it can be placed in any unused block of the cache. This way well never have a conflict between two or more memory addresses which map to a single cache block. In the previous example, we might put memory address 2 in cache block 2, and address 6 in block 3. Then subsequent repeated accesses to 2 and 6 would all be hits instead of misses. If all the blocks are already in use, its usually best to replace the least recently used one, assuming that if it hasnt been used it in a while, it wont be needed again anytime soon.

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The price of full associativity

However, a fully associative cache is expensive to implement. Because there is no index field in the address anymore, the entire address must be used as the tag, increasing the total cache size. Data could be anywhere in the cache, so we must check the tag of every cache block. Thats a lot of comparators!
Address (32 bits) 32 Tag = Index Valid ... ... ... Tag (32 bits) Data

Hit

= COMPUTER

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Set associativity
An intermediate possibility is a set-associative cache. The cache is divided into groups of blocks, called sets. Each memory address maps to exactly one set in the cache, but data may be placed in any block within that set. If each set has x blocks, the cache is an x-way associative cache. Here are several possible organizations of an eight-block cache.
1-way associativity 8 sets, 1 block each Set 0 1 2 3 4 5 6 7 COMPUTER 2-way associativity 4 sets, 2 blocks each Set 0 0 1 2 1 3 4-way associativity 2 sets, 4 blocks each Set

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Locating a set associative block

We can determine where a memory address belongs in an associative cache in a similar way as before. If a cache has 2s sets and each block has 2n bytes, the memory address can be partitioned as follows.
(m-s-n) Address (m bits) Tag s Index n Block offset

Our arithmetic computations now compute a set index, to select a set within the cache instead of an individual block. Block Offset = Memory Address mod 2n

Block Address = Memory Address / 2n Set Index = Block Address mod 2s

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Example placement in set-associative caches

Where would data from memory byte address 6195 be placed, assuming the eight-block cache designs below, with 16 bytes per block? 6195 in binary is 00...0110000 011 0011. Each block has 16 bytes, so the lowest 4 bits are the block offset. For the 1-way cache, the next three bits (011) are the set index. For the 2-way cache, the next two bits (11) are the set index. For the 4-way cache, the next one bit (1) is the set index. The data may go in any block, shown in green, within the correct set.
1-way associativity 8 sets, 1 block each Set 0 1 2 3 4 5 6 7
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2-way associativity 4 sets, 2 blocks each Set 0

4-way associativity 2 sets, 4 blocks each Set 0

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Block replacement
Any empty block in the correct set may be used for storing data. If there are no empty blocks, the cache controller will attempt to replace the least recently used block, just like before. For highly associative caches, its expensive to keep track of whats really the least recently used block, so some approximations are used. We wont get into the details.
1-way associativity 8 sets, 1 block each Set 0 1 2 3 4 5 6 7 2-way associativity 4 sets, 2 blocks each Set 0 0 1 2 1 3 4-way associativity 2 sets, 4 blocks each Set

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LRU example
Assume a fully-associative cache with two blocks, which of the following memory references miss in the cache. assume distinct addresses go to distinct blocks
addresses A B A C B A B
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0 Tags --

1 --

LRU 0

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LRU example
Assume a fully-associative cache with two blocks, which of the following memory references miss in the cache. assume distinct addresses go to distinct blocks
addresses miss On a miss, we replace the LRU. On a hit, we just update the LRU. miss A B A miss miss miss C B B A B B
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0 Tags

LRU 0 1 0 1 0 1 0 1

-A A A A

--B B C C A A

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Exercise
Assume you have a fully associative cache with 4 entries. For the following memory block address sequence, which entry becomes the LRU at the end? 8 9 5 2 6 5 9 10 3

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Set associative caches are a general idea

By now you may have noticed the 1-way set associative cache is the same as a direct-mapped cache. Similarly, if a cache has 2k blocks, a 2k-way set associative cache would be the same as a fully-associative cache.
1-way 8 sets, 1 block each Set 0 1 2 3 4 5 6 7 direct mapped Set 0 0 1 0 2 1 3 fully associative 2-way 4 sets, 2 blocks each Set 4-way 2 sets, 4 blocks each Set 8-way 1 set, 8 blocks

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Mind twist
Can we have odd number of blocks in a set?

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2-way set associative cache implementation

How does an implementation of a 2-way cache compare with that of a fully-associative cache?
Index Valid 0 ... 2k Tag Address (m bits) Tag (m-k-n) Index k Block offset

Data

Valid

Tag

Data

2n

2n

Only two comparators are needed. The cache tags are a little shorter too.
COMPUTER

2-to-1 mux Hit Data 2n

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Exercise
For a 64KB cache, how do you organize it for a direct mapped cache? What about 2-way set associative cache? 96KB cache?

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Summary
Larger block sizes can take advantage of spatial locality by loading data from not just one address, but also nearby addresses, into the cache. Associative caches assign each memory address to a particular set within the cache, but not to any specific block within that set. Set sizes range from 1 (direct-mapped) to 2k (fully associative). Larger sets and higher associativity lead to fewer cache conflicts and lower miss rates, but they also increase the hardware cost. In practice, 2-way through 16-way set-associative caches strike a good balance between lower miss rates and higher costs.
COMPUTER

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