Topics
High-density memory architecture
Memories:
ROM; SRAM; DRAM.
PLAs.
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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Memory operation
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Read-only memory (ROM)
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Address is divided into row, column.
Row may contain full word or more than one word.
Selected row drives/senses bit lines in columns. I Amplifiers/drivers read/write bit lines.
ROM core is organized as NOR gates pull-down transistors of NOR determine programming. I Erasable ROMs require special processing that is not typically available. I ROMs on digital ICs are generally maskprogrammedplacement of pull-downs determines ROM contents.
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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ROM core circuit
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Static RAM (SRAM)
Core cell uses six-transistor circuit to store value. I Value is stored symmetricallyboth true and complement are stored on crosscoupled transistors. I SRAM retains value as long as power is applied to circuit.
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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SRAM core cell
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SRAM core operation
Read:
precharge bit and bit high; set select line high from row decoder; one bit line will be pulled down.
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Write:
set bit/bit to desired (complementary) values; set select line high; drive on bit lines will flip state if necessary.
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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SRAM sense amp
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Sense amp operation
Differential pairtakes advantage of complementarity of bit lines. I When one bit line goes low, that arm of diff pair reduces its current, causing compensating increase in current in other arm. I Sense amp can be cross-coupled to increase speed.
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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3-transistor dynamic RAM (DRAM)
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3-T DRAM core cell
First form of DRAMmodern commercial DRAMs use one-transistor cell. I 3-transistor cell can easily be made with a digital process. I Dynamic RAM loses value due to charge leakagemust be refreshed.
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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3-T DRAM operation
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One-Transistor DRAM
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Value is stored on gate capacitance of t1. I Read:
read = 1, write = 0, read_data is precharged; t1 will pull down read_data if 1 is stored.
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Write:
read = 0, write = 1, write_data = value; guard transistor writes value onto gate capacitance.
Capacitor is not parasitic but intentional. Read operation (precharge bit line) is destructive; refresh is necessary. Special requirements for sense amplifiers.
word
bit
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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Flash Memory
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Programmable logic array (PLA)
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Non-volatile memory (not erased when SiO2 insulator power is off). By applying high Regular gate voltages on the Floating gate regular gate, charge gets trapped on n+ n+ p-tub floating gate.
Used to implement specialized logic functions. I A direct implementation of the sum-ofproducts form. I A PLA decodes only some addresses (input values); a ROM decodes all addresses. I PLA not as common in CMOS as in nMOS, but is used for some logic functions.
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
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PLA organization
p1 p2 AND plane p3 p4 OR plane I
PLA structure
AND plane, OR plane, inverters together form complete two-level logic functions. I Both AND and OR planes are implemented as NOR circuits. I Pull-down transistors form programming/personality of PLA. Transistors may be referred to as programming tabs.
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
i0 i0
Revised by SG: February 29, 2004 Modern VLSI Design 3e: Chapter 6, Part 2
i1 i1
product term
f0
f1
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Precharged bus circuit (PLA NOR gate)
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