The Communication System For Advanced Automotive Control Systems
The Communication System For Advanced Automotive Control Systems
The Communication System For Advanced Automotive Control Systems
Outline:
• Scalable static and dynamic message transmission (deterministic and flexible)
• High net data rate of 5 Mbit/sec; gross data rate approximately 10Mbit/sec
• Scalable fault-tolerance (single and dual channel)
• Error containment on the physical layer through an independent Bus Guardian
• Fault tolerant clock synchronisation (global time base)
Motivation
• Deterministic and fault tolerant bus system for advanced automotive control
applications
FlexRay
requirements
MOST
CAN
LIN
Goals
Basic Features
Redundancy
ECU
Node
Permanent
Power • 1 or 2 bus drivers connected to one
communication controller
ECU • Connection to “permanent power”
Communication Controller
Guardian
Guardian
Bus
Data Transmission
node A node B node C node D node E node F node G
channel 1
messages channel 1
slot 0 1 2 3 4 5 6 7 8 9 1011 12 1314 15
1 2 3 4 5 6 7 9 11 12 14 15 frame
... (static part)
da db dc dd de df dg dk dl dm do dq
ID
A B C B D E F C A A F E
datatype
messages channel 2
slot 0 1 2 3 4 5 6 7 8 9 1011 12 13 1415
node
1 2 3 4 5 8 9 11 12 13 frame
...
(dynamic part)
d´a dh di d´d d´e dj d´k d´l dn dp
ID
A B C B D G C A A G
static part dynamic part
datatype
node
communication cycle
ID: Identifier, 10 bit, range: (110 ... 102310), defines the slot number in the static
part or the priority in the dynamic part
MUX: Multiplex Field, 1 bit, enables a node to transmit different messages with the
same ID
SYNC: Synchronisation Field, 1 bit, tags the frames which will be used for the clock
synchronisation
LEN: Length field, 4 bit, LEN = number of used data bytes (010 ... 1210)
CYCLE: Cycle Counter, 8 bit, range: (010 ... 25510). The CYCLE-field will be used as
cycle counter or as a data byte. The cycle counter will be incremented
consistently in all communication controllers at the beginning of each
communication cycle
SYNC: Synchronisation field, 1 bit, tags the frames which contain the cycle counter
• Support of all topologies (single channel, dual channel, mixed single and dual
channel)
• Only nodes in the static part can participate in the clock synchronisation
(with frames which are tagged with the SYNC bit)