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Digital Circuits: Experiment 2 2012-13/I Combinational Circuits For Binary Addition

The document describes an experiment involving combinational logic circuits for binary addition and subtraction. It involves setting up half adder, full adder, and full subtractor circuits using logic gates from integrated circuit chips. The circuits are tested by applying input combinations and verifying the output values match the expected logic expressions.

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Sidhartha Sankar Rout
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55 views2 pages

Digital Circuits: Experiment 2 2012-13/I Combinational Circuits For Binary Addition

The document describes an experiment involving combinational logic circuits for binary addition and subtraction. It involves setting up half adder, full adder, and full subtractor circuits using logic gates from integrated circuit chips. The circuits are tested by applying input combinations and verifying the output values match the expected logic expressions.

Uploaded by

Sidhartha Sankar Rout
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Circuits

Experiment 2 Combinational Circuits for Binary A ition 2012-13/I

We will use various kinds of CMOS gates as required for the implementation of the logic. The pin connections of all the ICs are the same as given in !ig" 1 #a$ of the write-up for Experiment 1. emem!er that for all future e"periments# the connection of the $ CC % $&& and 'nd pins of each IC chip used must !e connected to the ()$ and 'nd !uses on the !read!oard# using *& and +,-C. wires respectivel/. These !uses are alwa/s connected# !/ *& and +,-C. 0umper wires to the d-c power suppl/. %art A" De &organ's (a)s &e Morgan1s laws state that 2- ( +31 4 -1 +1 and 2- +31 4 -1 ( +1. $erif/ these laws !/ proceeding step !/ step as follows5 1. Set up a circuit consisting of two 6O gates and one -6& gate out of the given IC chips to perform the function 7 4 -1 +1# using a 6O gate with its two inputs connected together to perform the 6OT function. &raw the circuit diagram and mark the IC pin num!ers on the diagram# !/ 6O -8# 6O -9#....-6&-8# -6&-9...and so on. 2" Connect two input switches to the two inputs - and +# and the output 7 to the input of an ,*& displa/ !/ 0umper wires. -ppl/ the four possi!le com!inations of 2!inar/3 values to the inputs - and + !/ means of the input switches and ta!ulate the corresponding values of the output 7 as o!served on the ,*& displa/..$erif/ that the truth ta!le so o!tained is the same as that of a 6O gate. 3" epeat steps 8 and 9 using an O gate instead of an -6& gate to verif/ that the truth ta!le of the function 7 4 -1 ( +1 is the same as that of a 6-6& gate. er using +ates 7 !its as output

%art B" Binary *alf A

- !inar/ :alf -dder adds two !its - and + to generate S;M and Caccording to the following +oolean e"pressions for the outputs5 S;M 4 -1 + ( - +1 4 - + and C- 7 4 - +.

1" Set up the circuit of a :alf -dder using an <O gate and an -6& gate out of the given IC chips. -ppl/ the inputs - and + from two input switches and o!serve the outputs S;M and C- 7 on two ,*& displa/s for all com!inations of the inputs. 2" Ta!ulate these values and verif/ the operation of the :alf -dder. &o 6ot dismantle this circuit as it will !e used as part of the circuit to !e used in the ne"t =art. %art C" Binary !ull A er using +ates

- !inar/ >ull -dder adds two !its - and + along with a carr/-in !it C to generate S;M and C- 7 !its as output. It can !e implemented with two :alf -dders and one -6& gate. In this implementation# one :alf -dder is used to add the !its - and + to generate intermediate sum and carr/ !its S8 and C8. -nother :alf -dder is then used to generate the final S;M !/ adding the carr/ in !it C to the S8 !it generated !/ the first :alf -dder5 S;M 4 S8 C. 6ote that the logic for the S;M output of a >ull -dder is thus S;M 4 - + C.

The carr/ !it C9 24 S8 C3 generated !/ this :alf -dder is com!ined with S8 to generate the final C- 7 output given !/ the e"pression5 C- 7 4 C8 ( C9. The logic for the C- 7 output of a >ull -dder is thus C- 7 4 - + ( S8 C 4 - + ( - C ( + C. 1" Set up another :alf -dder using another <O and another -6& gate out of the same ICs used in step B"1# and connect the C input and the S8 output generated !/ the first :alf -dder as its inputs to generate the final S;M output and the C9 output. 2. $erif/ that the logic for C- 7 can also !e implemented with an <O gate 2i.e. C- 7 4 C8 C93# there!/ eliminating the need for a separate O chip and making the complete realisation of the >ull -dder possi!le using two IC chips. 'enerate the final C- 7 output from the intermediate carr/ outputs C8 and C9# using one of the unused gates in the <O chip. 3" $erif/ the truth ta!le e"perimentall/ !/ appl/ing the inputs -# + and C through three input switches and displa/ing the S8# C8# C9# S;M and C- 7 outputs. -gain# do not dismantle this circuit as it will !e used with a small change in the ne"t =art. %art D" Binary !ull ,ubtractor using +ates - !inar/ >ull Su!tractor su!tracts the Su!trahend !it + and a +orrow-in !it C from the Minuend !it - to generate &I>>* *6C* and +O OW !its as output. Write down the complete truth ta!le of a >ull Su!tractor and verif/ that the &I>>* *6C* and +O OW outputs are given !/ the following logic e"pressions5 &I>>* *6C* 4 - + C and +O OW 4 -1 + ( -1 C ( + C. Thus the &I>>* *6C* output of a >ull Su!tractor has the same logic as that of the S;M output of a >ull -dder# and the +O OW output of a >ull Su!tractor can !e o!tained from the C- 7 output of a >ull -dder simpl/ !/ replacing - !/ -1. 1" ;se the last remaining gate in the given <O chip to generate -1# and modif/ the >ull -dder circuit appropriatel/ for performing su!traction. 2" $erif/ the truth ta!le e"perimentall/ !/ appl/ing the inputs -# + and C through three input switches and displa/ing the &I>>* *6C* and +O OW outputs on ,*&s.

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