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Dynamic CMOS

Dynamic CMOS circuits rely on temporary storage of signal values on node capacitances rather than direct connections to power rails. Dynamic gates have two phases, precharge and evaluate, and require fewer transistors than static gates but impose timing constraints. Domino logic is a popular dynamic style that allows cascading of gates for high speed but only implements non-inverting logic.

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115 views

Dynamic CMOS

Dynamic CMOS circuits rely on temporary storage of signal values on node capacitances rather than direct connections to power rails. Dynamic gates have two phases, precharge and evaluate, and require fewer transistors than static gates but impose timing constraints. Domino logic is a popular dynamic style that allows cascading of gates for high speed but only implements non-inverting logic.

Uploaded by

Poornanand Naik
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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VLSI Design Dynamic CMOS

[Adapted from Rabaey Rabaeys s Digital Integrated Circuits, 2002, 2002 J J. Rabaey et al al.] ]

Dynamic CMOS.1

Dynamic CMOS

In static circuits at every point in time (except ( when switching) the output is connected to either GND or VDD via a low resistance path.

fan-in of N requires 2N devices

Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.

requires i only l N+2t transistors i t takes a sequence of precharge and conditional evaluation phases to realize logic functions

Dynamic CMOS.2

Dynamic Gate

CLK In1 In2 In3 CLK

Mp

CLK Out CL

Mp

Out A C B

PDN

Me

CLK

Me

Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)


Dynamic CMOS.3

Dynamic Gate

CLK In1 In2 In3 CLK

Mp

CLK Out CL

off Mp on

1 Out !((A&B)|C) C

PDN

A B

Me

CLK

off Me on

Two phase operation g ( (CLK = 0) ) Precharge Evaluate (CLK = 1)


Dynamic CMOS.4

Conditions on Output

Once the output of O f a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation.

Output p can be in the high g impedance p state during g and after evaluation (PDN off), state is stored on CL

Dynamic CMOS.5

Properties of Dynamic Gates


Logic function is implemented by the PDN only


number of transistors is N + 2 (versus 2N for static complementary CMOS) should be smaller in area than static complementary CMOS

Full swing outputs (VOL = GND and VOH = VDD) Nonratioed - sizing of the devices is not important for proper functioning (only for performance) F t switching Faster it hi speeds d

reduced load capacitance due to lower number of transistors per gate (Cint) so a reduced logical effort reduced load capacitance due to smaller fan-out (Cext) no Isc, so all the current provided by PDN goes into discharging CL Ignoring the influence of precharge time on the switching speed of the gate, tpLH = 0 but the presence of the evaluation transistor slows down the tpHL

Dynamic CMOS.6

Properties of Dynamic Gates, cont


Power dissipation should be better


consumes only dynamic power no short circuit power consumption since the pull-up path is not on when evaluating lower CL- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two) by construction can have at most one transition per cycle no glitching

But p power dissipation p can be significantly g y higher g due to


higher transition probabilities extra load on CLK

PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all equal to VTn

low noise margin (NML)

Needs a precharge clock

Dynamic CMOS.7

Dynamic Behavior
CLK Out In1 In2 In3
0.5 1.5 2.5

Evaluate

In4 CLK
-0.5 0

In & CLK

Out
0.5

Precharge
1

Time ns Time,

#Trns 6
Dynamic CMOS.8

VOH 2.5V

VOL 0V

VM

NMH

NML VTn

tpHL

tpLH

tp

VTn 2.5-VTn

110ps 0ns 83ps

Cascading Dynamic Gates


V CLK Out1 I In CLK
Me

CLK
Mp

CLK

Mp

Out2

In Out1 VTn V t

CLK

Me

Out2

Only a single 0 1 transition allowed at the inputs during the evaluation period!
Dynamic CMOS.9

Domino Logic

CLK In1 In2 In3 CLK

Mp

11 10

Out1

CLK
00 01

Mp

Out2

PDN

In4 In5

PDN

Me

CLK

Me

Dynamic CMOS.10

Why Domino?

CLK In1 Ini Inj CLK PDN Ini Inj PDN Ini Inj PDN Ini Inj PDN

Dynamic CMOS.11

Properties of Domino Logic


Only non-inverting logic can be implemented, fixes include


can reorganize the logic using Boolean transformations use differential logic (dual rail) use np-CMOS p (zipper) ( pp )

Very high speed


tpHL

=0

static inverter can be optimized to match fan-out (separation of fan-in and fan-out capacitances)

Dynamic CMOS.12

Differential (Dual Rail) Domino


off CLK Out = AB 1 A B CLK
Me Mp Mkp

on
Mkp Mp

CLK 1 0 !Out = !(AB) !B

0 !A

Due to its high-performance, differential domino is very popular and is used in several commercial microprocessors!
Dynamic CMOS.13

np-CMOS (Zipper)
CLK In1 In2 In3 CLK
Me Mp

11 10

Out1

!CLK In4

Me

PUN
00 01

PDN

In5
Mp

!CLK to other PDNs

Out2 (to PDN)

to other PUNs

Only 0 1 transitions allowed at inputs of PDN O l 1 0 transitions Only t iti allowed ll d at ti inputs t of f PUN
Dynamic CMOS.14

How to Choose a Logic Style


Must consider ease of f design, robustness (noise ( immunity), ) area, speed, power, system clocking requirements, fan-out, functionality, ease of testing
4-input NAND Style Comp Static CPL* domino DCVSL* * Dual Rail # Trans 8 12 + 2 6+2 10 Ease 1 2 4 3 Ratioed? Delay Power no no no yes 3 4 2 1 1 3 2 + clk 4

Current trend is towards an increased use of complementary static CMOS: design support through DA t l robust, tools, b t more amenable bl t to voltage lt scaling. li

Dynamic CMOS.15

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