HIGH-DENSITY PROGRAMMABLE LOGIC High-Speed Global Interconnect 4000 PLD Gates 48 I/O Pins, Six Dedicated Inputs 144 Registers Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Fast Random Logic Security Cell Prevents Unauthorized Copying HIGH PERFORMANCE E2CMOS TECHNOLOGY fmax = 60 MHz Maximum Operating Frequency tpd = 20 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile E2CMOS Technology 100% Tested IN-SYSTEM PROGRAMMABLE In-System Programmable (ISP) 5-Volt Only Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality Reprogram Soldered Devices for Faster Debugging COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Four Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity ispDesignEXPERT LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER PC and UNIX Platforms unctional Block
Functional Block Diagram
A0
C7 C6 C5 GLB
Output Routing Pool
A1 A2 A3 A4 A5 A6 A7 Logic Array
D Q
D Q
C4 C3 C2 C1
D Q
Global Routing Pool (GRP)
C0
B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool
CLK
0139-A-isp
Description The ispLSI 1024/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD883. This military grade device contains 144 Registers, 48 Universal I/O pins, six Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1024/883 features 5-Volt in-system programmability and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 1024/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. C7 (see figure 1). There are a total of 24 GLBs in the ispLSI 1024/883 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
Diagram
Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
The device also has 48 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. The I/O cells within the Megablock also share a common Output Enable (OE) signal. The ispLSI 1024/883 device contains three of these Megablocks.
The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1024/883 device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B4 on the ispLSI 1024/883 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.
Specifications ispLSI 1024/883
Absolute Maximum Ratings 1 Supply Voltage Vcc ...................................-0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C 1. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Military/883 TC = -55C to +125C MIN. 4.5 0 2.0 MAX. 5.5 0.8 Vcc + 1 V V 0005A mil.eps
UNITS
VCC VIL VIH
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance I/O and Clock Capacitance MAXIMUM1 10 10 UNITS pf pf TEST CONDITIONS VCC=5.0V, VIN=2.0V VCC=5.0V, VI/O, VY=2.0V Table 2- 0006mil
C1 C2
1. Characterized but not 100% tested.
Data Retention Specifications
PARAMETER Data Retention Erase/Reprogram Cycles MINIMUM 20 10000 MAXIMUM UNITS Years Cycles Table 2- 0008B
Specifications ispLSI 1024/883
Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% to 90% 1.5V 1.5V See figure 2
Figure 2. Test Load
+ 5V R1 Device Output R2 CL* Test Point
3-state levels are measured 0.5V from steady-state active level.
Table 2- 0003
Output Load Conditions (see figure 2)
Test Condition A B Active High Active Low C Active High to Z at VOH - 0.5V Active Low to Z at VOL + 0.5V Table 2- 0004A
R1 470
R2 390 390 390 390 390
CL 35pF 35pF 35pF 5pF 5pF
*CL includes Test Fixture and Probe Capacitance.
470
470
DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current isp Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL =8 mA IOH =-4 mA 0V VIN VIL (MAX.) 3.5V VIN VCC 0V VIN VIL (MAX.) 0V VIN VIL VCC = 5V, VOUT = 0.5V VIL = 0.5V, VIH = 3.0V fTOGGLE = 1 MHz 1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using six 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25oC. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC. 0007A-24 mil CONDITION MIN. 2.4 TYP. 3 135 MAX. 0.4 -10 10 -150 -150 -200 215 UNITS V V A A A A mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1
ICC2,4
Specifications ispLSI 1024/883
External Timing Parameters Over Recommended Operating Conditions 5 2 PARAMETER TEST #
COND.
DESCRIPTION1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback 3 Clock Frequency with External Feedback (tsu2 1 ) + tco1 Clock Frequency, Max Toggle 4 GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock 60 38 83 9 0 13 0 13 6 6
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Ext. Sync. Clock Pulse Duration, High 17 Ext. Sync. Clock Pulse Duration, Low 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
2.5 8.5
Table 2-0030-24 mil
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-Bit loadable counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions Section.
I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock I/O Register Hold Time after Clock I/O Register Clock to Out Delay I/O Register Reset to Out Delay Dedicated Input Delay
4 Product Term Bypass Path Delay 1 Product Term/XOR Path Delay 20 Product Term/XOR Path Delay XOR Adjacent Path Delay3 GLB Register Bypass Delay GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Output Enable to I/O Cell Delay GLB Product Term Clock Delay
1.3 6.0 4.6
8.6 9.3 10.6 12.7 1.3 2.7 3.3 13.3 12.0 9.9
ns ns ns ns ns ns ns ns ns ns ns ns
45 46
ORP Delay ORP Bypass Delay
3.3 0.7
ns ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Lattice Hard Macros.
Specifications ispLSI 1024/883
Internal Timing Parameters1 2
PARAMETER
DESCRIPTION
-60 MIN. MAX.
UNITS
Outputs tob toen todis Clocks tgy0 tgy1/2 tgcp tioy2/3 tiocp
47 48 49
Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled
4.0 6.7 6.7
ns ns ns
50 51 52 53 54
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y2 to Global GLB Clock Line Clock Delay, Clock GLB to Global GLB Clock Line Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line
6.0 4.6 1.3 4.6 1.3
6.0 7.3 6.6 7.3 6.6
ns ns ns ns ns
Global Reset tgr 55
Global Reset to GLB and I/O Registers
12.0
ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
Specifications ispLSI 1024/883
ispLSI Timing Model I/O Cell GRP Feedback Ded. In GLB ORP I/O Cell
Power Consumption Power consumption in the ispLSI 1024/883 device depends on two primary factors: the speed at which the device is operating, and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax 200 ispLSI 1024
used. Figure 3 shows the relationship between power and operating speed.
150
ICC (mA)
100
50
10
20
30
40
50
60
70
80
fmax (MHz) Notes: Configuration of Six 16-bit Counters Typical Current at 5V, 25C
ICC can be estimated for the ispLSI 1024 using the following equation: ICC = 42 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.008) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127A-24-80-isp
DESCRIPTION Input/Output Pins - These are the general purpose I/O pins used by the logic array.
Input - These pins are dedicated input pins to the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 is also used as one of the two control pins for the isp state machine. It is a dedicated input pin when ispEN is logic high. Input - This pin performs two functions. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. It is a dedicated input pin when ispEN is logic high. Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. It is a dedicated input pin when ispEN is logic high. Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated input pin when ispEN is logic high. No Connect
21
MODE/IN 31 SDO/IN 11 SCLK/IN 21 NC2
55
34
49
RESET Y0 Y1
20 16 54
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. 18, 35, 52 Ground (GND)
Y2
51
Y3
50
GND
1,
VCC
17,
36,
53,
68
VCC Table 2 - 0002C-24 mil
1. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, Vcc or GND.
Part Number Description ispLSI 1024 XX Device Family ispLSI Device Number Speed 60 = 60 MHz fmax Package H = JLCC
X Grade /883 = 883 Military Process
Power L = Low 00212-80B-isp1024 mil
Ordering Information MILITARY/883 Family ispLSI
fmax (MHz) 60
tpd (ns) 20
Ordering Number ispLSI 1024-60LH/883
SMD # 5962-9476101MXC
Package 68-Pin JLCC
Table 2-0041A-24-mil
Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended.
12
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