Sembt4 Arch Cpu
Sembt4 Arch Cpu
Sembt4 Arch Cpu
Embedded Systems
4 - Hardware Architecture
Power Management
RMR2012
RMR2012
ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language).
Memory holds data & instructions. Central processing unit (CPU) fetches instructions from memory.
Separate CPU and memory distinguishes programmable computer.
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CPU + memory
address
memory
200
2008 Wayne Wolf
data
200 PC
CPU
ADD r5,r1,r3
ADD r5,r1,r3
IR
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Harvard architecture
PC
CPU
data
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Harvard cant use self-modifying code. Harvard allows two simultaneous memory fetches. Most DSPs use Harvard architecture for streaming data:
greater memory bandwidth;
2008 Wayne Wolf
Maths is not everything
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Fixed vs. variable length. Addressing modes. Number of operands. Types of operands.
2008 Wayne Wolf
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Multiple implementations
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Assembly language
Basic features:
One instruction per line. Labels provide names for addresses (usually in rst column). Instructions often start in later columns. Columns run to end of line.
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header LDR r1,[r4] SUB r0,r0,r1 MOV sp,#INIT_SP ADR lr, start+1 BX lr CODE16 ; 3 addresses instruction ; set-up stack pointer ; Processor starts in ARM state, ; so small ARM code header used ; to call Thumb main program. ; Subsequent instructions are Thumb.
start
;********************************************************************** ;* This an example of 16 bits code (Thumb mode) ;********************************************************************** BL forever BL MOV BL chksw0 BL AND BEQ irq_init seg_rot r0,#0xf leds_on sw_rd r0,r0 chksw0 ; init. interrupts ; check display of hex digits ; sw on the leds ; read DIP_SW port, r0 carries word ; check if any DIP_SW has been mod. ; if not, keep checking
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; ; ; ; ; ;
move source to destination assign a hexadecimal value 0x05 to Register R5 move source to destination assign a hexadecimal value 0x03 to Register R6 compare source to destination R5-R6 = 5-3 = 2 greater than 0, so R5 > R6
JNE! somewhere! ! !
; jump if not equal ; The program will jump to somewhere because R5 " R6
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ARM versions
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mobile phones
! TDMI
! T: Thumb, 16-bit instruction set ! D: on-chip Debug support, enabling the processor to halt in
! M: enhanced Multiplier, yield a full 64-bit result, high performance ! I: EmbeddedICE hardware
Maths is not everything
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r0 r1 r2 r3 r4 r5 r6 r7
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r14
r15 (PC)
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Endianness
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Word is 32 bits long. Word can be divided into four 8-bit bytes. ARM addresses can be 32 bits long. Address refers to byte.
Maths is not everything
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ARM states
When the processor is executing in ARM state:
All instructions are 32 bits wide All instructions must be word aligned
All instructions are 8 bits wide Processor performs a word access to read 4 instructions at once
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Processor Core
The engine that fetches instructions and execute them E.g.: ARM7TDMI, ARM9TDMI, ARM9E-S
CPU Core
Consists of the ARM processor core and some tightly coupled function blocks Cache and memory management blocks E.g.: ARM710T, ARM720T, ARM74T, ARM920T, ARM922T, ARM940T, ARM946E-S, and ARM966E-S
ARM710T
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Examples:
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Basic format:
ADD r0,r1,r2 Computes r1+r2, stores in r0.
Immediate operand:
ADD r0,r1,#2 Computes r1+2, stores in r0.
Maths is not everything
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add
(w.
AND, ORR, EOR BIC : bit clear LSL, LSR : logical shift left/right ASL, ASR : arithmetic shift left/right ROR : rotate right RRX : rotate right extended with C
SUB, SBC : subtract (w. carry) RSB, RSC : reverse subtract (w. carry) MUL, MLA : multiply (and accumulate)
Maths is not everything
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Logical shift:
lls with zeroes.
Arithmetic shift:
lls with ones.
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RRX performs 33-bit rotate, including C bit from CPSR above sign bit.
CMP : compare CMN : negated compare TST : bit-wise test TEQ : bit-wise negated test
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LDR, LDRH, LDRB : load (half-word, byte) STR, STRH, STRB : store (half-word, byte) Addressing modes:
register indirect : LDR r0,[r1]
Maths is not everything
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Cannot refer to an address directly in an instruction. Generate value by performing arithmetic on PC.
2008 Wayne Wolf
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Example: C assignments
x = (a + b) - c;
Assembler:
! ADR r4,a! ! ; get address for a ! LDR r0,[r4]! ; get value of a ! ADR r4,b! ! ; get address for b, reusing r4 ! LDR r1,[r4]! ; get value of b ! ADD r3,r0,r1! ; compute a+b ! ADR r4,c! ! ; get address for c ! LDR r2[r4]! ; get value of c SUB r3,r3,r2! ; complete computation of x
Maths is not everything
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Example: C assignment
y = a*(b+c);
Assembler:
! ADR r4,b ; get address for b ! LDR r0,[r4] ; get value of b ! ADR r4,c ; get address for c ! LDR r1,[r4] ; get value of c ! ADD r2,r0,r1 ; compute partial result ! ADR r4,a ; get address for a ! LDR r0,[r4] ; get value of a ! MUL r2,r2,r0 ; compute final value for y
2008 Wayne Wolf
Maths is not everything
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Example: C assignment
z = (a << 2) |
(b & 15);
Assembler:
! ADR r4,a ; get address for a ! LDR r0,[r4] ; get value of a ! MOV r0,r0,LSL 2 ; perform shift ! ADR r4,b ; get address for b ! LDR r1,[r4] ; get value of b ! AND r1,r1,#15 ; perform AND ! ORR r1,r0,r1 ; perform OR
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! ADR r4,z ; get address for z ! STR r1,[r4] ; store value for z
Base-plus-offset addressing:
LDR r0,[r1,#16] Loads from location r1+16
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ARM ow of control
Branch operation:
B #100
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Example: if statement
if (a < b) { x = 5; y = c + d; } else x = c - d;
Assembler:
; compute and test condition ! ADR r4,a ; get address for a ! LDR r0,[r4] ; get value of a ! ADR r4,b ; get address for b ! LDR r1,[r4] ; get value for b ! CMP r0,r1 ; compare a < b ! BGE fblock ; if a >= b, branch to false block
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If statement, contd.
; true block ! MOV r0,#5 ; generate value for x ! ADR r4,x ; get address for x ! STR r0,[r4] ; store x ! ADR r4,c ; get address for c ! LDR r0,[r4] ; get value of c ! ADR r4,d ; get address for d ! LDR r1,[r4] ; get value of d ! ADD r0,r0,r1 ; compute y
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! ADR r4,y ; get address for y ! STR r0,[r4] ; store y ! B after ; branch around false block
If statement, contd.
; false block fblock ADR r4,c ; get address for c ! LDR r0,[r4] ; get value of c ! ADR r4,d ; get address for d ! LDR r1,[r4] ; get value for d ! SUB r0,r0,r1 ; compute a-b ! ADR r4,x ; get address for x
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; false block ! ADRGE r4,c ; get address for c ! LDRGE r0,[r4] ; get value of c ! ADRGE r4,d ; get address for d ! LDRGE r1,[r4] ; get value for d ! SUBGE r0,r0,r1 ; compute a-b ! ADRGE r4,x ; get address for x
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! ! SUB r13,#4 ; pop f2s arg off stack ! ! LDR r15,[r13]#-4 ; restore register and return
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Memory architecture
16 16-bit registers 16-bit Arithmetic Logic Unit (ALU).
Maths is not everything
16-bit address bus (64K address space) 16-bit data bus (8-bit addressability) 8/16-bit peripherals
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MSP430 Registers
R0 (PC) Program Counter
This register always points to the next instruction to be fetched Each instruction occupies an even number of bytes. Therefore, the least signicant bit (LSB) of the PC register is always zero. After fetch of an instruction, the PC register is incremented by 2, 4, or 6 to point to the next instruction.
The stack grows down thru RAM and thus SP must be initialized with a valid RAM address SP always points to an even address, so its LSB is always zero
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MSP430 Registers
R2 (SR/CG1) Status Register
The status of the MSP430 CPU is contained in register R2 Only accessible through register addressing mode - all other addressing modes are reserved to support the constants generator
V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C Overflow bit Turns off the SMCLK. Turns off the DCO dc generator. Oscillator off Turns off the CPU. General interrupt enable Negative bit Zero bit Carry bit
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MSP430 ALU
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MSP430X CPU
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MSP430X Registers
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MSP430 Instructions
There are three formats used to encode instructions for processing by the CPU core
Double operand Single operand Jumps
The instructions for double and single operands, depend on the suffix used, (.w) word or (.b) byte These suffixes allow word or byte data access If the suffix is ignored, the instruction processes word data by default
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MSP430 Instructions
Memory
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1
PC
Instruction Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
0
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
Op-code
4 to 16 Decoder
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0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Op-code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Instruction Undefined RCC, SWPB, RRA, SXT, PUSH, CALL, RETI JNE, JEQ, JNC, JC JN, JGE, JL, JMP MOV ADD ADDC SUBC SUB CMP DADD BIT BIC BIS XOR AND
Double Operand
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MSP430X Instructions
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14 Op-code
13
12
11
10
Condition
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Operation
src+dst!dst src+dst+C!dst src+dst+C!dst (dec) dst+.not.src+1!dst dst+.not.src+C!dst src.and.dst!dst .not.src.and.dst!dst src.or.dst!dst src.and.dst src.xor.dst!dst dst-src src!dst
Description
Add source to destination Add source and carry to destination Decimal add source and carry to destination Subtract source from destination Subtract source and not carry from destination AND source with destination Clear bits in destination Set bits in destination Test bits in destination XOR source with destination Compare source to destination Move source to destination
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0100
0101
00
0100
The instruction instructs the CPU to copy the 16-bit 2s complement number in register r5 to register r4
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PUSH(.B or .W) src SP-2!SP, src!@SP Program flow control instructions CALL(.B or .W) dst SP-2!SP, PC+2!@SP dst!PC RETI
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@SP+!SR, @SP+!SP
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Logically shift the contents of register r5 to the right through the status register carry
Assembly:!rrc.w r5 Instruction code:! 0x1005
Op-code rrc b/w 16-bits Ad Register D-reg r5
000100000
00
0101
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The CPU shifts the 16-bit register r5 one bit to the right (divide by 2) the carry bit prior to the instruction becomes the MSB of the result while the LSB shifted out replaces the carry bit in the status register
Jump instructions are used to direct program flow to another part of the program. The condition on which a jump occurs depends on the Condition field consisting of 3 bits:
000: jump if not equal 001: jump if equal 010: jump if carry ag equal to zero 011: jump if carry ag equal to one 100: jump if negative (N = 1) 101: jump if greater than or equal (N = V) 110: jump if lower (N ! V) 111: unconditional jump
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Thus, the range of the jump is -511 to +512 words, (-1023 to 1024 bytes ) from the current instruction Note: Use a BR instruction to jump to any address
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001
011
1111100100
The CPU will add to the incremented PC (R0) the value -28 x 2 if the carry is set
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In combination with registers R0-R3, three additional source addressing modes are available:
Maths is not everything
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In combination with registers R0/R2, two additional destination addressing modes are available:
label - PC Relative, x(PC)
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00 = Register Mode
add.w r4,r10
Memory PC PC
0x540a
;r10 = r4 + r10
CPU
Registers
PC R4
ADDER
ss ddre
Bus
Data Bus (1
cycle)
0x540a IR
R10
ALU
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01 = Indexed Mode
ss ddre
Bus
CPU
0x541a IR
Registers
PC R4
Address
Bus
ADDER
R10
Data Bus
(+1 cycle
ALU
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add.w @r4,r10
Memory PC PC
0x542a
ss ddre
Bus
Data Bus (1
cycle)
Registers
PC R4
Addre
s Bus
ADDER
Data Bus
R10
(+1 cycle
ALU
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add.w @r4+,r10
Memory PC PC
0x543a
ss ddre
Bus
Data Bus (1
res s
cycle)
Registers
PC
s Bu
d Ad
0002
R4
ADDER
R10
Data Bus
(+1 cycle
ALU
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add.w cte,r10
Memory PC PC PC
0x501a 0x000c
ss ddre
Bus
Registers
PC
Address
Bus
ADDER
R10
Data Bus
(+1 cycle
ALU
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add.w &cte,r10
Memory PC PC PC
0x521a 0xc018
ss ddre
Bus
Data Bus (1
cycle)
0x521a IR
Registers
PC
0000
ADDER
Bus
Data Bus
R10
(+1 cycle
ALU
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add.w #100,r10
Memory PC PC PC
0x503a 0x0064
ss ddre
Bus
Data Bus (1
cycle)
0x503a IR
Dat
aB
us (+
1c
ycl e)
ADDER
R10
ALU
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Constant Generator
add.w #1,r10
Memory PC PC
0x531a
;r10 = #1 + r10
CPU
0x531a IR
ss ddre
Bus
Data Bus (1
cycle)
Registers
0000 0001 0002 0004 0008 ffff
PC
ADDER
R10
ALU
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add.w cte,var
Memory
PC PC PC
0x501a 0x000c 0x0218
ss ddre
Bus
Data Bus (1
Registers
PC
PC
Data Bus
(+1 cycle
ALU
Data
Bus
(+1
cycl e)
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Source
Destination
Example
mov r10,r11 mov 2(r5),6(r6) mov EDE,TONI mov &MEM,&TCDAT mov @r10,r11 mov @r10+,tab(r6) mov #45,TONI mov #2,&MEM
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Operation
r10 ! r11 M(2+r5) ! M(6+r6) M(EDE) ! M(TONI) M(MEM) ! M(TCDAT) M(r10) ! r11 M(r10) ! M(tab+r6) , r10+2 ! r10 #45 ! M(TONI) #2 ! M(MEM) #1 ! r11 #45 ! r11
C C
1 3 3 3 1 2 3 2 1 2
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Instruction timing:
1 cycle to fetch instruction word +1 cycle if source is @Rn, @Rn+, or #Imm +2 cycles if source uses indexed mode
1st to fetch base address 2nd to fetch source Includes absolute and symbolic modes
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+2 cycles if destination uses indexed mode +1 cycle if writing destination back to memory +1 cycle if writing to PC (R0) Jump instructions are always 2 cycles
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Example add R5,R8 add @R5,R6 mov @R5+,R0 add R5,4(R6) add R8,EDE add R5,&EDE add #100,TAB(R8)
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Cycles Length 1 2 3 4 4 4 5 6 4 1 1 1 2 2 2 3 3 2
&TONI &EDE
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MSP30 Controller
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