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Xilinx 7 Series FPGA's and Vivado Tool Flow: Workshop On

This document provides information about a workshop on Xilinx 7 Series FPGAs and the Vivado tool flow. The workshop will be held on January 22nd, 2014 at the Indian Institute of Science in Bangalore. On completion, participants will understand the 7 series FPGA architecture, Vivado design flow, and high-level synthesis using Vivado HLS. They will learn how to develop embedded systems for the Zynq ARM processor and complete simple hardware and embedded system designs in Vivado and Vivado HLS. The workshop is free for participants but has limited seating; registration is required by January 20th.

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106 views2 pages

Xilinx 7 Series FPGA's and Vivado Tool Flow: Workshop On

This document provides information about a workshop on Xilinx 7 Series FPGAs and the Vivado tool flow. The workshop will be held on January 22nd, 2014 at the Indian Institute of Science in Bangalore. On completion, participants will understand the 7 series FPGA architecture, Vivado design flow, and high-level synthesis using Vivado HLS. They will learn how to develop embedded systems for the Zynq ARM processor and complete simple hardware and embedded system designs in Vivado and Vivado HLS. The workshop is free for participants but has limited seating; registration is required by January 20th.

Uploaded by

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We take content rights seriously. If you suspect this is your content, claim it here.
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Workshop on

completion, participants will be able to: On completion

Xilinx 7 Series FPGAs and Vivado Tool flow


22nd January, 2014 Name: Dr/Mr/Ms ________________________

Department of Electrical Engineering, Engineering Indian Institute of Science, Bangalore

Describe the key features of Xilinx 7 series FPGAs Understand the Vivado design flow Develop an embedded system using Zynq Address the algorithm to FPGA implementation flow using Vivado HLS Understand high-level synthesis flow of Vivado HLS The department offers a vibrant environment for postgraduate education and research in Electrical Engineering. Established in 1911, it is one of the first few departments at IISc. The vision of the department is to provide the leadership to enable India's excellence in the field of Electrical Elect Engineering. The department is committed to advancement of the frontiers of knowledge in Electrical Engineering and to provide the students with a stimulating and rewarding learning experience. The department is currently engaged in research in many areas of Electrical Engineering including Power Systems, Energy Studies, Power Electronics, Electrical Drives, High Voltage engineering, Signal Processing, Image Processing and Multimedia, Biomedical Imaging etc. The department admits students for 2-year 2 ME programs as well as research programs leading to Ph.D. and M. Sc. (Engg) degrees. The department is recognized as a Center for Advanced Studies in Electrical Engineering by University Grants Commission.

_________________________________

Designation: __________________________

Organization: _________________________ Address: _____________________________ _____________________________ _____________________________ Pin code: ________ Phone: _____________ Mobile: ______________________________ E-Mail: ______________________________

Course Highlights: The training program delivers the following key concepts to the participants: Architecture and features of 7 series FPGAs from Xilinx Xilinx Vivado Tool flow and its comprehensive features overview Zynq All Programmable SoC Architecture Embedded Design flow using Zynq Vivado High Level Synthesis flow

Signature of the Candidate

Important Dates Last date for registration: 20th Jan 2014 Program Date: 22nd Jan 2014

Venue:

Department of Electrical Engineering, Indian Institute of Science, C V Raman Road, Bangalore, Karnataka -560012

CoreEL Technologies is a Customer Application Specific Product & Solutions (CASPS) company offering innovative solutions from its diverse portfolio of offerings that include Intellectual Property (IP) cores, System Design, Prototype Development, Manufacturing, Sustenance, Next-gen products, Semiconductor solutions, EDA tools, COTS products and Technology Training.

Rapidly architect an embedded system targeting the ARM processor of Zynq located on ZedBoard using Vivado and IP Integrator

Pre Pre-requisites: Concepts of digital design Familiarity with HDL (VHDL or Verilog) Digital logic and FPGA design experience Basic experience with Xilinx Vivado design software suite Basic understanding of C programming Basic microprocessor experience

Resource Persons: Persons Dr. Parimal Patel, Xilinx University Program Mrs. Sadiya Arshad, National Manager, CoreEL Technologies Mr. Mayur Deshmukh, Deshmukh Applications Engineer, CoreEL Technologies, Target arget participants: participants Faculty members PG students tudents and Participants from industry

CoreEL University Program (CUP) is the sole authorized partner of Xilinx University Program (XUP) & enables the

academic institutions across India to drive excellence in imparting education on VLSI and Embedded System technologies. CUP strives to drive excellence in teaching-learning experience through setting up world class laboratory infrastructure and enabling the teaching staff and students on the latest tools, technologies and methodologies.
Agenda

Organizing Committee Convener: Sastry P S, Chairman, Electrical Engineering Department, Indian Institute of Science

Topics:

7-Series Architecture Overview Vivado Design Flow Lab 1: Vivado Design Flow

Use Vivado IDE to create a simple HDL design. Simulate the design using the XSIM HDL simulator available in Vivado design suite. Generate the bit stream and verify in hardware

Cost: This workshop is extended to the participants free of cost. Limited seats only; registrations are mandatory. Address of Correspondence: Dr. Rathna

This course provides participants an overview of Xilinx 7 series FPGA architecture, Vivado tool flow with emphasis on embedded design flow using Zynq, and Vivado High Level Synthesis concepts.
Objectives

Introduction to Embedded System Design using Zynq Lab 2: Simple Hardware Design Create a Vivado project and use IP Integrator to develop a basic embedded system for a target board. Introduction to High-Level Synthesis using Vivado HLS Lab 3: Creating Project and Understanding Reports Experience a basic design flow of Vivado HLS and review generated output.

Professor Electrical Engineering Department, Indian Institute of Science Bangalore - 560 012 Karnataka, India
Point of Contact: Email:

After the completion of this training program the participants will be able to:
Describe the architecture and features of 7 series FPGAs from Xilinx Understand the Vivado design flow Understand high-level synthesis flow of Vivado HLS

[email protected] [email protected] [email protected] [email protected] [email protected]

Phone No: +919945031122

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