UNIVERSITY OF WATERLOO

Department of Electrical and Computer Engineering

ECE 324
VHDL Tutorial Notes

Wayne M. Loucks, PEng [email protected]

Robert B. Gorbet, PEng [email protected]

Carol C.W. Hulls, PEng [email protected]

Bill Bishop [email protected]

June 2002

Copyright (c) 2002 by the University of Waterloo. All Rights Reserved.

 UNIVERSITY OF WATERLOO
Department of Electrical and Computer Engineering

Section I:
VHDL Tutorial

June 2002
 VHDL Tutorial

Tutorial Outline

• Introduction to VHDL

• VHDL Designs

• Signals

• Assignment Statements

• Process Statements

• Examples

• VHDL and Quartus II

Introduction to VHDL I-1

 VHDL Tutorial

VHDL

• V - VHSIC (Very High Speed Integrated Circuit)

H - Hardware
D - Description
L - Language

• Language to describe the structure and/or behaviour of digital

hardware designs

• VHDL designs can be simulated and/or synthesized

• Two versions of VHDL have been standardized by the IEEE

– VHDL87 ⇒ IEEE-1076-1987
– VHDL93 ⇒ IEEE-1076-1993

Introduction to VHDL I-2

 VHDL Tutorial

VHDL Documentation

• Books
– Michael John Sebastian Smith, Application Specific Integrated Cir-
cuits, Addison-Wesley, Reading Mass., 1998.
– Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic
with VHDL Design, McGraw-Hill, New York, NY, 2000.
– Douglas Perry, VHDL, 3rd Edition, McGraw Hill, New York, NY,
1998.
– Peter J. Ashenden, The Designer’s Guide to VHDL, Morgan Kauf-
mann Publishers, Inc., San Francisco, CA, 1996.
– Sudhakar Yalamanachili, VHDL Starter’s Guide, Prentice-Hall, Up-
per Saddle River, NJ, 1998.
– David Pellerin and Douglas Taylor, VHDL Made Easy, Prentice-Hall,
Upper Saddle River, NJ, 1997.
– K.C. Chang, Digital Design and Modelling with VHDL and Synthesis
IEEE Computer Society, Los Alamitos, CA, 1997.

• Websites ⇒ A list of web resources can be found on the course website

Introduction to VHDL I-3

 VHDL Tutorial

Entities, Architectures, and Configurations

• VHDL is a strongly-typed language for describing a digital hardware de-

sign. The structure of a VHDL design resembles the structure of a modern,
object-oriented software design in the sense that every VHDL design de-
scribes both an external interface and an internal implementation.
A VHDL design consists of the following specifications:
Entity :
A specification of the external interface to the design. The specifi-
cation of the external interface to the design is unique.
Architecture :
A specification of the internal implementation of the design. There
can be several specifications of the internal implementation of the
design.
Configuration :
A specification of the mapping between an architecture and a par-
ticular instance of an entity. There must be a configuration for
each instance of an entity. The configuration defaults to the last
compiled architecture if one has not been explicitly specified.

VHDL Designs I-4

 VHDL Tutorial

Architecture and Entity Introduction

Some description of Conceptual view of problem

a module's operation

E1: Module 1 (Entity for Module 1)

separate the Define the ports of
A
implementation from unit to be designed
its interface C
(its interface, specified
B
in the system as an entity)

A1: Module 1 Architecture 2 A3: Module 1 Architecture 3

Provide another design Provide another design
for Module 1 for Module 1
ASIC DESIGN Speed DESIGN

A2: Module 1 Architecture 2 A4: Module 1 Architecture 4

Provide another design
Provide another design
for Module 1
for Module 1
Fault Tolerant
Area DESIGN
DESIGN

entityintro 1.

VHDL Designs I-5

 VHDL Tutorial

Architecture and Entity Hierarchy

E3: Module 3 (entity for Module 3)

X
Y D
Z

A1: Module 3 Architecture 1

Interconnect various Designer of A1
modules Need not know
X M1 internal detail of
Y M2 D
E2 or E3.
Z M1

E1: Module 1 (Entity for Module 1) E2: Module 2 (Entity for Module 2)
separate the separate the
A A
implementation from implementation from
C its interface C
its interface B
B in the system
in the system

entityintro 2.

VHDL Designs I-6

 VHDL Tutorial

Small Example

andnand.vhd

-- A VHDL file to implement a And-Nand

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY andNand IS
PORT(
a, b : IN STD_LOGIC;
q, qBar : OUT STD_LOGIC
);
END andNand;

ARCHITECTURE gateVersion OF andNand IS

SIGNAL a_and_b : STD_LOGIC;

BEGIN
a_and_b <= a AND b;
q <= a_and_b;
qBar <= NOT a_and_b;
END gateVersion;

NOTE
andnand.

VHDL Designs I-7

 VHDL Tutorial

Language Elements

Comments :

-- All comment lines start with two hyphens.

Libraries and Packages :

There are many libraries and packages available for VHDL. An important
VHDL library is the IEEE library. This library provides the std logic 1164
package. This package provides a set of user-defined datatypes and con-
version functions that should be used in VHDL designs. It can be instan-
tiated as follows:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Datatypes :
VHDL supports a set of built-in datatypes as well as user-defined datatypes.
Only a few will be introduced in this tutorial!
• Built-in datatypes will not be used this term. They work well for
simulation but not so well for synthesis.
– BIT: Boolean value of 0 or 1.
– BIT VECTOR: An array of bits.
– INTEGER: An integer value (within a range).

VHDL Designs I-8

 VHDL Tutorial

STD LOGIC 1164 Defined Datatypes

• The datatypes specified in STD LOGIC 1164 will be used exclusively this
term.

STD ULOGIC Values

Uninitialized ’U’ Forcing Unknown ’X’
Don’t care ’-’ High Impedance ’Z’
–
Forcing 1 ’1’ Forcing 0 ’0’
Weak Unknown ’W’ Weak 0 ’L’
Weak 1 ’H’

– STD ULOGIC VECTOR: An array of STD ULOGIC.

– STD LOGIC: A resolved version of STD ULOGIC. If two or more
distinct STD LOGIC are driven onto a bus in a design at one instant
in time, the bus will have a defined value (usually X).
– STD LOGIC VECTOR: An array of STD LOGIC.
– NOTE: IEEE recommends the use of STD LOGIC and
STD LOGIC VECTOR.

VHDL Designs I-9

 VHDL Tutorial

Entity Declaration

The entity declaration specifies the following:

• Name of the entity

• Set of port declarations defining the inputs and outputs to the digital
hardware design.
– Port name
∗ Consists of letters, digits, and/or underscores
∗ Must begin with a letter
∗ Case insensitive
– Port direction

IN Input port
OUT Output port
INOUT Bidirectional port
BUFFER Buffered output port
LINKAGE Deprecated in IEEE 1076-2000

– Port signal type

∗ STD LOGIC
∗ STD LOGIC VECTOR(max DOWNTO min)

VHDL Designs I - 10
 VHDL Tutorial

Signals

In VHDL, signals are used to convey information between (and within) entities.
Signals represent connection points in a VHDL design.
Sample Signal Specifications:
SIGNAL x1 : BIT;
SIGNAL c : BIT_VECTOR(1 TO 4);
SIGNAL byte : BIT_VECTOR(10 DOWNTO 0);

SIGNAL din0 : STD_LOGIC;

SIGNAL dinA : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL ece324 : STD_LOGIC;

Signals are associated with a value and a set of attributes. Attributes allow VHDL
designers to check for signal transitions, model delays, and create ”generic” de-
scriptions of entities. Attributes are often used during simulation.

Attribute Syntax Attribute Note

ece324’EVENT This attribute is true if an event just
happened on the signal ece324. This
attribute is fully supported for simu-
lation and partially supported for syn-
thesis.
ece324’DELAYED(T) Creates a signal the same as ece324
but delayed by a time T. This at-
tribute is only supported for simula-
tion

VHDL Designs I - 11
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Signal Operators

Logical Operators :

• AND
• OR
• XOR
• XNOR
• NOT
• NAND
• NOR

Relational Operators :

• Equal =
• Not Equal /=
• Less Than <
• Greater Than >

Accessing Vector Elements :

some_signal(0) <= other_signal(1);

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Assignment Statements

SIGNAL x, y, z : STD_LOGIC;
SIGNAL a, b, c : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sel : STD_LOGIC_VECTOR(2 DOWNTO 0);

-- Concurrent Signal Assignment Statements

-- NOTE: Both x and a are produced concurrently
x <= y AND z;
a <= b OR c;

-- Alternatively, signals may be assigned constants

x <= ’0’;
y <= ’1’;
z <= ’Z’;
a <= "00111010"; -- Assigns 0x3A to a
b <= X"3A"; -- Assigns 0x3A to b
c <= X"3" & X"A"; -- Assigns 0x3A to c

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Assignment Statements

SIGNAL x, y, z : STD_LOGIC;
SIGNAL a, b, c : STD_LOGIC_VECTOR( 7 downto 0);
SIGNAL sel : STD_LOGIC_VECTOR( 2 downto 0);

-- Conditional Assignment Statement

-- NOTE: This implements a tree structure of logic gates!
x <= ’0’ WHEN sel = "000" ELSE
y WHEN sel = "011" ELSE
z WHEN x = ’1’ ELSE
’1’;

-- Selected Signal Assignment Statement

-- NOTE: The selection values must be constants.
WITH sel SELECT
x <= ’0’ WHEN "000",
y WHEN "011",
z WHEN "100",
’1’ WHEN OTHERS;

-- Selected signal assignments also work with vectors.

WITH x SELECT
a <= "01010101" WHEN ’1’,
b WHEN OTHERS;

-- NOTE: Conditional assignment statements are evaluated

-- in (priority) order while selected signal assignment
-- statements are evaluated in parallel.

VHDL Designs I - 14
 VHDL Tutorial

Process Statements

This construct is not required for the labs this term. However, a process is a
fundamental concept of VHDL.
The process statement allows a VHDL designer to describe the behaviour of
a portion of an architecture. It is easy to fall into the trap of believing that
statements within a process are sequential. This is not (necessarily) the case!
The following is a quote from the Brown and Vranesic text...

The tendency for the novice is to write code that resembles a

computer program, containing many variables and loops. It is
difficult to determine what logic circuit the CAD tools will produce
when synthesizing such code. ... A good general guideline is to
assume that if the designer cannot readily determine what logic
circuit is described by the VHDL code, then the CAD tools are
not likely to synthesize the circuit that the designer is trying to
describe.

VHDL Designs I - 15
 VHDL Tutorial

Process Specific Statements

Variables :
Variables can be declared within a process. Variables can be used like sig-
nals. However, variables and signals have a subtle difference with respect
to the assignment of a value.
VARIABLE variable_name : variable_type;

IF Statements :

IF condition1 THEN
statements1;
ELSIF condition2 THEN
statements2;
ELSE
statements3;
END IF;

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Process Specific Statements (cont.)

Case Statements :

CASE variable_name IS
WHEN value1 =>
statement1;
WHEN value2 =>
statement2;
WHEN OTHERS =>
statement4;
END CASE;

Loop Statements :

Assert Statements :

Wait Statements :
Wait statements halt the execution of a process until a desired event or
delay has happened. Wait statements can be used to build sequential
designs.

VHDL Designs I - 17
 VHDL Tutorial

Process Statement in a Combinational Problem

SIGNAL a, b, c : STD_LOGIC;
SIGNAL Sel, x, y, z : STD_LOGIC;
SIGNAL DV : STD_LOGIC_VECTOR(17 DOWNTO 0);
-- Assume that a, b, c and Sel are set on elsewhere

PROCESS (a, b, c)
-- a, b, and c are in the sensitivity list.
-- In this case (combinational) they are
-- inputs.

BEGIN
-- Signal assignment statements can go anywhere
-- inside a process.
x <= a;

-- If statements
IF a = ’0’ THEN
x <= c AND b;
y <= c OR b;
ELSIF b = ’0’ THEN
z <= c OR a;
ELSE
w <= ’0’;
END IF; -- Note x, y, and z are
-- not always assigned
-- in this example

-- Continued on next slide

VHDL Designs I - 18
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Process Statement in a Combinational Problem (cont.)

-- Continued from previous example

-- Case statement

CASE Sel IS
WHEN ’0’ =>
z <= a AND b;
WHEN OTHERS
z <= a OR b;

-- For Loops

FOR i IN 1 to 4 LOOP
DV(i) <= a XOR b;
END LOOP;

-- While Loops

WHILE boolean_expression LOOP

statement;
-- More statements could be added here.
END LOOP;

END PROCESS;

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Process Statement in Sequential Circuits

-- Assume we have defined ports and signals such that:

-- d is the flip-flop input pin
-- reset is the flip-flop reset pin
-- clock is the flip-flop clock pin
-- q is the flip-flop output pin

ff1: PROCESS
(
clock,
reset
)
BEGIN
IF (reset = ’1’) THEN
q <= ’0’;
ELSIF (clock = ’1’) AND (clock’EVENT) THEN
q <= d;
END IF;
END PROCESS ff1;

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Example

Consider the following problem using vector outputs

Logical Problem
(ECE 223, ME 262)
Entity
DataIn(vector)

Segments(6)
Segments

Segments(1)

Segments(4) Segments(5)
DPin
Segments(0)
Segments(2)

Segments(3)
DP
Segments(7)

sevenseg

VHDL Designs I - 21
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Vector Seven Segment Entity

Assumption:

• The mapping from Segments(1) to pins on the FPGA must be done by

the user.
-- Seven Segment Display Example
-- Individual Assignments
-- Decimal Point is ignored for sake of brevity

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY seven_seg IS

PORT
(
dataIn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
decimalIn: IN STD_LOGIC;
segments : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);

END seven_seg;

ARCHITECTURE theLongWay OF seven_seg IS

BEGIN
-- seven segment display is active low
-- segments defined same as with showhex
-- 6
-- 1 5
-- 0

VHDL Designs I - 22
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-- 2 4
-- 3
-- 7 is decimal point, always off

WITH dataIn SELECT

segments(0) <= ’1’ WHEN "0000",
’1’ WHEN "0001",
’1’ WHEN "0111",
’0’ WHEN OTHERS;
WITH dataIn SELECT
segments(1) <= ’1’ WHEN "0001",
’1’ WHEN "0010",
’1’ WHEN "0011",
’1’ WHEN "0111",
’1’ WHEN "1001",
’0’ WHEN OTHERS;
WITH dataIn SELECT
segments(2) <= ’1’ WHEN "0001",
’1’ WHEN "0011",
’1’ WHEN "0100",
’1’ WHEN "0101",
’1’ WHEN "0111",
’1’ WHEN "1001",
’0’ WHEN OTHERS;
WITH dataIn SELECT
segments(3) <= ’1’ WHEN "0001",
’1’ WHEN "0100",
’1’ WHEN "0111",
’0’ WHEN OTHERS;
WITH dataIn SELECT
segments(4) <= ’1’ WHEN "0010",
’0’ WHEN OTHERS;

VHDL Designs I - 22
 VHDL Tutorial

WITH dataIn SELECT

segments(5) <= ’1’ WHEN "0101",
’0’ WHEN OTHERS;
WITH dataIn SELECT
segments(6) <= ’1’ WHEN "0001",
’1’ WHEN "0100",
’0’ WHEN OTHERS;
-- segments(7) <= DecimalIn;

END theLongWay;

ARCHITECTURE theBetterWay OF seven_seg IS

BEGIN
-- seven segment display is active low
-- segments defined same as with showhex
-- 6
-- 1 5
-- 0
-- 2 4
-- 3
-- 7 is decimal point, always off
WITH dataIn SELECT
segments <= "10000001" WHEN "0000",
"11001111" WHEN "0001",
"10010010" WHEN "0010",
"10000110" WHEN "0011",
"11001100" WHEN "0100",
"10100100" WHEN "0101",
"10100000" WHEN "0110",
"10001111" WHEN "0111",

VHDL Designs I - 22
 VHDL Tutorial

"10000000" WHEN "1000",

"10000100" WHEN "1001",
"11111111" WHEN OTHERS;
END theBetterWay;

VHDL Designs I - 22
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VHDL and Quartus II

• Open a new vhdl file

• Use a template to give basic structure. (2 input AND gate);

• LIBRARY

• USE

• ENTITY

• ARCHITECTURE

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A First VHDL Description

• Start Quartus II and open a new VHDL file.

• Save the file as a VHDL file named and.vhd.

• Start editing the file...

--
-- A 2 input AND Gate
--
-- A nice description of my file
-- My name and date
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;

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Designing a Multiplexer

Suppose you wished to design a Quad 2-Input Multiplexer (MUX)...

select_data

data_a
data_q
data_a

• Required Inputs
– 1 control bit
– 4 pairs of 2 input lines

• Outputs
– Four output lines

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Entity Declaration for a Quad 2-Input Multiplexer

-- Quadruple 2 Input MUX

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY quad_2_input IS

PORT
(
select_data : IN STD_LOGIC;
data_a, data_b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);

END quad_2_input;

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Device Functionality

The truth table for the MUX would be:

select data q0 data q1 data q2 data q3

0 data a0 data a1 data a2 data a3
1 data b0 data b1 data b2 data b3

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Architecture Body

• The architecture body can contain a description of

– Behaviour
– Structure
– Combination of behaviour and structure

• The architecture body contains

– A name
– A description of the entity being implemented
– Statements to implement the entity

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Gate Model
-- Quadruple 2 Input MUX

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY quad_2_input IS

PORT
(
select_data : IN STD_LOGIC;
data_a, data_b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);

END quad_2_input;

ARCHITECTURE gates_only OF quad_2_input IS

BEGIN

data_q(0) <= (data_a(0) AND NOT select_data) OR (data_b(0) AND select_data);

data_q(1) <= (data_a(1) AND NOT select_data) OR (data_b(1) AND select_data);
data_q(2) <= (data_a(2) AND NOT select_data) OR (data_b(2) AND select_data);
data_q(3) <= (data_a(3) AND NOT select_data) OR (data_b(3) AND select_data);

END gates_only;

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Conditional Assignment
-- Quadruple 2 Input MUX

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY quad_2_input IS

PORT
(
select_data : IN STD_LOGIC;
data_a, data_b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);

END quad_2_input;

ARCHITECTURE conditional_assign OF quad_2_input IS

BEGIN

data_q <= data_a WHEN select_data = ’0’ ELSE

data_b;

END conditional_assign;

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Selected Assignment Statement

-- Quadruple 2 Input MUX

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY quad_2_input IS

PORT
(
select_data : IN STD_LOGIC;
data_a, data_b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);

END quad_2_input;

ARCHITECTURE using_select OF quad_2_input IS

BEGIN

WITH select_data SELECT

data_q <= data_a WHEN ’0’,
data_b WHEN OTHERS,

END using_select;

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Process and If Statements

-- Quadruple 2 Input MUX

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY quad_2_input IS

PORT
(
select_data : IN STD_LOGIC;
data_a, data_b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);

END quad_2_input;

ARCHITECTURE process_if OF quad_2_input IS

BEGIN

PROCESS (select_data, data_a, data_b)

BEGIN
IF (select_data = ’0’) THEN
data_q <= data_a;
ELSE
data_q <= data_b;
END IF;
END PROCESS;

END process_if;

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Process and Case Statements

-- Quadruple 2 Input MUX

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY quad_2_input IS

PORT
(
select_data : IN STD_LOGIC;
data_a, data_b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);

END quad_2_input;

ARCHITECTURE process_case OF quad_2_input IS

BEGIN

PROCESS (select_data, data_a, data_b)

BEGIN
CASE select_data IS
WHEN ’0’ =>
data_q <= data_a;
WHEN OTHERS =>
data_q <= data_b;
END CASE;
END PROCESS;

END process_case;

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Process and Loop Statements

-- Quadruple 2 Input MUX

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY quad_2_input IS

PORT
(
select_data : IN STD_LOGIC;
data_a, data_b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);

END quad_2_input;

ARCHITECTURE process_loop OF quad_2_input IS

BEGIN

PROCESS (select_data, data_a, data_b)

BEGIN
FOR i IN 0 to 3 LOOP
data_q(i) <= (data_a(i) AND NOT select_data)
OR (data_b(i) AND select_data);
END LOOP;
END PROCESS;

END process_loop;

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Execution of VHDL

When do the statements get executed?

• Compile your VHDL code

• Simulate your VHDL MUX using the waveform file mux.vwf

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Using Components

This slide illustrates the use of components.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY conf_seven_seg IS
PORT(
ConfDataIn : IN STD_LOGIC_VECTOR(3 downto 0);
ConfDPin : IN STD_LOGIC;
ConfSegments: OUT STD_LOGIC_VECTOR(7 downto 0));
END conf_seven_seg;
-- Architecture Body
ARCHITECTURE Long OF conf_seven_seg IS
SIGNAL DPInternal : STD_LOGIC;
SIGNAL DinInternal : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL DoutInteral : STD_LOGIC_VECTOR(7 downto 0);
COMPONENT seven_seg
PORT(
DataIn : IN STD_LOGIC_VECTOR(3 downto 0);
DecimalIn : IN STD_LOGIC;
segments : OUT STD_LOGIC_VECTOR(7 downto 0));
END COMPONENT;
BEGIN
LongSevenSeg: seven_seg
PORT MAP (DataIn => ConfDataIn,
DecimalIn => ConfDPIn,
segments => ConfSegments
);
END Long;

VHDL Designs I - 36