ML605 Hardware User Guide

UG534 (v1.7) June 19, 2012

 Copyright 20092012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DISCLAIMER The information disclosed to you hereunder (the Materials) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.

Revision History
The following table shows the revision history for this document.
Date 8/17/09 11/17/09 Version 1.0 1.1 Initial Xilinx release. Updated Figure 1-1, Figure 1-2, Figure 1-3, Figure 1-11, and Figure 1-14. Added Figure 1-7, Figure 1-8, Figure 1-10, and Figure 1-13. Updated Table 1-15 and Table 1-18. Updated Appendix C, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout and Appendix D, ML605 Master UCF. Minor typographical edits. Updated Figure 1-2, Figure 1-3, Figure 1-17, Table 1-3, Table 1-8, Table 1-9, Table B-34, and Table B-35. Miscellaneous typographical edits. Corrected typos in Table 1-31 and Figure 1-28. Updated 7. Clock Generation, including Table 1-7. Updated Package Placement column in Table 1-8. Updated Figure 1-17. Added notes about FMC HPC J64 and J63 connectors to 19. VITA 57.1 FMC HPC Connector and 20. VITA 57.1 FMC LPC Connector, respectively. Updated description of PMBus Pod and TI Fusion Digital Power Software GUI in Onboard Power Regulation. Updated Table B-35, Appendix C, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout, and Appendix D, ML605 Master UCF. Updated description of Fusion Digital Power Software in Onboard Power Regulation. Revised note in Table 1-6. Revised oscillator manufacturer information from Epson to SiTime on page page 14, page 29 and page 78. Revision

01/15/10 1/21/10 05/18/10

1.2 1.2.1 1.3

10/12/10 02/15/11

1.4 1.5

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Date 07/18/11

Version 1.6

Revision Corrected jitter to stability in section Oscillator (Differential), page 29. Added Table 1-32, page 69, and table notes in Table 1-31. Revised the FPGA U1 Pins for IIC_SDA_MAIN and IIC_SCL_MAIN in Table 1-18, page 46. Added [Ref 4] link to Oscillator (Differential), page 29. Revised Oscillator Socket (SingleEnded, 2.5V), page 29. Revised Figure 1-10, page 33.

06/19/12

1.7

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ML605 Hardware User Guide

ML605 Hardware User Guide

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UG534 (v1.7) June 19, 2012

Table of Contents
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 1: ML605 Evaluation Board

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Related Xilinx Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1. Virtex-6 XC6VLX240T-1FFG1156 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. 512 MB DDR3 Memory SODIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. 128 Mb Platform Flash XL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. 32 MB Linear BPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ML605 Flash Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. System ACE CF and CompactFlash Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. USB JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Socket (Single-Ended, 2.5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMA Connectors (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. Multi-Gigabit Transceivers (GTX MGTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9. PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10. SFP Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SGMII GTX Transceiver Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13. USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14. DVI Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16. Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet PHY Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FPGA INIT and DONE LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Pushbutton Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User SMA GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Display (16 Character x 2 Lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18. Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power On/Off Slide Switch SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 17 22 22 23 26 28 29 29 29 31 33 34 37 38 39 41 42 43 44 46 47 48 49 49 50 51 52 53 54 55 55

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FPGA_PROG_B Pushbutton SW4 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSACE_RESET_B Pushbutton SW3 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . System ACE CF CompactFlash Image Select DIP Switch S1 . . . . . . . . . . . . . . . . . . . . . . Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2 . . . . . . . . . . .

19. VITA 57.1 FMC HPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20. VITA 57.1 FMC LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Adapter and Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Onboard Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22. System Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

56 56 57 58 59 65 67 67 68 71

Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Appendix A: References Appendix B: Default Switch and Jumper Settings Appendix C: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout Appendix D: ML605 Master UCF

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Preface

About This Guide

This manual accompanies the Virtex-6 FPGA ML605 Evaluation Board and contains information about the ML605 hardware and software tools.

Guide Contents
This manual contains the following chapters: Chapter 1, ML605 Evaluation Board, provides an overview of the embedded development board and details the components and features of the ML605 board. Appendix B, Default Switch and Jumper Settings. Appendix C, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout. Appendix D, ML605 Master UCF. Appendix A, References.

Additional Documentation
The following documents are also available for download at http://www.xilinx.com/support/documentation/virtex-6.htm. Virtex-6 Family Overview The features and product selection of the Virtex-6 family are outlined in this overview. Virtex-6 FPGA Data Sheet: DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex-6 family. Virtex-6 FPGA Packaging and Pinout Specifications This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications. Virtex-6 FPGA Configuration Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG configuration, reconfiguration techniques, and readback through the SelectMAP and JTAG interfaces. Virtex-6 FPGA Clocking Resources User Guide This guide describes the clocking resources available in all Virtex-6 devices, including the MMCM and PLLs.

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Virtex-6 FPGA Memory Resources User Guide The functionality of the block RAM and FIFO are described in this user guide. Virtex-6 FPGA SelectIO Resources User Guide This guide describes the SelectIO resources available in all Virtex-6 devices. Virtex-6 FPGA GTX Transceivers User Guide This guide describes the GTX transceivers available in all Virtex-6 FPGAs except the XC6VLX760.

Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in all Virtex-6 FPGAs except the XC6VLX760.

Virtex-6 FPGA DSP48E1 Slice User Guide This guide describes the architecture of the DSP48E1 slice in Virtex-6 FPGAs and provides configuration examples.

Virtex-6 FPGA System Monitor User Guide The System Monitor functionality available in all Virtex-6 devices is outlined in this guide.

Virtex-6 FPGA PCB Design Guide This guide provides information on PCB design for Virtex-6 devices, with a focus on strategies for making design decisions at the PCB and interface level.

Additional Support Resources

To search the database of silicon and software questions and answers or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support.

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Chapter 1

ML605 Evaluation Board

Overview
The ML605 board enables hardware and software developers to create or evaluate designs targeting the Virtex-6 XC6VLX240T-1FFG1156 FPGA. The ML605 provides board features common to many embedded processing systems. Some commonly used features include: a DDR3 SODIMM memory, an 8-lane PCI Express interface, a tri-mode Ethernet PHY, general purpose I/O, and a UART. Additional user desired features can be added through mezzanine cards attached to the onboard high-speed VITA-57 FPGA Mezzanine Connector (FMC) high pin count (HPC) expansion connector, or the onboard VITA-57 FMC low pin count (LPC) connector. Features, page 10 provides a general listing of the board features with details provided in Detailed Description, page 13.

Additional Information
Additional information and support material is located at: http://www.xilinx.com/ml605

This information includes: Current version of this user guide in PDF format Example design files for demonstration of Virtex-6 FPGA features and technology Demonstration hardware and software configuration files for the System ACE CF controller, Platform Flash configuration storage device, and linear flash chip Reference design files Schematics in PDF and DxDesigner formats Bill of materials (BOM) Printed-circuit board (PCB) layout in Allegro PCB format Gerber files for the PCB (Many free or shareware Gerber file viewers are available on the internet for viewing and printing these files.) Additional documentation, errata, frequently asked questions, and the latest news

For information about the Virtex-6 family of FPGA devices, including product highlights, data sheets, user guides, and application notes, see the Virtex-6 FPGA documentation page at http://www.xilinx.com/support/documentation/virtex-6.htm.

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Chapter 1: ML605 Evaluation Board

Features
The ML605 provides the following features: 1. Virtex-6 XC6VLX240T-1FFG1156 FPGA 2. 512 MB DDR3 Memory SODIMM 3. 128 Mb Platform Flash XL 4. 32 MB Linear BPI Flash 5. System ACE CF and CompactFlash Connector 6. USB JTAG 7. Clock Generation Fixed 200 MHz oscillator (differential) Socketed 2.5V oscillator (single-ended) SMA connectors (differential) SMA connectors for MGT clocking FMC - HPC connector FMC - LPC connector SMA PCIe SFP Module connector Ethernet PHY SGMII interface Gen1 8-lane (x8) Gen2 4-lane (x4)

8. Multi-Gigabit Transceivers (GTX MGTs)

9. PCI Express Endpoint Connectivity

10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY 12. USB-to-UART Bridge 13. USB Controller 14. DVI Codec 15. IIC Bus IIC EEPROM - 1 KB DDR3 SODIMM socket DVI CODEC DVI connector FMC HPC connector FMC LPC connector SFP module connector

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Overview

16. Status LEDs Ethernet status FPGA INIT FPGA DONE System ACE CF Status USER LED Group 1 - GPIO (8) USER LED Group 2 - directional (5) User pushbuttons - directional (5) CPU reset pushbutton User DIP switch - GPIO (8-pole) User SMA GPIO connectors (2) LCD character display (16 characters x 2 lines) Power on/off slide switch System ACE CF reset pushbutton System ACE CF bitstream image select DIP switch Configuration MODE DIP switch

17. User I/O

18. Switches

19. VITA 57.1 FMC HPC Connector 20. VITA 57.1 FMC LPC Connector 21. Power Management PMBus voltage and current monitoring via TI power controller 22. System Monitor 3. 128 Mb Platform Flash XL 4. 32 MB Linear BPI Flash 5. System ACE CF and CompactFlash Connector 6. USB JTAG

Configuration Options

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Chapter 1: ML605 Evaluation Board

Block Diagram
Figure 1-1 shows a high-level block diagram of the ML605 and its peripherals.
X-Ref Target - Figure 1-1

System ACE CF S.A. CompactFlash S.A. 8-bit MPU I/F

JTAG USB Mini-B USB JTAG Circuit

VITA 57.1 FMC HPC Connector

VITA 57.1 FMC LPC Connector

Platform Flash Linear BPI Flash

BANK32 BANK24 BANK34

BANK12, 13 BANK15,16 BANK14,22 BANK34,116 BANK23,24 BANK112,113 BANK0

SYSMON I/F INIT, DONE LEDs PROG PB, MODE SW

DVI Codec VGA Video DVI Video Connector

BANK32 Virtex-6 FPGA XC6VLX240T - 1FFG1156

BANK33 BANK34

IIC Bus IIC EEPROM FMC HPC DDR3 SODIMM IIC FMC LPC

10/100/1000 Ethernet PHY MII/GMII/RMII

BANK33

BANK116

SFP Module Connector SGMII

BANK 25, 35 BANK 26, 36 SODIMM Socket 204-pin, DDR3 Decoupling Caps BANK14, 33, 36 BANK24,34 BANK14

BANK114 BANK115 BANK24 PCIe X8 Edge Connector MGT SMA REF Clock MGT RX/TX SMA Port

MEM Vterm Regulator

User LED/SW User DIP SW User LCD

200 MHz LVDS Clock SMA Clock User S.E. 2.5V Clock

USB Controller Host Type A Peripheral Mini-B Connectors

CP2103 USB-TO-UART Bridge USB Mini-B

UG534_01_092709

Figure 1-1:

ML605 High-Level Block Diagram

Related Xilinx Documents

Prior to using the ML605 Evaluation Board, users should be familiar with Xilinx resources. See Appendix A, References for a direct link to Xilinx documentation. See the following locations for additional documentation on Xilinx tools and solutions: ISE: www.xilinx.com/ise EDK: www.xilinx.com/edk Intellectual Property: www.xilinx.com/ipcenter Answer Browser: www.xilinx.com/support

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Detailed Description

Detailed Description
Figure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document.
X-Ref Target - Figure 1-2

17a 10 17d

20

19

13 21c

18a 13

16c 23

7b

7c

17e

18d

18c 21d

16b 5 18b

2 12 6 16a 1 22 11 8 3 17f 14 4 9 8 21a 17c 21a 7d

21b

17b 7a
(on backside)

15

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Figure 1-2:

ML605 Board Photo

The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1. Table 1-1:
Number 1 2 3 4 5 6

ML605 Features
Feature Virtex-6 FPGA DDR3 SODIMM 128 Mb Platform Flash XL Linear BPI Flash System ACE CF controller, CF connector JTAG cable connector (USB Mini-B) Notes XC6VLX240T-1FFG1156 Micron 512 MB MT4JSF6464HY-1G1 Xilinx XCF128X-FTG64C Numonyx JS28F256P30T95 Xilinx XCCACE-TQ144I (bottom of board) USB JTAG download circuit Schematic Page 2 - 12 15 25 26 13 46

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Table 1-1:
Number

ML605 Features (Contd)

Feature Clock generation a. 200 MHz oscillator (on backside) Notes 200 MHz OSC, oscillator socket, SMA connectors SiTime 200 MHz 2.5V LVDS OSC MMD Components 66 MHz 2.5V SMA pair SMA pair SMA x4 Card edge connector, 8-lane AMP 136073-1 Marvell M88E1111 EPHY Silicon Labs CP2103GM bridge Cypress CY7C67300-100AXI controller Chrontel CH7301C-TF Video codec ST Microelectronics M24C08WDW6TP Schematic Page 30 30 30 30 30 30 21 23 24 33 27 28, 29 32 13, 24, 31 Right-angle link rate and direction LEDs Init (red), Done (green) Status (green), Error (red) 24 31 13 31 User I/O (active-High) User I/O (active-High) User I/O (active-High) 30, 31, 33 31 31 31 30 33

b. Oscillator socket, singleended c. SMA connectors d. MGT REFCLK SMA connectors

8 9 10 11 12 13 14 15

GTX RX/TX port PCIe Gen1 (8-lane), Gen2 (4-lane) SFP connector and cage Ethernet (10/100/1000) with SGMII USB Mini-B, USB-to-UART bridge USB-A Host, USB Mini-B peripheral connectors Video - DVI connector IIC NV EEPROM, 8 Kb (on backside) Status LEDs a. Ethernet status

16 b. FPGA INIT, DONE c. System ACE CF status User I/O a. User LEDs, green (8) b. User pushbuttons, N.O. momentary (5) 17 c. User LEDs, green (5)

d. User DIP switch (8-pole) User I/O (active-High) e. User GPIO SMA connectors f. LCD 16 character x 2 line display SMA pair Displaytech S162D BA BC

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Detailed Description

Table 1-1:
Number

ML605 Features (Contd)

Feature Switches a. Power On/Off Slide switch active-Low 4-pole DIP switch (active-High) 6-pole DIP switch (active-High) Samtec ASP-134486-01 Samtec ASP-134603-01 Notes Schematic Page 13, 25, 39 39 13 25 25 16 -19 20 35 - 44 2 x TI UCD9240PFC 2 x PTD08A020W, 3 x PTD08A010W 6-pin Molex mini-fit connector 4-pin ATX disk type connector 2x6 DIP male pin header Jumper on = enable LED Jumper off = disable LED 35, 40 36-38, 43, 44 39 39 34 13

18

b. FPGA_PROG_B pushbutton c. System ACE CF Image Select d. Mode Switch

19 20

FMC - HPC connector FMC - LPC connector Power management a. PMBus controllers b. Voltage regulators

21 c. 12V power input connector d. 12V power input connector 22 23 System Monitor Interface connector System ACE Error DS30 LED disable jumper J69

1. Virtex-6 XC6VLX240T-1FFG1156 FPGA

A Virtex-6 XC6VLX240T-1FFG1156 FPGA is installed on the embedded development board. Keep-Out areas and drill holes are defined around the FPGA to support an Ironwood Electronics SG-BGA-6046 FPGA socket.

References
See the Virtex-6 FPGA Data Sheet. [Ref 4]

Configuration
The ML605 supports configuration in the following modes: Slave SelectMAP (using Platform Flash XL with the onboard 47 MHz oscillator) Master BPI-Up (using Linear BPI Flash device) JTAG (using the included USB-A to Mini-B cable) JTAG (using System ACE CF and CompactFlash card)

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The ML605 supports Master BPI-Up, JTAG, and Slave SelectMAP. These are selected by setting M[2:0] options 010, 101 and 110 shown in Table 1-2. Table 1-2: Virtex-6 FPGA Configuration Modes
M[2:0] 000 001 010 011 100 101 110 111
Bus Width(1)

Configuration Mode
Master Serial(2) Master SPI(2)

CCLK Direction Output Output Output Output Output Input (TCK) Input Input

1 1 8, 16 8, 16 8, 16 1 8, 16, 32 1

Master BPI-Up(2) Master BPI-Down(2) Master SelectMAP(2) JTAG Slave SelectMAP Slave Serial(3)
Notes:

1. The parallel configuration modes bus is auto-detected by the configuration logic. 2. In Master configuration mode, the CCLK pin is the clock source for the Virtex-6 FPGA internal configuration logic. The Virtex-6 FPGA CCLK output pin must be free from reflections to avoid double-clocking the internal configuration logic. See the Virtex-6 FPGA Configuration User Guide for more details. [Ref 5] 3. This is the default setting due to internal pull-up termination on mode pins.

For an overview on configuring the FPGA, see Configuration Options, page 76. Note: The mode switches are part of DIP switch S2. The default mode setting (see Table B-34,
page 79) is M[2:0]=010, which selects Master BPI-Up at board power-on. Switch S1 position 4 must be OFF to disable the System ACE controller from attempting to boot if a CF card is present.

References
See the Virtex-6 FPGA Configuration User Guide for detailed configuration information. [Ref 5]

I/O Voltage Rails

There are 16 I/O banks available on the Virtex-6 device. The voltage applied to the FPGA I/O banks used by the ML605 board is summarized in Table 1-3. Table 1-3: Voltage Rails
I/O Rail VCC2V5_FPGA FMC_VIO_B_M2C VCC2V5_FPGA VCC2V5_FPGA VCC2V5_FPGA VCC2V5_FPGA VCC2V5_FPGA VCC2V5_FPGA Voltage 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V U1 FPGA Bank Bank 0 Bank 12(1) Bank 13 Bank 14 Bank 15 Bank 16 Bank 22 Bank 23

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Table 1-3:

Voltage Rails (Contd)

I/O Rail VCC2V5_FPGA VCC1V5_FPGA VCC1V5_FPGA VCC2V5_FPGA VCC2V5_FPGA VCC2V5_FPGA VCC1V5_FPGA VCC1V5_FPGA Voltage 2.5V 1.5V 1.5V 2.5V 2.5V 2.5V 1.5V 1.5V

U1 FPGA Bank Bank 24 Bank 25 Bank 26 Bank 32 Bank 33 Bank 34 Bank 35 Bank 36
Notes:

1. The VITA 57.1 specification stipulates that the Bank 12 voltage named FMC_VIO_B_M2C is supplied by the FMC card plugged onto the relevant FMC connector (ML605 J64). FMC_VIO_B_M2C cannot exceed the base board (ML605) Vadj of the FMC connector. The ML605 FMC Vadj maximum is 2.5V.

References
See the Xilinx Virtex-6 FPGA documentation for more information at http://www.xilinx.com/support/documentation/virtex-6.htm.

2. 512 MB DDR3 Memory SODIMM

A 512MB DDR3 SODIMM is provided as a flexible and efficient form-factor volatile memory for user applications. The ML605 SODIMM socket is wired to support a maximum SODIMM size of 2 GB. The ML605 DDR3 64-bit wide interface has been tested to 800 MT/s. The DDR3 interface is implemented in FPGA banks 25, 26, 35, and 36. DCI VRP/N resistor connections are only implemented banks 26 and 36. DCI functionality in banks 25 and 35 is achieved in the UCF by cascading DCI between adjacent banks as follows:
CONFIG DCI_CASCADE = "36 35"; CONFIG DCI_CASCADE = "26 25";

Table 1-4 shows the connections and pin numbers for the DDR3 SODIMM. Table 1-4: DDR3 SODIMM Connections
J1 SODIMM U1 FPGA Pin L14 A16 B16 E16 D16 J17 Schematic Net Name Pin Number DDR3_A0 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A5 98 97 96 95 92 91 Pin Name A0 A1 A2 A3 A4 A5

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Table 1-4:

DDR3 SODIMM Connections (Contd)

J1 SODIMM Schematic Net Name Pin Number Pin Name A6 A7 A8 A9 A10/AP A11 A12_BC_N A13 A14 A15 BA0 BA1 BA2 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A9 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A13 DDR3_A14 DDR3_A15 DDR3_BA0 DDR3_BA1 DDR3_BA2 90 86 89 85 107 84 83 119 80 78 109 108 79

U1 FPGA Pin A15 B15 G15 F15 M16 M15 H15 J15 D15 C15 K19 J19 L15

J11 E13 F13 K11 L11 K13 K12 D11 M13 J14 B13 B12 G10 M11 C12 A11 G11 F11 D14 C14

DDR3_D0 DDR3_D1 DDR3_D2 DDR3_D3 DDR3_D4 DDR3_D5 DDR3_D6 DDR3_D7 DDR3_D8 DDR3_D9 DDR3_D10 DDR3_D11 DDR3_D12 DDR3_D13 DDR3_D14 DDR3_D15 DDR3_D16 DDR3_D17 DDR3_D18 DDR3_D19

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19

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Table 1-4:

DDR3 SODIMM Connections (Contd)

J1 SODIMM Schematic Net Name Pin Number Pin Name DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DDR3_D20 DDR3_D21 DDR3_D22 DDR3_D23 DDR3_D24 DDR3_D25 DDR3_D26 DDR3_D27 DDR3_D28 DDR3_D29 DDR3_D30 DDR3_D31 DDR3_D32 DDR3_D33 DDR3_D34 DDR3_D35 DDR3_D36 DDR3_D37 DDR3_D38 DDR3_D39 DDR3_D40 DDR3_D41 DDR3_D42 DDR3_D43 DDR3_D44 DDR3_D45 DDR3_D46 DDR3_D47 DDR3_D48 DDR3_D49 DDR3_D50 DDR3_D51 DDR3_D52 DDR3_D53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166

U1 FPGA Pin G12 G13 F14 H14 C19 G20 E19 F20 A20 A21 E22 E23 G21 B21 A23 A24 C20 D20 J20 G22 D26 F26 B26 E26 C24 D25 D27 C25 C27 B28 D29 B27 G27 A28

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Table 1-4:

DDR3 SODIMM Connections (Contd)

J1 SODIMM Schematic Net Name Pin Number Pin Name DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DDR3_D54 DDR3_D55 DDR3_D56 DDR3_D57 DDR3_D58 DDR3_D59 DDR3_D60 DDR3_D61 DDR3_D62 DDR3_D63 DDR3_DM0 DDR3_DM1 DDR3_DM2 DDR3_DM3 DDR3_DM4 DDR3_DM5 DDR3_DM6 DDR3_DM7 174 176 181 183 191 193 180 182 192 194 11 28 46 63 136 153 170 187

U1 FPGA Pin E24 G25 F28 B31 H29 H28 B30 A30 E29 F29 E11 B11 E14 D19 B22 A26 A29 A31

E12 D12 J12 H12 A14 A13 H20 H19 C23 B23 A25 B25 G28 H27 D30

DDR3_DQS0_N DDR3_DQS0_P DDR3_DQS1_N DDR3_DQS1_P DDR3_DQS2_N DDR3_DQS2_P DDR3_DQS3_N DDR3_DQS3_P DDR3_DQS4_N DDR3_DQS4_P DDR3_DQS5_N DDR3_DQS5_P DDR3_DQS6_N DDR3_DQS6_P DDR3_DQS7_N

10 12 27 29 45 47 62 64 135 137 152 154 169 171 186

DQS0_N DQS0_P DQS1_N DQS1_P DQS2_N DQS2_P DQS3_N DQS3_P DQS4_N DQS4_P DQS5_N DQS5_P DQS6_N DQS6_P DQS7_N

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Table 1-4:

DDR3 SODIMM Connections (Contd)

J1 SODIMM Schematic Net Name Pin Number Pin Name DQS7_P DDR3_DQS7_P 188

U1 FPGA Pin C30

F18 E17 E18 K18 K17 D17 B17 C17 L19 M18 M17 H18 G18 L16 K16

DDR3_ODT0 DDR3_ODT1 DDR3_RESET_B DDR3_S0_B DDR3_S1_B DDR3_TEMP_EVENT DDR3_WE_B DDR3_CAS_B DDR3_RAS_B DDR3_CKE0 DDR3_CKE1 DDR3_CLK0_N DDR3_CLK0_P DDR3_CLK1_N DDR3_CLK1_P

116 120 30 114 121 198 113 115 110 73 74 103 101 104 102

ODT0 ODT1 RESET_B S0_B S1_B EVENT_B WE_B CAS_B RAS_B CKE0 CKE1 CK0_N CK0_P CK1_N CK1_P

The Memory Interface Generator (MIG) tool guidelines specify a set of U1 FPGA No Connect pins. These should be added to the UCF as CONFIG PROHIBIT pins as follows:
CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG PROHIBIT PROHIBIT PROHIBIT PROHIBIT PROHIBIT PROHIBIT PROHIBIT PROHIBIT PROHIBIT PROHIBIT PROHIBIT PROHIBIT = = = = = = = = = = = = H22; F21; B20; F19; C13; M12; L13; K14; F25; C29; C28; D24;

References
See the Micron Technology, Inc. for more information [Ref 22]. In addition, see the Virtex-6 FPGA Memory Interface Solutions User Guide [Ref 6] and the Virtex-6 FPGA Memory Resources User Guide [Ref 9].

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3. 128 Mb Platform Flash XL

A 128 Mb Xilinx XCF128X-FTG64C Platform Flash XL device is used with an onboard 47 MHz oscillator (X4) to configure the FPGA in less than 100 ms from power valid as required by the PCI Express Card Electromechanical Specification. This allows the PCIe interface to be recognized and enumerated when plugged into a host PC. To achieve the fastest configuration speed, the FPGA mode pins are set to Slave SelectMAP and the onboard 47 MHz clock source external to the FPGA is used for configuration. Configuration DIP switch S2, switch 1, controls the 47 MHz oscillator enable as outlined in 18. Switches, page 55. See S2 switch setting details in Table 1-26, page 58. Also, see the FPGA Design Considerations for the Configuration Flash, page 25 for FPGA design recommendations.

4. 32 MB Linear BPI Flash

A Numonyx JS28F256P30 Linear BPI Flash memory (P30) on the ML605 provides 32 MB of non-volatile storage that can be used for configuration as well as software storage. The Linear BPI Flash shares the dual use configuration pins in parallel with the XCF128 Platform Flash XL. The P30_CS net is used to select the P30 or the XCF128. Power-on configuration is selected by the P30_CS net which is tied to a dip switch S2 (selects pullup/pulldown) and is also wired to an FPGA non-config pin. The dip switch allows power selection for the configuration device P30 or XCF128XL. The dip switch selection can be overridden by the FPGA after configuration by controlling the logic level of the P30_CS signal. See S2 switch setting details in Table 1-26, page 58. For an overview on configuring the FPGA, see Configuration Options, page 76. Figure 1-3 shows a block diagram for the Platform Flash and BPI Flash.
X-Ref Target - Figure 1-3

U27 PLATFORM FLASH FPGA U1 Bank 34 FLASH_A[22:0] A D

S1 Switch 4
OFF = Disable System ACE, enable U4/U27 flash boot ON = Enable System ACE boot when CF card is present

S2 SWITCH 6 ON = U4 BPI Upper Half OFF = U4 BPI Lower Half

CE

FLASH_D[15:0] FPGA U1 VCC2V5 Bank 24 U10 6 PLATFLASH_FCS_B VCC2V5 510 S2-2 2 11 1 4.7K

U4 BPI FLASH A D

P30_CS_SEL (FPGA U1 pin AJ12)

FPGA U1 Bank 24

FLASH_A[23]

S2 SWITCH 2 ON = U4 BOOT OFF = U27 BOOT

VCC2V5 510 S2-6 6 7 4.7K

VCC2V5 4 FLASH_CE_B 3 FPGA_FCS_B FPGA U1 Bank 24

UG534_03_011110

A23

Figure 1-3:

Platform Flash and BPI Flash Block Diagram

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ML605 Flash Boot Options

The ML605 has two parallel wired flash memory devices as shown in Figure 1-3. At ML605 power-up, before FPGA configuration, DIP switch S2 switch 2 selects which flash device, U4 (BPI) or U27 (Platform Flash), provides the boot bitstream. Typically S2 switch 2 will be open/OFF to select the U27 Platform Flash. Given that the mode switches (S2 switch 3/M0, switch 4/M1 and switch 5/M2) are set to Slave SelectMAP mode, then U27, driven at 47 MHz, can load a PCIe core bitstream before a host PC motherboard can scan its PCIe slots.When S2 switch 2 is closed/ON at power up, the FPGA will be configured from the BPI flash device U4. Note that U4 address bit A23 is switched by S2 switch 6, which allows the lower or upper half of U4 to be chosen as a data source. Table 1-5 shows the connections and pin numbers for the boot flash devices. Table 1-5: Platform Flash and BPI Flash Connections
U4 BPI Flash U1 FPGA Pin AL8 AK8 AC9 AD10 C8 B8 E9 E8 A8 A9 D9 C9 D10 C10 F10 F9 AH8 AG8 AP9 AN9 AF10 AF9 AL9 AA23 Schematic Net Name Pin Number FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 29 25 24 23 22 21 20 19 8 7 6 5 4 3 2 1 55 18 17 16 11 10 9 26 Pin Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 Pin Number A1 B1 C1 D1 D2 A2 C2 A3 B3 C3 D3 C4 A5 B5 C5 D7 D8 A7 B7 C7 C8 A8 G1 NC Pin Name A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 U27 Platform Flash

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Table 1-5:

Platform Flash and BPI Flash Connections (Contd)

U4 BPI Flash U27 Platform Flash Pin Number Pin Name Schematic Net Name Pin Number Pin Name

U1 FPGA Pin

AF24 AF25 W24 V24 H24 H25 P24 R24 G23 H23 N24 N23 F23 F24 L24 M23

FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_D8 FLASH_D9 FLASH_D10 FLASH_D11 FLASH_D12 FLASH_D13 FLASH_D14 FLASH_D15

34 36 39 41 47 49 51 53 35 37 40 42 48 50 52 54

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

F2 E2 G3 E4 E5 G5 G6 H7 E1 E3 F3 F4 F5 H5 G7 E7

DQ00 DQ01 DQ02 DQ03 DQ04 DQ05 DQ06 DQ07 DQ08 DQ09 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

J26 AF23 AA24 K8 AC23 Y24 NA(1) NA(1)

Notes:
1. 2. 3. 4.

FLASH_WAIT FPGA_FWE_B FPGA_FOE_B FPGA_CCLK PLATFLASH_L_B FPGA_FCS_B(2) PLATFLASH_FCS_B(3) FLASH_CE_B(4)

56 14 32 NA(1) NA(1) NA(1) NA(1) 30

WAIT /WE /OE NA(1) NA(1) NA(1) NA(1) /OE

NA(1) G8 F8 F1 H1 NA(1) B4 NA(1)

NA(1) /W /G K /L NA(1) /E NA(1)

Not Applicable FPGA control flash memory select signal connected to pin U10.3 Platform Flash select signal connected to pin U10.6 BPI Flash select signal connected to pin U10.4

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FPGA Design Considerations for the Configuration Flash

After FPGA configuration, the FPGA design can disable the configuration flash or access the configuration flash to read/write code or data. When the FPGA design does not use the configuration flash, the FPGA design must drive the FPGA FCS_B pin High in order to disable the configuration flash and put the flash into a quiescent, low-power state. Otherwise, the Platform Flash XL, in particular, can continue to drive its array data onto the data bus causing unnecessary switching noise and power consumption. For FPGA designs that access the flash for reading/writing stored code or data, connect the FPGA design or EDK embedded memory controller (EMC) peripheral to the flash through the pins defined in Table 1-5, page 23. The Platform Flash XL defaults to a synchronous read mode. Typically, the Platform Flash XL requires an initialization procedure to put the Platform Flash XL into the common, asynchronous read mode before accessing stored code or data. To put the Platform Flash XL into asynchronous read mode, apply the Set Configuration Register command sequence. See the Platform Flash XL High-Density Configuration and Storage Device Data Sheet for details on the Set Configuration Register command. [Ref 17]

References
See the Numonyx StrataFlash Embedded Memory Data Sheet. [Ref 24] Visit the Xilinx Platform Flash product page and click the Resources tab for more information. Also, see the Platform Flash XL High-Density Configuration and Storage Device Data Sheet [Ref 17] and the Virtex-6 Configuration User Guide [Ref 10].

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5. System ACE CF and CompactFlash Connector

The Xilinx System ACE CompactFlash (CF) configuration controller allows a Type I or Type II CompactFlash card to program the FPGA through the JTAG port. Both hardware and software data can be downloaded through the JTAG port. The System ACE CF controller supports up to eight configuration images on a single CompactFlash card. The configuration address switches allow the user to choose which of the eight configuration images to use. The CompactFlash (CF) card shipped with the board is correctly formatted to enable the System ACE CF controller to access the data stored in the card. The System ACE CF controller requires a FAT16 file system, with only one reserved sector permitted, and a sector-per-cluster size of more than one (UnitSize greater than 512). The FAT16 file system supports partitions of up to 2 GB. If multiple partitions are used, the System ACE CF directory structure must reside in the first partition on the CompactFlash, with the xilinx.sys file located in the root directory. The xilinx.sys file is used by the System ACE CF controller to define the project directory structure, which consists of one main folder containing eight sub-folders used to store the eight ACE files containing the configuration images. Only one ACE file should exist within each sub-folder. All folder names must be compliant to the DOS 8.3 short file name format. This means that the folder names can be up to eight characters long, and cannot contain the following reserved characters: < > " / \ |. This DOS 8.3 file name restriction does not apply to the actual ACE file names. Other folders and files may also coexist with the System ACE CF project within the FAT16 partition. However, the root directory must not contain more than a total of 16 folder and/or file entries, including deleted entries. When ejecting or unplugging the CompactFlash device, it is important to safely stop any read or write access to the CompactFlash device to avoid data corruption. System ACE CF error and status LEDs indicate the operational state of the System ACE CF controller: A blinking red error LED indicates that no CompactFlash card is present. A solid red error LED indicates an error condition during configuration. A blinking green status LED indicates a configuration operation is ongoing. A solid green status LED indicates a successful download.

Note: Jumper J69 can be removed to disable the Red Error LED circuit. It is recommended that this
jumper is installed during operations utilizing the CompactFlash card.

Every time a CompactFlash card is inserted into the System ACE CF socket, a configuration operation is initiated. Pressing the System ACE CF reset button re-programs the FPGA. Note: System ACE CF configuration is enabled by way of DIP switch S1. See 18. Switches, page 55 for more details. The System ACE CF MPU port is connected to the FPGA. This connection allows the FPGA to use the System ACE CF controller to reconfigure the system or access the CompactFlash card as a generic FAT file system.

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Table 1-6 lists the System ACE CF connections. Table 1-6: System ACE CF Connections
U19 XCCACETQ144I U1 FPGA Pin AM15 AJ17 AJ16 AP16 AG16 AH15 AF16 AN15 AC15 AP15 AG17 AH17 AG15 AF15 AK14 AJ15 AJ14 L9 AL15 AL14 AC8 AE8 AD8 AF8 AE16
Notes:
1. The System ACE CF clock is sourced from U28 33.000 MHz osc.

Schematic Net Name Pin Number SYSACE_D0 SYSACE_D1 SYSACE_D2 SYSACE_D3 SYSACE_D4 SYSACE_D5 SYSACE_D6 SYSACE_D7 SYSACE_MPA00 SYSACE_MPA01 SYSACE_MPA02 SYSACE_MPA03 SYSACE_MPA04 SYSACE_MPA05 SYSACE_MPA06 SYSACE_MPBRDY SYSACE_MPCE SYSACE_MPIRQ SYSACE_MPOE SYSACE_MPWE SYSACE_CFGTDI FPGA_TCK FPGA_TDI FPGA_TMS CLK_33MHZ_SYSACE(1) 66 65 63 62 61 60 59 58 70 69 68 67 45 44 43 39 42 41 77 76 81 80 82 85 93 Pin Name MPD00 MPD01 MPD02 MPD03 MPD04 MPD05 MPD06 MPD07 MPA00 MPA01 MPA02 MPA03 MPA04 MPA05 MPA06 MPBRDY MPCE MPIRQ MPOE MPWE CFGTDI CFGTCK CFGTDO CFGTMS CLK

References
See the System ACE CF product page and the System ACE CompactFlash Solution Data Sheet. [Ref 18]

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6. USB JTAG
JTAG configuration is provided through onboard USB-to-JTAG configuration logic where a computer host accesses the ML605 JTAG chain through a Type-A (computer host side) to Type-Mini-B (ML605 side) USB cable. The JTAG chain of the board is illustrated in Figure 1-4. JTAG configuration is allowable at any time under any mode pin setting. JTAG initiated configuration takes priority over the mode pin settings.
X-Ref Target - Figure 1-4

J17

J18

3.3V

2.5V

J22 USB Mini-B

FMC HPC
TDI TDO

FMC LPC TDI TDO

System ACE CF
TSTTDI CFGTDO

FPGA
TDI U1 TDO

J64

J63

U19
TSTTDO CFGTDI

UG534_04_081309

Figure 1-4:

JTAG Chain Diagram

FMC bypass jumpers J17 and J18 must be connected between pins 1-2 (bypass) to enable JTAG access to the FPGA on the basic ML605 board (without FMC expansion modules installed), as shown in Figure 1-5 and Figure 1-6. When either or both VITA 57.1 FMC expansion connectors are populated with an expansion module that has a JTAG chain, the respective jumper(s) must be set to connect pins 2-3 in order to include the FMC expansion module's JTAG chain in the main ML605 JTAG chain.
X-Ref Target - Figure 1-5

J17
1

FMC_TDI_BUF
2

Bypass FMC HPC J64 = Jumper 1-2

FMC_LPC_TDI
3

Include FMC HPC J64 = Jumper 2-3

FMC_HPC_TDO H - 1x3
UG534_05_081309

Figure 1-5:
X-Ref Target - Figure 1-6

VITA 57.1 FMC HPC (J64) JTAG Bypass Jumper J17

J18
1

FMC_LPC_TDI
2

Bypass FMC LPC J63 = Jumper 1-2

SYSACE_TDI
3

Include FMC LPC J63 = Jumper 2-3

FMC_LPC_TDO H - 1x3
UG534_06_081309

Figure 1-6:

VITA 57.1 FMC LPC (J63) JTAG Bypass Jumper J18

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The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug. The JTAG connector (USB Mini-B J22) allows a host computer to download bitstreams to the FPGA using the Xilinx iMPACT software tool. In addition, the JTAG connector allows debug tools such as the ChipScope Pro Analyzer tool or a software debugger to access the FPGA. The iMPACT software tool can also program the BPI flash via the USB J22 connection. iMPACT can download a temporary design to the FPGA through the JTAG. This provides a connection within the FPGA from the FPGA's JTAG port to the FPGA's BPI interface. Through the connection made by the temporary design in the FPGA, iMPACT can indirectly program the BPI flash or the Platform Flash XL from the JTAG USB J22 connector. For an overview on configuring the FPGA, see Configuration Options, page 76.

7. Clock Generation
There are three FPGA fabric clock sources available on the ML605 (refer to Table 1-7).

Oscillator (Differential)
The ML605 has one 2.5V LVDS differential 200 MHz oscillator (U11) soldered onto the board and wired to an FPGA global clock input. The 200 MHz signal names are SYSCLK_N and SYSCLK_P. Crystal oscillator: SiTime SiT9102AI-243N25E200.00000 Frequency stability: 50 ppm

For more details, see the SiTime SiT9102 data sheet [Ref 25]. For more information about LVDS clocking, refer to DS152 [Ref 4].

Oscillator Socket (Single-Ended, 2.5V)

One populated single-ended clock socket (X5) is provided for user applications. The X5 socket is populated with a 66 MHz 2.5V single-ended MMD Components MBH2100H66.000 MHz oscillator. The 66 MHz signal name is USER_CLOCK. For more information about LVDS clocking, refer to DS152 [Ref 4].

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X-Ref Target - Figure 1-7

Silkscreened outline has beveled corner Socket has notch in crossbar

UG534_07_092109

Figure 1-7: ML605 Oscillator Socket Pin 1 Location Identifiers

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X-Ref Target - Figure 1-8

Oscillator body has one square corner Oscillator top has corner dot marking

UG534_08_092109

Figure 1-8:

ML605 Oscillator Pin 1 Location Identifiers

SMA Connectors (Differential)

A high-precision clock signal can be provided to the FPGA using differential clock signals through the onboard 50 SMA connectors J58(P)/J55(N). This differential user clock has the signal names USER_SMA_CLOCK_N and USER_SMA_CLOCK_P.

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GTX SMA Clock

The ML605 includes a pair of SMA connectors for a GTX (MGT) Clock as described in Figure 1-9 and Table 1-7.
X-Ref Target - Figure 1-9

J30 32K10K-400E3
GND1 GND2 GND3 SIG GND4 GND5 GND6 GND7 2 3 4 5 6 7 8

SMA_REFCLK_N SMA_REFCLK_P

C61 1 0.1UF 10V 2 X5R

SMA_REFCLK_C_N1

J31 32K10K-400E3
GND1 GND2 GND3 SIG GND4 GND5 GND6 GND7 2 3 4 5 6 7 8

C62 1 0.1UF 10V 2 X5R

SMA_REFCLK_C_P1

UG534_09_081309

Figure 1-9: Table 1-7:

GTX SMA Clock

ML605 Clock Connections

Schematic Net Name SYSCLK_N SYSCLK_P USER_CLOCK SMA_REFCLK_N SMA_REFCLK_P USER_SMA_CLOCK_N USER_SMA_CLOCK_P SMA Pin U11.5 U11.4 X5.5 J30.1 J31.1 J55.1 J58.1

U1 FPGA Pin H9 J9 U23 F5 F6 M22 L23

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8. Multi-Gigabit Transceivers (GTX MGTs)

The ML605 provides access to 20 MGTs.
X-Ref Target - Figure 1-10

Eight (8) of the MGTs are wired to the PCIe x8 Endpoint (P1) edge connector fingers Eight (8) of the MGTs are wired to the FMC HPC connector (J64) One (1) MGT is wired to SMA connectors (J26, J27) One (1) MGTs is wired to the FMC LPC connector (J63) One (1) MGT is wired to the SFP Module connector (P4) One (1) MGT is used for an SGMII connection to the Ethernet PHY (U80)

Note: xxx MHz = user specified frequency

GTX_X0Y19 GTX_X0Y18 REFCLK0 REFCLK1 GTX_X0Y17 GTX_X0Y16 GTX_X0Y15

SGMII 125 MHz LVDS SMA xxx MHz LVDS

BANK_116 BANK_115

SGMII SMA

SFP FMC#2 PCIe Lane1 PCIe Lane 2

100 MHz LVDS FMC#2 LPC xxx MHz GBTCLK0 LVDS AC coupling on Mezz 100 MHz in from PCIe Fingers (HCSL)

GTX_X0Y14 REFCLK0 REFCLK1 GTX_X0Y13

ICS 854104

250 MHz LVDS

ICS874001
No Connect No Connect

GTX_X0Y12 GTX_X0Y11 GTX_X0Y10 REFCLK0

PCIe Lane 3 PCIe Lane 4 PCIe Lane 5 PCIe Lane 6

PCIe

No Connect

REFCLK1 GTX_X0Y09 GTX_X0Y08 GTX_X0Y07 GTX_X0Y06

BANK_114 BANK_113

PCIe Lane 7 PCIe Lane 8 FMC#1 FMC#1

FMC#1 HPC xxx MHz LVDS GBTCLK0 AC coupling on Mezz FMC#1 HPC CLK2_M2C (LVDS)

(LVDS)

REFCLK0 REFCLK1
GTX_X0Y05

ICS 854104
To FPGA CLK2_M2C_IO CC pin

GTX_X0Y04

FMC#1 FMC#1 FMC#1 FMC#1

PCIe

GTX_X0Y03 GTX_X0Y02

(LVDS) FMC#1 HPC CLK3_M2C (LVDS)

REFCLK0 REFCLK1 GTX_X0Y01

ICS 854104
To FPGA CLK3_M2C_IO CC pin

BANK_112

FMC#1 HPC xxx MHz LVDS GBTCLK1 AC coupling on Mezz

GTX_X0Y00

FMC#1 FMC#1
UG534_10_021012

Figure 1-10:

MGT Clocking

References
See the Virtex-6 FPGA GTX Transceivers User Guide. [Ref 12]

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9. PCI Express Endpoint Connectivity

The 8-lane PCIe edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1 application and 5.0 GT/s for a Gen2 application. The Virtex FPGA GTX MGTs are used for the multi-gigabit per second serial interfaces. The ML605 board trace impedance on all PCIe lanes supports both Gen1 and Gen2 applications. The ML605 supports up to Gen1 x8 and Gen2 x4 as shipped with a -1 speed grade for the LX240T device. Figure 1-11 is a diagram of the PCIe MGT bank 114 and 115 clocking.
X-Ref Target - Figure 1-11

Note: PCIe edge connector signal nomenclature is from perspective of the system/motherboard.

P1
REFCLK+,-

U14
PCIE_CLK_Q0_P/N CLK/NCLK Q0/NQ0

U9

Q1/NQ1 PCIE_100M_MGT1_P/N CLK/NCLK Q/NQ

ICS854104
PCIE_100M_MGT0_C_P/N PCIE_100M_MGT0_P/N PERp,n[7:0] PETp,n[7:0]

ICS874001
PCIE_250M_MGT1_C_P/N PCIE_250M_MGT1_P/N

U1 Bank 115
MGTREFCLK0 P/N MGTTX P/N[3:0] MGTRX P/N[3:0]

U1 Bank 114
MGTREFCLK0 P/N MGTTX P/N[7:4] PCIE_TX[7:0]_P/N PCIE_RX[7:0]_P/N
UG534_11_100809

PCIe 8-Lane Edge Connector

MGTRX P/N[7:4]

Figure 1-11:

PCIe MGT Banks 114 and 115 Clocking

PCIe lane width/size is selected via jumper J42 as shown in Figure 1-12. The default lane size selection is 1-lane (J42 pins 1 and 2 jumpered).
X-Ref Target - Figure 1-12

J42 PCIE_PRSNT_X1 PCIE_PRSNT_X4 PCIE_PRSNT_X8

1 3 5 2 4 6

PCIE_PRSNT_B

H-2X3

UG534_12_111709

Figure 1-12:

PCIe Lane Size Select Jumper J42

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Table 1-8 shows the PCIe connector (P1) that provides up to 8-lane access through the GTX transceivers to the Virtex-6 FPGA integrated Endpoint block for PCIe designs. Table 1-8:
U1 FPGA Pin F1 F2 H1 H2 K1 K2 M1 M2 P1 P2 T1 T2 V1 V2 Y1 Y2 J3 J4 K5 K6 L3 L4 N3 N4 R3 R4 U3 U4 W3 W4

PCIe Edge Connector Connections

P1 PCIe Edge Connector Schematic Net Name Pin Number PCIE_TXO_P PCIE_TXO_N PCIE_TX1_P PCIE_TX1_N PCIE_TX2_P PCIE_TX2_N PCIE_TX3_P PCIE_TX3_N PCIE_TX4_P PCIE_TX4_N PCIE_TX5_P PCIE_TX5_N PCIE_TX6_P PCIE_TX6_N PCIE_TX7_P PCIE_TX7_N PCIE_RXO_P PCIE_RXO_N PCIE_RX1_P PCIE_RX1_N PCIE_RX2_P PCIE_RX2_N PCIE_RX3_P PCIE_RX3_N PCIE_RX4_P PCIE_RX4_N PCIE_RX5_P PCIE_RX5_N PCIE_RX6_P PCIE_RX6_N A16 A17 A21 A22 A25 A26 A29 A30 A35 A36 A39 A40 A43 A44 A47 A48 B14 B15 B19 B20 B23 B24 B27 B28 B33 B34 B37 B38 B41 B42 Pin Name PERp0 PERn0 PERp1 PERn1 PERp2 PERn2 PERp3 PERn3 PERp4 PERn4 PERp5 PERn5 PERp6 PERn6 PERp7 PERn7 PETp0 PETn0 PETp1 PETn1 PETp2 PETn2 PETp3 PETn3 PETp4 PETn4 PETp5 PETn5 PETp6 PETn6 Integrated Endpoint block transmit pair Integrated Endpoint block transmit pair Integrated Endpoint block transmit pair Integrated Endpoint block transmit pair Integrated Endpoint block transmit pair Integrated Endpoint block transmit pair Integrated Endpoint block transmit pair Integrated Endpoint block transmit pair Integrated Endpoint block receive pair Integrated Endpoint block receive pair Integrated Endpoint block receive pair Integrated Endpoint block receive pair Integrated Endpoint block receive pair Integrated Endpoint block receive pair Integrated Endpoint block receive pair Description Package Placement GTXE1_X0Y15

GTXE1_X0Y14

GTXE1_X0Y13

GTXE1_X0Y12

GTXE1_X0Y11

GTXE1_X0Y10

GTXE1_X0Y9

GTXE1_X0Y8

GTXE1_X0Y15

GTXE1_X0Y14

GTXE1_X0Y13

GTXE1_X0Y12

GTXE1_X0Y11

GTXE1_X0Y10

GTXE1_X0Y9

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Table 1-8:
U1 FPGA Pin AA3 AA4 P6 P5 V6 V5 U14.6 U14.7 J42.2,4,6 AD22

PCIe Edge Connector Connections (Contd)

P1 PCIe Edge Connector Schematic Net Name Pin Number PCIE_RX7_P PCIE_RX7_N PCIE_100M_MGT0_P PCIE_100M_MGT0_N PCIE_250M_MGT1_P PCIE_250M_MGT1_N PCIE_CLK_QO_P PCIE_CLK_QO_N PCIE_PRSNT_B PCIE_WAKE_B B45 B46 U14.16 U14.15 U9.18 U9.17 A13 A14 A1 B11 Pin Name PETp7 PETn7 Q0 NQ0 Q NQ REFCLK+ REFCLKPRSNT#1 WAKE# Integrated Endpoint block receive pair Sourced from U14 ICS854104 clock driver Sourced from U9 ICS874001 clock multiplier/driver Integrated Endpoint block differential clock pair from PCIe edge connector J42 Lane Size Select jumper Integrated Endpoint block wake signal, not connected on ML605 board Integrated Endpoint block reset signal Description Package Placement GTXE1_X0Y8 IBUF_ GTXE1_X0Y6 IBUF_ GTXE1_X0Y4

AE13
Notes:
1. 2. 3. 4. 5.

PCIE_PERST_B

A11

PERST

PCIE_TXn_P/N pairs are capacitively coupled to FPGA PCIE_100M_MGT0_P/N pairs are capacitively coupled to FPGA PCIE_250M_MGT1_P/N pairs are capacitively coupled to FPGA PCIE_PERST_B is level-shifted by U32 For ML605, access is through MGT Banks 114 and 115

The PCIe interface obtains its power from the DC power supply provided with the ML605 or through the 12V ATX power supply connector. The PCIe edge connector is not used for any power connections. The board can be powered by one of two 12V sources; J60, a 6-pin (2x3) molex-type connector and J25, a 4-pin (inline) ATX disk drive type connector. The 6-pin molex-type connector provides 60W (12V @ 5A) from the AC power adapter provided with the board while the 4-pin ATX disk drive connector is provided for users who want to power their board while it is installed inside a PC chassis. For applications requiring additional power, such as the use of expansion cards drawing significant power, a larger AC adapter might be required. If a different AC adapter is used, its load regulation should be better than 10%. ML605 power switch SW2 turns the board on and off by controlling the 12V supply to the board. Caution! Never apply power to the power brick connector (J60) and the 4-pin ATX disk drive
connector (J25) at the same time as this will result in damage to the board. See Figure 1-23, page 55. Never connect an auxiliary PCIe 6-pin molex power connector to J60 6-pin molex on the ML605 board as this could result in damage to the PCIe motherboard and/or ML605 board. The 6-pin molex connector is marked with a no PCIe power label to warn users of the potential hazard.

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References
See the following websites for more Virtex-6 FPGA Integrated Endpoint Block for PCI Express information: http://www.xilinx.com/products/ipcenter/V6_PCI_Express_Block.htm http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pciexpress_v6pciexpressendpointblock.htm

In addition, see the PCI Express specifications for more information. [Ref 27]

10. SFP Module Connector

The board contains a small form-factor pluggable (SFP) connector and cage assembly that accepts SFP modules. The SFP interface is connected to MGT Bank 116 on the FPGA. The SFP module serial ID interface is connected to the SFP IIC bus (see 15. IIC Bus, page 44 for more information). The control and status signals for the SFP module are connected to jumpers and test points as described in Table 1-9. The SFP module connections are shown in Table 1-10, page 38. Table 1-9: SFP Module Control and Status
Board Connection Test Point J52 SFP_TX_FAULT High = Fault Low = Normal Operation Jumper J65 SFP_TX_DISABLE Off = SFP Disabled On = SFP Enabled Test Point J53 SFP_MOD_DETECT High = Module Not Present Low = Module Present Jumper J54 SFP_RT_SEL Jumper Pins 1-2 = Full Bandwidth Jumper Pins 2-3 = Reduced Bandwidth Test Point J51 SFP_LOS High = Loss of Receiver Signal Low = Normal Operation SFP Control/Status Signal

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Table 1-10:

SFP Module Connections

P4 SFP Module Connector Schematic Net Name Pin Number Pin Name RDP_13 RDN_12 TDP_18 TDN_19 LOS TX_DISABLE SFP_RX_P SFP_RX_N SFP_TX_P SFP_TX_N SFP_LOS SFP_TX_DISABLE(1) 13 12 18 19 8 3

U1 FPGA Pin E3 E4 C3 C4 V23 AP12

Notes:

1. The SFP TX Disable pin 3 is driven by transistor Q22, the base of which is driven by the FPGA signal SFP_TX_DISABLE_FPGA.

11. 10/100/1000 Tri-Speed Ethernet PHY

The ML605 utilizes the onboard Marvell Alaska PHY device (88E1111) for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports MII, GMII, RGMII, and SGMII interfaces from the FPGA to the PHY (Table 1-11). The PHY connection to a userprovided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector with built-in magnetics. Table 1-11: PHY Default Interface Mode
Jumper Settings Mode J66 GMII/MII to copper (default) SGMII to copper, no clock RGMII Jumper over pins 1-2 Jumper over pins 2-3 Jumper over pins 1-2 J67 Jumper over pins 1-2 Jumper over pins 2-3 No jumper J68 No jumper No jumper Jumper on

On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1-12. These settings can be overwritten via software commands passed over the MDIO interface. Table 1-12:
Pin CFG0 CFG1 CFG2 CFG3 CFG4

Board Connections for PHY Configuration Pins

Connection on Bit[2] Bit[1] Bit[0] Board Definition and Value Definition and Value Definition and Value VCC 2.5V Ground VCC 2.5V VCC 2.5V VCC 2.5V PHYADR[2] = 1 ENA_PAUSE = 0 ANEG[3] = 1 ANEG[0] = 1 HWCFG_MD[2] = 1 PHYADR[1] = 1 PHYADR[4] = 0 ANEG[2] = 1 ENA_XC = 1 HWCFG_MD[1] = 1 PHYADR[0] = 1 PHYADR[3] = 0 ANEG[1] = 1 DIS_125 = 1 HWCFG_MD[0] = 1

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Table 1-12:
Pin CFG5 CFG6

Board Connections for PHY Configuration Pins (Contd)

Connection on Bit[2] Bit[1] Bit[0] Board Definition and Value Definition and Value Definition and Value VCC 2.5V PHY_LED_RX DIS_FC = 1 SEL_BDT = 0 DIS_SLEEP = 1 INT_POL = 1 HWCFG_MD[3] = 1 75/50= 0

SGMII GTX Transceiver Clock Generation

An Integrated Circuit Systems ICS844021I chip generates a high-quality, low-jitter, 125MHz LVDS clock from an inexpensive 25-MHz crystal oscillator. This clock is sent to the GTX driving the SGMII interface. Series AC coupling capacitors are also present to allow the clock input of the FPGA to set the common mode voltage.
X-Ref Target - Figure 1-13

VDDA_SGMIICLK
C348 33PF 2 50V NPO

VDD_SGMIICLK ICS84402II VDDA GND XTAL_OUT XTAL_IN VDD Q0 NQ0 OE 8 7 6 5 SGMIICLK_QO_C_P SGMIICLK_QO_C_N
C55 1 0.1UF 10V 2 X5R C56 1 0.1UF 10V 2 X5R

1 2 X3 1 R132 DNP 1% 2 1/16W 25.000MHZ GND_SGMIICLK SGMIICLK_XTAL_OUT SGMIICLK_XTAL_IN 3 4

SGMIICLK_QO_P SGMIICLK_QO_N

C347 33PF 2 50V NPO

U82 125.00 MHz Clock

UG534_13_111709

Figure 1-13:

Ethernet SGMII Clock - 125 MHz

Table 1-13 shows the connections and pin numbers for the PHY. Table 1-13: Ethernet PHYConnections
U80 M88E1111 U1 FPGA Pin AN14 AP14 AH14 AH13 AL13 AK13 AP11 AG12 AM13 AN13 AF14 AE14 AN12 Schematic Net Name Pin Number PHY_MDIO PHY_MDC PHY_INT PHY_RESET PHY_CRS PHY_COL PHY_RXCLK PHY_RXER PHY_RXCTL_RXDV PHY_RXD0 PHY_RXD1 PHY_RXD2 PHY_RXD3 33 35 32 36 115 114 7 8 4 3 128 126 125 Pin Name MDIO MDC INT_B RESET_B CRS COL RXCLK RXER RXDV RXD0 RXD1 RXD2 RXD3

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Table 1-13:

Ethernet PHYConnections (Contd)

U80 M88E1111 Schematic Net Name Pin Number Pin Name RXD4 RXD5 RXD6 RXD7 GTXCLK TXCLK TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 SIN_P SIN_N SOUT_P SOUT_N PHY_RXD4 PHY_RXD5 PHY_RXD6 PHY_RXD7 PHY_TXC_GTXCLK PHY_TXCLK PHY_TXER PHY_TXCTL_TXEN PHY_TXD0 PHY_TXD1 PHY_TXD2 PHY_TXD3 PHY_TXD4 PHY_TXD5 PHY_TXD6 PHY_TXD7 SGMII_TX_P SGMII_TX_N SGMII_RX_P SGMII_RX_N 124 123 121 120 14 10 13 16 18 19 20 24 25 26 28 29 113 112 107 105

U1 FPGA Pin AM12 AD11 AC12 AC13 AH12 AD12 AH10 AJ10 AM11 AL11 AG10 AG11 AL10 AM10 AE11 AF11 A3 A4 B5 B6

References
See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information. [Ref 28] Also, see the LogiCORE IP Tri-Mode Ethernet MAC User Guide. [Ref 19]

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12. USB-to-UART Bridge

The ML605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U34) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to ML605 connector J21). Table 1-14 details the ML605 J21 pinout. Xilinx UART IP is expected to be implemented in the FPGA fabric (for instance, Xilinx XPS UART Lite. The FPGA supports the USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS). Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the CP2103GM USB-to-UART bridge to appear as a COM port to host computer communications application software (for example, HyperTerm or TeraTerm). The VCP device driver must be installed on the host PC prior to establishing communications with the ML605. Refer to the evaluation kit Getting Started Guide for driver installation instructions. Table 1-14: USB Type B Pin Assignments and Signal Definitions
Signal Name VBUS USB_DATA_N USB_DATA_P GROUND Description +5V from host system (not used) Bidirectional differential serial data (N-side) Bidirectional differential serial data (P-side) Signal ground USB Connector Pin 1 2 3 4

Table 1-15:

USB-to-UART Connections
UART function in FPGA RTS, output CTS, input TX, data out RX, data in Schematic Net Name USB_1_CTS USB_1_RTS USB_1_RX USB_1_TX U34 CP2103GM Pin 22 23 24 25 UART Function in CP2103GM CTS, input RTS, output RXD, data in TXD, data out

U1 FPGA Pin T24 T23 J25 J24

References
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers. In addition, see some of the Xilinx UART IP specifications at: http://www.xilinx.com/support/documentation/ip_documentation/xps_uartlite.pdf http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf

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13. USB Controller

The ML605 provides USB support via a Cypress CY7C67300 EZ-Host Programmable Embedded USB Host and Peripheral Controller (U81). The host port is a USB Type-A connector (J5). A USB keyboard (without an internal USB hub) will be able to connect to this USB Host port to demonstrate functionality. The peripheral port is a USB Type Mini-B (J20). Table 1-16:
U1 FPGA Pin
Y32 W26 W27 R33 R34 T30 T31 T29 V28 V27 U25 Y28 W32 W31 Y29 W29 Y34 Y33 Y31 Y27 W25 T25 V25

USB Controller Connections

U81 USB Controller Schematic Net Name Pin Number
52 50 49 94 93 92 91 90 89 87 86 66 65 61 60 59 58 57 56 46 47 85 48

Pin Name
GPIO19_A0_CS0_52 50_GPIO20_A1_CS1 49_GPIO21_CS_N GPIO0_D0_94 GPIO1_D1_93 GPIO2_D2_92 GPIO3_D3_91 GPIO4_D4_90 GPIO5_D5_89 GPIO6_D6_87 GPIO7_D7_86 GPIO8_D8_MISO_66 GPIO9_D9_nSSI_65 GPIO10_D10_SCK_61 GPIO11_D11_MOSI_60 GPIO12_D12_59 GPIO13_D13_58 GPIO14_D14_57 GPIO15_D15_SSI_N_56 46_GPIO24_INT_IORDY_IRQ0 47_GPIO23_RD_N_IOR RESET_N_85 48_GPIO22_WR_N_IOW

USB_A0_LS USB_A1_LS USB_CS_B_LS USB_D0_LS USB_D1_LS USB_D2_LS USB_D3_LS USB_D4_LS USB_D5_LS USB_D6_LS USB_D7_LS USB_D8_LS USB_D9_LS USB_D10_LS USB_D11_LS USB_D12_LS USB_D13_LS USB_D14_LS USB_D15_LS USB_INT_LS USB_RD_B_LS USB_RESET_B_LS USB_WR_B_LS

References
See the Cypress CY7C67300 Data Sheet for more information. [Ref 29] In addition, see the USB Specifications for more information. [Ref 30] The FPGA requires implementation of a peripheral controller in order to communicate with the Cypress USB device. See the XPS External Peripheral Controller (EPC) v1.02a Data Sheet for more information. [Ref 20]

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14. DVI Codec

The ML605 features a DVI connector (P3) to support an external video monitor. The DVI circuitry utilizes a Chrontel CH7301C (U38) capable of 1600 X 1200 resolution with 24-bit color. The video interface chip drives both the digital and analog signals to the DVI connector. A DVI monitor can be connected to the board directly. A VGA monitor can also be connected to the board using the supplied DVI-to-VGA adaptor. The Chrontel CH7301C is controlled by way of the video IIC bus. The DVI connector (Table 1-17) supports the IIC protocol to allow the board to read the monitor's configuration parameters. These parameters can be read by the FPGA using the DVI IIC bus (see 15. IIC Bus, page 44). Table 1-17: DVI Controller Connections
U38 Chrontel CH7301C U1 FPGA Pin Schematic Net Name Pin Number AJ19 AH19 AM17 AM16 AD17 AE17 AK18 AK17 AE18 AF18 AL16 AK16 AD16 AN17 AP17 AD15 AC17 AC18 No Connect No Connect DVI_D0 DVI_D1 DVI_D2 DVI_D3 DVI_D4 DVI_D5 DVI_D6 DVI_D7 DVI_D8 DVI_D9 DVI_D10 DVI_D11 DVI_DE DVI_H DVI_RESET_B_LS DVI_V DVI_XCLK_N DVI_XCLK_P DVI_GPIO0 DVI_GPIO1 63 62 61 60 59 58 55 54 53 52 51 50 2 4 13 5 56 57 8 7 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DE H RESET_B V XCLK_N XCLK_P GPIO0 GPIO1

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15. IIC Bus

The ML605 implements four IIC bus interfaces at the FPGA. The "MAIN" IIC bus hosts four items: FPGA U1 Bank 34 "MAIN" IIC interface 8Kb NV Memory U6 FMC HPC connector J64 DDR3 SODIMM Socket J1

The "DVI" IIC bus hosts two items: FPGA U1 Bank 34 "DVI" IIC interface DVI codec U38 and DVI connector J63

The "LPC" IIC bus hosts two items: FPGA U1 Bank 33 "LPC" IIC interface FMC LPC connector J63

The "SFP" IIC bus hosts two items: FPGA U1 Bank 13 "SFP" IIC interface SFP module connector P4

The ML605 IIC bus topology is shown in Figure 1-14.

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X-Ref Target - Figure 1-14

U1
IIC_SDA_MAIN_LS BANK 34
FPGA IIC INTERFACE

BANK 13 BANK 34

IIC_SCL_MAIN_LS IIC_SDA_SFP IIC_SCL_SFP IIC_SDA_DVI IIC_SCL_DVI FMC_LPC_IIC_SDA_LS

LEVEL SHIFTER

U6 ST MICRO M24C08-WDW6TP Addr: 0b1010100 through 0b1010111 J64 FMC HPC COLUMN C 2 Kb EEPROM on any FMC LPC Mezzanine Card Addr: 0b1010000 J1

BANK 33

FMC_LPC_IIC_SCL_LS

J63
FMC LPC COLUMN C 2 Kb EEPROM on any FMC LPC Mezzanine Card Addr: 0b1010001

LEVEL SHIFTER

LEVEL SHIFTER

LEVEL SHIFTER

FMC_LPC_IIC_SCL FMC_LPC_IIC_SDA

P3
DVI CONN Addr: 0b1010000

IIC_CLK_DVI_F IIC_SDA_DVI_F

U38
DVI CODEC CHRONTEL CH730C-TF Addr: 0b1110110

DDR3 SODIMM IIC_SCL_MAIN SOCKET Addr: 0b1010011 IIC_SDA_MAIN 2 Kb EEPROM Addr: 0b0011011 Temperature Sensor P4 SFP_MOD_DEF2 SFP MODULE CONNECTOR SFP_MOD_DEF1 Addr: 0b1010000
UG534_14_092109

Figure 1-14:

IIC Bus Topology

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8 Kb NV Memory
The ML605 hosts an 8 Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U6). The IIC address of U7 is 0b1010100, and U6 is not write protected (WP pin 7 is tied to GND). The IIC memory is shown in Figure 1-15.
X-Ref Target - Figure 1-15

VCC3V3

1 R414 5%

IIC SCL MAIN IIC SDA MAIN

R413 0 5% 1/16W

U6 6 SCL 5 SDA 1 A0 2 A1 3 A2

VCC3V3 WP 7

VCC3V3

1 2

8 VCC GND 4

C65 X5R 10V 0.1UF

R414 0 5% 1/16W

M24C08-WDW6TP 1 R305 DNP 1% 1/16W IIC Address = 0b1010100

UG534_15_072109

Figure 1-15: Table 1-18:

IIC Memory U6

IIC Memory Connections

IIC Memory U6 Schematic Net Name Pin Number Pin Name A0 A1 A2 SDA SCL WP Tied to GND Tied to GND Pulled up (0) to VCC3V3 IIC_SDA_MAIN IIC_SCL_MAIN Tied to GND 1 2 3 5 6 7

FPGA U1 Pin Not Applicable Not Applicable Not Applicable AE9 AK9 Not Applicable

References
See the ST Micro M24C08 Data Sheet for more information. [Ref 31] In addition, see the Xilinx XPS IIC Bus Interface (v2.00a) Data Sheet. [Ref 21]

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16. Status LEDs

Table 1-19 defines the status LEDs. Table 1-19:
Designator DS1 DS2 DS13 DS23

Status LEDs
Signal Name SYSACE_STAT_LED TI_PWRGOOD and MGT_TI_PWRGOOD FPGA_DONE LED_GRN LED_RED Color GREEN GREEN GREEN GREEN RED GREEN GREEN GREEN GREEN RED RED GREEN 12V AVCC GD MGT_AVTT DDR3 PWR GD System ACE CF Error LED INIT FMC PWR GD Label System ACE CF Status LED POWER GOOD DONE STATUS Description System ACE CF Status Both UCD9240 controllers report power good FPGA configured successfully USB JTAG Connection Status (Dual LED) 12V Power On MGT AVCC Power On MGT AVTT Power On DDR3 VTTDDR Power Good System ACE CF Error FPGA Initialization in progress FMC Power Good

DS25 DS27 DS28 DS29 DS30 DS31 DS32

12V MGT_AVCC MGT_AVTT DDR3_VTTDDR_PWRGOOD SYSACE_ERR_LED FPGA_INIT_B DVI_GPIO1_FMC_C2M_PG

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Ethernet PHY Status LEDs

The Ethernet PHY status LEDs are mounted to be visible when the ML605 board is installed into a PC motherboard. They are mounted in right-angle, plastic housings and can be seen on the connector end of the board. This cluster of six LEDs is installed adjacent to the RJ45 Ethernet jack P2.
X-Ref Target - Figure 1-16

Direction Indicator

Link Rate (Mbps)

DUP TX RX

10 100 1000

P2

End view of ML605 Ethernet jack and status LEDs when installed vertically in a PC chassis
UG534_16_101209

Figure 1-16:

Ethernet PHY Status LEDs

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FPGA INIT and DONE LEDs

The typical Xilinx FPGA power up and configuration status LEDs are present on the ML605. The red INIT LED DS31 comes on momentarily after the FPGA powers up and during its internal power-on process. The DONE LED DS13 comes on after the FPGA programming bitstream has been downloaded and the FPGA successfully configured.
X-Ref Target - Figure 1-17

VCC2V5
2

VCC2V5 1 Q14 R419 330 5% 1/16W

2 FPGA_DONE

FPGA INIT B

1 NDS336P
3

DS13
LED-RED-SMT

1 2

R3 27.4 1% 1/16W

1 2

UG534_17_050510

Figure 1-17: Table 1-20:

FPGA INIT and DONE LEDs

FPGA INIT and DONE LED Connections

Schematic Net Name FPGA_INIT_B FPGA_DONE Controlled LED DS31 INIT, Red DS13 DONE, Green

FPGA U1 Pin P8 R8

17. User I/O

The ML605 provides the following user and general purpose I/O capabilities: User LEDs (8) with parallel wired GPIO male pin header User Pushbutton (5) switches with associated direction LEDs CPU Reset pushbutton switch User DIP switch (8-pole) User SMA GPIO LCD Display (16 char x 2 lines)

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LED-GRN-SMT

DS31

R4 27.4 1% 1/16W

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User LEDs
The ML605 provides two groups of active-High LEDs as described in Figure 1-18 and Table 1-21.
X-Ref Target - Figure 1-18

J62
GPIO_LED_0 GPIO_LED_1 GPIO_LED_2 GPIO_LED_3 GPIO_LED_4 GPIO_LED_5 GPIO_LED_6 GPIO_LED_7 1 2 3 4 5 6 7 8

H-1X8

DS10

DS11

DS21

DS22

DS14

DS15

LED-GRN-SMT

LED-GRN-SMT

LED-GRN-SMT

LED-GRN-SMT

LED-GRN-SMT

LED-GRN-SMT

LED-GRN-SMT

DS12

DS9

1 2

R5 27.4 1% 1/16W

1 2

R6 27.4 1% 1/16W

1 2

R7 27.4 1% 1/16W

1 2

R8 27.4 1% 1/16W

1 2

R9 27.4 1% 1/16W

1 2

R10 27.4 1% 1/16W

1 2

R11 27.4 1% 1/16W

1 2

LED-GRN-SMT

R12 27.4 1% 1/16W

GPIO_LED_C GPIO_LED_W GPIO_LED_E GPIO_LED_S GPIO_LED_N

LED-GRN-SMT

LED-GRN-SMT

LED-GRN-SMT

LED-GRN-SMT

GPIO_LED_W_R

GPIO_LED_N_R

1 R13 2

1 R14

1 R15

1 R16

GPIO_LED_C_R

GPIO_LED_S_R

GPIO_LED_E_R

27.4 1% 1/16W 2

27.4 1% 1/16W 2

27.4 1% 1/16W 2

27.4 1% 1/16W 2

UG534_18_081109

Figure 1-18:

User LEDs and GPIO Connector, Directional LEDs

Note: See User Pushbutton Switches, page 51 for more details about the LEDs.

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LED-GRN-SMT

This group of LEDs is mounted adjacent to their respective direction pushbuttons, as seen on the right side of the LCD on the board photo (Figure 1-2).

DS20

DS18

DS19

DS17

DS16
1

R17 27.4 1% 1/16W

Detailed Description

Table 1-21:

User LED Connections

Controlled LED DS12 DS11 DS9 DS10 DS15 DS14 DS22 DS21 DS16 DS17 DS19 DS18 DS20

FPGA U1 Pin Schematic Net Name GPIO J62 Pin AC22 AC24 AE22 AE23 AB23 AG23 AE24 AD24 AP24 AD21 AE21 AH28 AH27 GPIO_LED_0 GPIO_LED_1 GPIO_LED_2 GPIO_LED_3 GPIO_LED_4 GPIO_LED_5 GPIO_LED_6 GPIO_LED_7 GPIO_LED_C GPIO_LED_W GPIO_LED_E GPIO_LED_S GPIO_LED_N 1 2 3 4 5 6 7 8

User Pushbutton Switches

The ML605 provides six active-High pushbutton switches: SW5, SW6, SW7, SW8 and SW9, arranged in a diamond configuration to depict directional headings North, South, East, West and Center respectively SW10 CPU Reset pushbutton

The six pushbuttons all have the same active-High topology as the sample shown in Figure 1-19. The five directional pushbuttons are assigned as GPIO and the sixth is assigned as CPU_RESET. Figure 1-19 and Table 1-22, page 52 describe the pushbutton switches.
X-Ref Target - Figure 1-19

VCC1V5

Pushbutton 1 2 P1 P2 sw10
UG534_19_072109

P4 P3

4 3 4.7K R401

CPU RESET

5% 1/16W

Figure 1-19:

User Pushbutton Switch (Typical)

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Table 1-22:

User Pushbutton Switch Connections

Schematic Net Name
GPIO_SW_N GPIO_SW_S GPIO_SW_E GPIO_SW_W GPIO_SW_C CPU_RESET

U1 FPGA Pin
A19 A18 G17 H17 G26 H10

Pushbutton Switch Pin

SW5.2 SW6.2 SW7.2 SW8.2 SW9.2 SW10.2

User DIP Switch

The ML605 includes an active-High eight pole DIP switch as described in Figure 1-20 and Table 1-23.
X-Ref Target - Figure 1-20

VCC1V5 SW1 GPIO DIP SW1 GPIO DIP SW2 GPIO DIP SW3 GPIO DIP SW4 GPIO DIP SW5 GPIO DIP SW6 GPIO DIP SW7 GPIO DIP SW8
10 8 9 2 4.7K 5% 1 RP7 3 4.7K 5% 1 RP7 4 4.7K 5% 5 1 RP7 7 5% 5% 5% 5% 5%

1 2 3 4 5 6 7 8 SDMX-8-X

16 15 14 13 12 11 10 9

RP7 6 4.7K RP7 6 4.7K RP7 6 4.7K RP7 6 4.7K 1 RP7

4.7K

UG534_20_072109

Figure 1-20: Table 1-23:

User 8-pole DIP Switch

User DIP Switch Connections

Schematic Net Name
GPIO_DIP_SW1 GPIO_DIP_SW2 GPIO_DIP_SW3 GPIO_DIP_SW4 GPIO_DIP_SW5 GPIO_DIP_SW6 GPIO_DIP_SW7 GPIO_DIP_SW8

U1 FPGA Pin
D22 C22 L21 L20 C18 B18 K22 K21

DIP Switch Pin

SW1.1 SW1.2 SW1.3 SW1.4 SW1.5 SW1.6 SW1.7 SW1.8

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User SMA GPIO

The ML605 includes an pair of SMA connectors for GPIO as described in Figure 1-21 and Table 1-24.
X-Ref Target - Figure 1-21

USER SMA GPIO N USER SMA GPIO P

J56 32K10K-400E3 2 GND1 3 GND2 4 GND3 1 5 SIG GND4 6 GND5 7 GND6 8 GND7 J76 32K10K-400E3 2 GND1 3 GND2 4 GND3 1 5 SIG GND4 6 GND5 7 GND6 8 GND7

UG534_21_072109

Figure 1-21: User SMA GPIO Table 1-24: User SMA Connections
Schematic Net Name USER_SMA_GPIO_N USER_SMA_GPIO_P SMA Pin J56.1 J57.1

U1 FPGA Pin W34 V34

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LCD Display (16 Character x 2 Lines)

The ML605 board has a 16-character x 2-line LCD (Display Tech S162D BA BC, installed onto J41 2x7 header) on the board to display text information. Potentiometer R270 adjusts the contrast of the LCD. A ST2378E (U33) 2.5V-to-5V level-shifter is used to shift the voltage level between the FPGA and the LCD. The data interface to the LCD is connected to the FPGA to support 4-bit mode only. The LCD module has a connector that allows the LCD to be removed from the board to access to the components below it. Caution! Care should be taken not to scratch or damage the surface of the LCD window.
X-Ref Target - Figure 1-22

VCC5 VCC5 J41 R158

LCD_DB7 LCD_DB5 NC NC LCD_E LCD_RS

1 3 5 7 9 11 13

2 4 6 8 10 12 14

LCD_DB6 LCD_DB4 NC NC LCD_RW LCD_VEE

32 32
1

6.81K

2
1% R270 0-2K 1/2W 20% silkscreen: LCD Contrast
UG534_22_073109

32
2

SSW-107-01-T-D

Figure 1-22:

LCD Header J41 and Contrast Trimpot R270

Table 1-25:

LCD Header Connections

Schematic Net Name LCD_DB4_LS LCD_DB5_LS LCD_DB6_LS LCD_DB7_LS LCD_RW_LS LCD_RS_LS LCD_E_LS J41 Pin 4 3 2 1 10 11 9

U1 FPGA Pin AD14 AK11 AJ11 AE12 AC14 T28 AK12

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18. Switches
The ML605 Evaluation board includes the following switches: Power On/Off Slide Switch SW2 FPGA_PROG_B SW4 (active-Low) SYSACE_RESET_B SW3 (active-Low) System ACE CF CompactFlash Image Select DIP Switch S1 (active-High) MODE, Boot EEPROM Select and CCLK Osc Enable DIP switch S2 (active-High)

Power On/Off Slide Switch SW2

SW2 is the ML605 board main power on/off switch. Sliding the switch actuator from the off to on position applies 12V power from either J60 (6-pin Mini-Fit) or J25 (4-pin ATX) power connector to the VCC12_P power plane via the 1m 1% 3W series current sense resistor R346. See 22. System Monitor, page 71 for further details on 12V input current sensing. Green LED DS25 will illuminate when the ML605 board power is on. See section 21. Power Management, page 67 for details on the onboard power system.
X-Ref Target - Figure 1-23

VCC12_P

J60 12v 12v N/C N/C COM COM 39-30-1060 1 4 2 5 3 6 VCC12_P_IN

2

DPDT
1 3 4 NC NC

R346 I1 I1 I2 I2 1 E1 E2 E1 E2 3W 0.001R 0.5% Y14880R00100B09R

LED-GRN-SMT
R322 1.00K 1% 1/16W

NC NC

1 2

C280 330UF 16V ELEC

5 6

2 2

SW2 1201M2S3ABE2

DS25 1

PCIe Power
ATX Peripheral Cable Connector can plug into J25 when ML605 is in PC and the desk top AC adapter (brick) is not used. J25 12V COM COM 5V 350211-1 1 2 3 4 NC

CAUTION!
DO NOT plug a PC ATX power supply 6-pin connector into the J60 connector on the ML605 board. The ATX 6-pin connector has a different pinout than J60 and will damage the ML605 board and void the board warranty. DO NOT plug an auxilliary PCIe 6-pin molex power connector into the J60 connector as this could damage the PCIe motherboard and/or the ML605 board. J60 is marked with a NO PCIE POWER label to warn users of the potential hazard. DO NOT apply power to J60 and the 4-pin ATX disk drive connector J25 at the same time as this will damage the ML605 board.
UG534_23 _081209

Figure 1-23:

Power On/Off Slide Switch SW2

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FPGA_PROG_B Pushbutton SW4 (Active-Low)

This switch grounds the FPGA's PROG_B pin when pressed. This action clears the FPGA. See the Virtex-6 FPGA Data Sheet for more information on clearing the contents of the FPGA. [Ref 4]
X-Ref Target - Figure 1-24

VCC2V5

RP4 1

5%

4.7K FPGA PROG Pushbutton 1 2

FPGA_PROG_B

P1 P2 SW4

P4 P3

4 3

Silkscreen: PROG
UG534_24_073109

Figure 1-24:

FPGA PROG_B Pushbutton SW4

SYSACE_RESET_B Pushbutton SW3 (Active-Low)

When the System ACE CF configuration mode pin is high (enabled by closing DIP switch S1 switch 4), the System ACE CF controller configures the FPGA from the CompactFlash card when a card is inserted or the SYSACE RESET button is pressed. See 5. System ACE CF and CompactFlash Connector, page 26 for more details.
X-Ref Target - Figure 1-25

SYSACE_RESET_B 1 2

silkscreen: SYSACE RESET Pushbutton P1 P2 SW3 P4 P3 4 3

UG534_25_073109

Figure 1-25: System ACE CF RESET_B Pushbutton SW3

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System ACE CF CompactFlash Image Select DIP Switch S1

System ACE CF CompactFlash (CF) image select DIP switch S1, switches 13, select which CF resident bitstream image is downloaded to the FPGA (Figure 1-26). S1 switches 13 offer eight binary addresses. When ON (High), the S1 switch 4 enables the System ACE CF controller to configure the FPGA from the CF card when a card is inserted or when the SYSACE RESET button is pressed. See 5. System ACE CF and CompactFlash Connector, page 26 for more details about the System ACE controller.
X-Ref Target - Figure 1-26

VCC2V5

1/16W

1/16W

1 510

1 510 510

1/16W

1/16W 1 510 2 5%

2 5%

2 5% 5%

R62

R63

R64

R55

S1
1 2 3 4

SDMX-4-X
1.00K

ON

5 6 7 8

4 3 2 1
2 1% 1.00K 1/16W 2 1% 1.00K 1/16W 2 1% 1.00K 1/16W 2

SYSACE_CFGMODEPIN SYSACE_CFGADDR2 SYSACE_CFGADDR1 SYSACE_CFGADDR0

R61

R60

R59

R58

1% 1/16W

UG534_26_110409

Figure 1-26:

System ACE CF CompactFlash Image Select DIP Switch S1

Note: S1 switch 4 is the System ACE controller enable switch. When ON, this switch allows the
System ACE to boot at power-on if it finds a CF card present. In order to boot from BPI Flash U4 or Xilinx Platform Flash (U27) without System ACE contention, S1 switch 4 must be OFF.

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Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2
DIP switch S2 is a multi-purpose selector switch (Figure 1-27 and Table 1-27, page 59). FPGA Mode: S2 switches 3, 4, and 5 control the FPGA mode (Table 1-26). Oscillator Enable: S2 switch 1, CCLK_EXTERNAL, controls the enable pin of the 47 MHz oscillator SiT8102 (X4). When switch 1 is closed (CCLK_EXTERNAL High), X4 drives a 47 MHz clock onto the FPGA_CCLK signal. Boot EEPROM Select: S2 switch 2 is used to select the between the Xilinx Platform Flash or the Numonyx Linear BPI Flash for the FPGA boot memory device. Upper or Lower Address Select: S2 switch 6 is used to select the upper or lower half of flash memory U4 as the source of the FPGA bitstream image. When FLASH_A23 is High, the upper half of the address is selected. When FLASH_A23 is Low, the lower half of the address is selected.
X-Ref Target - Figure 1-27

VCC2V5

1/16W

1/16W

1 510

1 510 510

1/16W

2 5% 5%

2 5% 5%

1/16W

R51

R52

R57

S2 7 8 9 10 11 12 6 5 4 3 2 1
R56 R55 R54 R53 R50 R43 FLASH_A23 FPGA_M2 FPGA_M1 FPGA_M0 P30_CS_SEL CCLK EXTERNAL
4.7K 4.7K 4.7K 4.7K 4.7K 1 1 2 1/16w 5% 2 5% 1/16w 5% 4.7K

ON

SDMX-6-X

1 2 3 4

5 6

2 1/16w 5%

2 1/16w 5%

2 1/16w 5%

2 1/16w

UG534_27_110409

Figure 1-27:

Multi-Purpose Select DIP Switch S2

Table 1-26 shows the FPGA configuration modes controlled by S2 switches 3, 4, and 5. Table 1-26: ML605 Configuration Modes
M[2:0] 010 101 110 Bus Width 8, 16 1 8, 16, 32 CCLK Output Input (TCK) Input Configuration Mode Master BPI-Up JTAG Slave SelectMAP

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Table 1-27:

Switch S2 Configuration Details

Switch Configuration Mode/Method JTAG System ACE CF Off On(1) On Off On Off Slave SelectMAP Platform Flash XL On Off Off On On Don't Care Master BPI P30 Linear Flash Off On Off On Off Off(2)

Switch S2.1 S2.2 S2.3 S2.4 S2.5 S2.6

Notes:

Net Name CCLK_EXTERNAL P30_CS_SEL FPGA_M0 FPGA_M1 FPGA_M2 FLASH_A23

1. In JTAG mode, S2.2 is shown as ON for FPGA access to the P30 Linear Flash. Alternatively, set S2.2 to OFF for FPGA access to the Platform Flash XL. 2. In Master BPI mode, S2.6 is shown as OFF for selecting initial configuration from BPI address 0x000000. Alternatively, set S2.6 to ON to select initial configuration from BPI address 0x800000.

See 3. 128 Mb Platform Flash XL, page 22 and 4. 32 MB Linear BPI Flash, page 22 for details.

19. VITA 57.1 FMC HPC Connector

The ML605 implements both the High Pin Count (HPC, J64) and Low Pin Count (LPC, J63) connector options of VITA 57.1.1 FMC specification. This section discusses the FMC HPC J64 connector. Note: The FMC HPC J64 connector is a keyed connector oriented so that a plug-on card faces away
from the ML605 board.

The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector form factor is used for both versions. The HPC version is fully populated with 400 pins present, and the LPC version is partially populated with 160 pins. The 10 x 40 rows of a FMC HPC connector provides connectivity for: 160 single-ended or 80 differential user-defined signals 10 MGTs 2 MGT clocks 4 differential clocks 159 ground, 15 power connections

Of the above signal and clock connectivity capability, the ML605 implements the following subset: 78 differential user defined pairs: 34 LA pairs 24 HA pairs 20 HB pairs

8 MGTs

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2 MGT clocks 4 differential clocks

Note: The ML605 board VADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed
at 2.5V (non-adjustable). The 2.5V rail cannot be turned off. The ML605 VITA 57.1 FMC interfaces are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.

Table 1-28 shows the VITA 57.1 FMC HPC connections. The connector pinout is in Appendix C, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout. Any signal named FMC_HPC_xxxx that is wired between a U1 FPGA pin and some other device does not appear in this table. Table 1-28:
J64 FMC HPC Pin A2 A3 A6 A7 A10 A11 A14 A15 A18 A19 A22 A23 A26 A27 A30 A31 A34 A35 A38 A39

VITA 57.1 FMC HPC Connections

Schematic Net Name FMC_HPC_DP1_M2C_P FMC_HPC_DP1_M2C_N FMC_HPC_DP2_M2C_P FMC_HPC_DP2_M2C_N FMC_HPC_DP3_M2C_P FMC_HPC_DP3_M2C_N FMC_HPC_DP4_M2C_P FMC_HPC_DP4_M2C_N FMC_HPC_DP5_M2C_P FMC_HPC_DP5_M2C_N FMC_HPC_DP1_C2M_P FMC_HPC_DP1_C2M_N FMC_HPC_DP2_C2M_P FMC_HPC_DP2_C2M_N FMC_HPC_DP3_C2M_P FMC_HPC_DP3_C2M_N FMC_HPC_DP4_C2M_P FMC_HPC_DP4_C2M_N FMC_HPC_DP5_C2M_P FMC_HPC_DP5_C2M_N U1 FPGA Pin AE3 AE4 AF5 AF6 AG3 AG4 AJ3 AJ4 AL3 AL4 AD1 AD2 AF1 AF2 AH1 AH2 AK1 AK2 AM1 AM2 J64 FMC HPC Pin B12 B13 B16 B17 B20 B21 B32 B33 B36 B37 Schematic Net Name FMC_HPC_DP7_M2C_P FMC_HPC_DP7_M2C_N FMC_HPC_DP6_M2C_P FMC_HPC_DP6_M2C_N FMC_HPC_GBTCLK1_M2C_P FMC_HPC_GBTCLK1_M2C_N FMC_HPC_DP7_C2M_P FMC_HPC_DP7_C2M_N FMC_HPC_DP6_C2M_P FMC_HPC_DP6_C2M_N U1 FPGA Pin AP5 AP6 AM5 AM6 AK6 AK5 AP1 AP2 AN3 AN4

C2 C3 C6 C7

FMC_HPC_DP0_C2M_P FMC_HPC_DP0_C2M_N FMC_HPC_DP0_M2C_P FMC_HPC_DP0_M2C_N

AB1 AB2 AC3 AC4

D4 D5 D8 D9

FMC_HPC_GBTCLK0_M2C_P FMC_HPC_GBTCLK0_M2C_N FMC_HPC_LA01_CC_P FMC_HPC_LA01_CC_N

AD6 AD5 AK19 AL19

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Table 1-28:
J64 FMC HPC Pin C10 C11 C14 C15 C18 C19 C22 C23 C26 C27 C30 C31

VITA 57.1 FMC HPC Connections (Contd)

Schematic Net Name FMC_HPC_LA06_P FMC_HPC_LA06_N FMC_HPC_LA10_P FMC_HPC_LA10_N FMC_HPC_LA14_P FMC_HPC_LA14_N FMC_HPC_LA18_CC_P FMC_HPC_LA18_CC_N FMC_HPC_LA27_P FMC_HPC_LA27_N IIC_SCL_MAIN_LS(1) IIC_SDA_MAIN_LS(1) U1 FPGA Pin AG20 AG21 AM20 AL20 AN19 AN20 AH25 AJ25 AP30 AP31 AK9 AE9 J64 FMC HPC Pin D11 D12 D14 D15 D17 D18 D20 D21 D23 D24 D26 D27 D29 D30 D31 D33 Schematic Net Name FMC_HPC_LA05_P FMC_HPC_LA05_N FMC_HPC_LA09_P FMC_HPC_LA09_N FMC_HPC_LA13_P FMC_HPC_LA13_N FMC_HPC_LA17_CC_P FMC_HPC_LA17_CC_N FMC_HPC_LA23_P FMC_HPC_LA23_N FMC_HPC_LA26_P FMC_HPC_LA26_N FMC_HPC_TCK_BUF(2) FMC_TDI_BUF(2) FMC_HPC_TDO(2) FMC_TMS_BUF(2) U1 FPGA Pin AG22 AH22 AM18 AL18 AP19 AN18 AN27 AM27 AL26 AM26 AM25 AL25 U88.15 J17.1 J17.3 U88.17

E2 E3 E6 E7 E9 E10 E12 E13 E15 E16 E18 E19 E21 E22 E24

FMC_HPC_HA01_CC_P FMC_HPC_HA01_CC_N FMC_HPC_HA05_P FMC_HPC_HA05_N FMC_HPC_HA09_P FMC_HPC_HA09_N FMC_HPC_HA13_P FMC_HPC_HA13_N FMC_HPC_HA16_P FMC_HPC_HA16_N FMC_HPC_HA20_P FMC_HPC_HA20_N FMC_HPC_HB03_P FMC_HPC_HB03_N FMC_HPC_HB05_P

AD29 AC29 AB27 AC27 AB30 AB31 AE31 AD31 AC33 AB33 V32 V33 AL30 AM31 AN33

F1 F4 F5 F7 F8 F10 F11 F13 F14 F16 F17 F19 F20 F22 F23

FMC_HPC_PG_M2C_LS(1) FMC_HPC_HA00_CC_P FMC_HPC_HA00_CC_N FMC_HPC_HA04_P FMC_HPC_HA04_N FMC_HPC_HA08_P FMC_HPC_HA08_N FMC_HPC_HA12_P FMC_HPC_HA12_N FMC_HPC_HA15_P FMC_HPC_HA15_N FMC_HPC_HA19_P FMC_HPC_HA19_N FMC_HPC_HB02_P FMC_HPC_HB02_N

J27 AE33 AF33 AB28 AC28 AG31 AF31 AD32 AE32 AB32 AC32 U33 U32 AP32 AP33

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Table 1-28:
J64 FMC HPC Pin E25 E27 E28 E30 E31 E33 E34

VITA 57.1 FMC HPC Connections (Contd)

Schematic Net Name FMC_HPC_HB05_N FMC_HPC_HB09_P FMC_HPC_HB09_N FMC_HPC_HB13_P FMC_HPC_HB13_N FMC_HPC_HB19_P FMC_HPC_HB19_N U1 FPGA Pin AN34 AL34 AK34 AH33 AH32 AL31 AK31 J64 FMC HPC Pin F25 F26 F28 F29 F31 F32 F34 F35 Schematic Net Name FMC_HPC_HB04_P FMC_HPC_HB04_N FMC_HPC_HB08_P FMC_HPC_HB08_N FMC_HPC_HB12_P FMC_HPC_HB12_N FMC_HPC_HB16_P FMC_HPC_HB16_N U1 FPGA Pin AM33 AL33 AK33 AK32 AJ31 AJ32 AH29 AH30

G2 G3 G6 G7 G9 G10 G12 G13 G15 G16 G18 G19 G21 G22 G24 G25 G27 G28 G30 G31 G33 G34 G36

FMC_HPC_CLK1_M2C_P FMC_HPC_CLK1_M2C_N FMC_HPC_LA00_CC_P FMC_HPC_LA00_CC_N FMC_HPC_LA03_P FMC_HPC_LA03_N FMC_HPC_LA08_P FMC_HPC_LA08_N FMC_HPC_LA12_P FMC_HPC_LA12_N FMC_HPC_LA16_P FMC_HPC_LA16_N FMC_HPC_LA20_P FMC_HPC_LA20_N FMC_HPC_LA22_P FMC_HPC_LA22_N FMC_HPC_LA25_P FMC_HPC_LA25_N FMC_HPC_LA29_P FMC_HPC_LA29_N FMC_HPC_LA31_P FMC_HPC_LA31_N FMC_HPC_LA33_P

AP20 AP21 AF20 AF21 AC19 AD19 AK22 AJ22 AM21 AL21 AP22 AN23 AK23 AL24 AP27 AP26 AN28 AM28 AL28 AK28 AL29 AK29 AH23

H2 H4 H5 H7 H8 H10 H11 H13 H14 H16 H17 H19 H20 H22 H23 H25 H26 H28 H29 H31 H32 H34 H35

FMC_HPC_PRSNT_M2C_L(1) FMC_HPC_CLK0_M2C_P FMC_HPC_CLK0_M2C_N FMC_HPC_LA02_P FMC_HPC_LA02_N FMC_HPC_LA04_P FMC_HPC_LA04_N FMC_HPC_LA07_P FMC_HPC_LA07_N FMC_HPC_LA11_P FMC_HPC_LA11_N FMC_HPC_LA15_P FMC_HPC_LA15_N FMC_HPC_LA19_P FMC_HPC_LA19_N FMC_HPC_LA21_P FMC_HPC_LA21_N FMC_HPC_LA24_P FMC_HPC_LA24_N FMC_HPC_LA28_P FMC_HPC_LA28_N FMC_HPC_LA30_P FMC_HPC_LA30_N

AP25 K24 K23 AC20 AD20 AF19 AE19 AK21 AJ21 AM22 AN22 AM23 AL23 AN25 AN24 AN29 AP29 AN30 AM30 AK27 AJ27 AJ24 AK24

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Table 1-28:
J64 FMC HPC Pin G37

VITA 57.1 FMC HPC Connections (Contd)

Schematic Net Name FMC_HPC_LA33_N U1 FPGA Pin AH24 J64 FMC HPC Pin H37 H38 Schematic Net Name FMC_HPC_LA32_P FMC_HPC_LA32_N U1 FPGA Pin AG25 AG26

J2 J3 J6 J7 J9 J10 J12 J13 J15 J16 J18 J19 J21 J22 J24 J25 J27 J28 J30 J31 J33 J34 J36 J37
Notes:

FMC_HPC_CLK3_M2C_P(2) FMC_HPC_CLK3_M2C_N(2) FMC_HPC_HA03_P FMC_HPC_HA03_N FMC_HPC_HA07_P FMC_HPC_HA07_N FMC_HPC_HA11_P FMC_HPC_HA11_N FMC_HPC_HA14_P FMC_HPC_HA14_N FMC_HPC_HA18_P FMC_HPC_HA18_N FMC_HPC_HA22_P FMC_HPC_HA22_N FMC_HPC_HB01_P FMC_HPC_HB01_N FMC_HPC_HB07_P FMC_HPC_HB07_N FMC_HPC_HB11_P FMC_HPC_HB11_N FMC_HPC_HB15_P FMC_HPC_HB15_N FMC_HPC_HB18_P FMC_HPC_HB18_N

U84.6 U84.7 AA25 Y26 AA26 AB26 AG33 AG32 AA30 AA31 T33 T34 U28 V29 AN32 AM32 AJ34 AH34 AJ29 AJ30 AE28 AE29 AD25 AD26

K4 K5 K7 K8 K10 K11 K13 K14 K16 K17 K19 K20 K22 K23 K25 K26 K28 K29 K31 K32 K34 K35 K37 K38

FMC_HPC_CLK2_M2C_P(2) FMC_HPC_CLK2_M2C_N(2) FMC_HPC_HA02_P FMC_HPC_HA02_N FMC_HPC_HA06_P FMC_HPC_HA06_N FMC_HPC_HA10_P FMC_HPC_HA10_N FMC_HPC_HA17_CC_P FMC_HPC_HA17_CC_N FMC_HPC_HA21_P FMC_HPC_HA21_N FMC_HPC_HA23_P FMC_HPC_HA23_N FMC_HPC_HB00_CC_P FMC_HPC_HB00_CC_N FMC_HPC_HB06_CC_P FMC_HPC_HB06_CC_N FMC_HPC_HB10_P FMC_HPC_HB10_N FMC_HPC_HB14_P FMC_HPC_HB14_N FMC_HPC_HB17_CC_P FMC_HPC_HB17_CC_N

U83.6 U83.7 AB25 AC25 AA28 AA29 AD34 AC34 V30 W30 U31 U30 U26 U27 AF30 AG30 AF26 AE26 AF28 AF29 AE27 AD27 AG27 AG28

1. Signals ending with _LS are not directly connected to the FMC HPC connector. _LS signals are connected between the listed U1 FPGA pin and a level shifter device. The signal connected between the shifted side of said device and the FMC HPC pin listed has the same signal name, without the _LS on the end. 2. These signals do not connect to U1 FPGA pins. The pin numbers in the right-hand column identify the device and pin these signals are connected to (U88.17 = U88 pin 17, and so on).

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Table 1-29:

Power Supply Voltages for HPC Connector

Allowable Voltage Range Fixed 2.5V 0-VADJ 0-VADJ 0-VIO_B_M2C 3.3V 3.3V 12V No Pins Max Amps Tolerance 4 2 1 1 1 4 2 4 1.15 1 mA 1 mA 20 mA 3 1 +/- 5% +/- 5% +/- 2% +/- 2% +/- 5% +/- 5% +/- 5% Max Capacitive Load 1000 uF 500 uF 10 uF 10 uF 150 uF 1000 uF 1000 uF

Voltage Supply VADJ VIO_B_M2C VREF_A_M2C VREF_B_M2C 3P3VAUX 3P3V 12P0V

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20. VITA 57.1 FMC LPC Connector

The ML605 implements both the High Pin Count (HPC, J64) and Low Pin Count (LPC, J63) connector options of VITA 57.1.1 FMC specification. This section discusses the FMC LPC J63 connector. Note: The FMC LPC J63 connector is a keyed connector oriented so that a plug-on card faces away
from the ML605 board.

The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector form factor is used for both versions. The HPC version is fully populated with 400 pins present, and the LPC version is partially populated with 160 pins. The 10 x 40 rows of a FMC LPC connector provides connectivity for: 68 single-ended or 34 differential user defined signals 1 MGT 1 MGT clock 2 differential clocks 61 ground, 10 power connections

Of the above signal and clock connectivity capability, the ML605 implements the full set: 34 differential user-defined pairs: 34 LA pairs 1 MGT 1 MGT clock 2 differential clocks

Signaling Speed Ratings: Single-ended: 9 GHz / 18 Gb/s Differential Optimal Vertical: 9 GHz / 18 Gb/s Optimal Horizontal: 16 GHz / 32 Gb/s High Density Vertical 7 GHz / 15 Gb/s

Mechanical specifications: Samtec SEAM/SEAF Series 1.27mm x 1.27mm (0.050" x 0.050") pitch

The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on a -3 dB insertion loss point within a two-level signaling environment. Note: The ML605 board VADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed
at 2.5V (non-adjustable). The 2.5V rail cannot be turned off. The ML605 VITA 57.1 FMC interfaces are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.

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Table 1-30 shows the VITA 57.1 FMC LPC connections. The connector pinout is in Appendix C, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout. Any signal named FMC_LPC_xxxx that is wired between a U1 FPGA pin and some other device does not appear in this table. Table 1-30:
J63 FMC LPC Pin C2 C3 C6 C7 C10 C11 C14 C15 C18 C19 C22 C23 C26 C27

VITA 57.1 FMC LPC Connections

Schematic Net Name FMC_LPC_DP0_C2M_P FMC_LPC_DP0_C2M_N FMC_LPC_DP0_M2C_P FMC_LPC_DP0_M2C_N FMC_LPC_LA06_P FMC_LPC_LA06_N FMC_LPC_LA10_P FMC_LPC_LA10_N FMC_LPC_LA14_P FMC_LPC_LA14_N FMC_LPC_LA18_CC_P FMC_LPC_LA18_CC_N FMC_LPC_LA27_P FMC_LPC_LA27_N U1 FPGA Pin D1 D2 G3 G4 K33 J34 F30 G30 C33 B34 L29 L30 R31 R32 J63 FMC LPC Pin D4 D5 D8 D9 D11 D12 D14 D15 D17 D18 D20 D21 D23 D24 D26 D27 Schematic Net Name FMC_LPC_GBTCLK0_M2C_P FMC_LPC_GBTCLK0_M2C_N FMC_LPC_LA01_CC_P FMC_LPC_LA01_CC_N FMC_LPC_LA05_P FMC_LPC_LA05_N FMC_LPC_LA09_P FMC_LPC_LA09_N FMC_LPC_LA13_P FMC_LPC_LA13_N FMC_LPC_LA17_CC_P FMC_LPC_LA17_CC_N FMC_LPC_LA23_P FMC_LPC_LA23_N FMC_LPC_LA26_P FMC_LPC_LA26_N U1 FPGA Pin M6 M5 F31 E31 H34 H33 L25 L26 D34 C34 N28 N29 R28 R27 L33 M32

G2 G3 G6 G7 G9 G10 G12 G13 G15 G16 G18 G19

FMC_LPC_CLK1_M2C_P FMC_LPC_CLK1_M2C_N FMC_LPC_LA00_CC_P FMC_LPC_LA00_CC_N FMC_LPC_LA03_P FMC_LPC_LA03_N FMC_LPC_LA08_P FMC_LPC_LA08_N FMC_LPC_LA12_P FMC_LPC_LA12_N FMC_LPC_LA16_P FMC_LPC_LA16_N

F33 G33 K26 K27 J31 J32 J30 K29 E32 E33 A33 B33

H2 H4 H5 H7 H8 H10 H11 H13 H14 H16 H17 H19

FMC_LPC_PRSNT_M2C_L FMC_LPC_CLK0_M2C_P FMC_LPC_CLK0_M2C_N FMC_LPC_LA02_P FMC_LPC_LA02_N FMC_LPC_LA04_P FMC_LPC_LA04_N FMC_LPC_LA07_P FMC_LPC_LA07_N FMC_LPC_LA11_P FMC_LPC_LA11_N FMC_LPC_LA15_P

AD9 A10 B10 G31 H30 K28 J29 G32 H32 D31 D32 C32

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Table 1-30:
J63 FMC LPC Pin G21 G22 G24 G25 G27 G28 G30 G31 G33 G34 G36 G37

VITA 57.1 FMC LPC Connections (Contd)

Schematic Net Name FMC_LPC_LA20_P FMC_LPC_LA20_N FMC_LPC_LA22_P FMC_LPC_LA22_N FMC_LPC_LA25_P FMC_LPC_LA25_N FMC_LPC_LA29_P FMC_LPC_LA29_N FMC_LPC_LA31_P FMC_LPC_LA31_N FMC_LPC_LA33_P FMC_LPC_LA33_N U1 FPGA Pin P29 R29 N27 P27 P31 P30 N34 P34 M31 L31 K32 K31 J63 FMC LPC Pin H20 H22 H23 H25 H26 H28 H29 H31 H32 H34 H35 H37 H38 Schematic Net Name FMC_LPC_LA15_N FMC_LPC_LA19_P FMC_LPC_LA19_N FMC_LPC_LA21_P FMC_LPC_LA21_N FMC_LPC_LA24_P FMC_LPC_LA24_N FMC_LPC_LA28_P FMC_LPC_LA28_N FMC_LPC_LA30_P FMC_LPC_LA30_N FMC_LPC_LA32_P FMC_LPC_LA32_N U1 FPGA Pin B32 M30 N30 R26 T26 N32 P32 N33 M33 M26 M27 N25 M25

References
See the data sheet for the ROHS compliant FMC HPC Samtec SEARAY connector (carrier side socket ASP-134486-01; module side plug ASP-134488-01), and the high-speed characterization report for this connector system on the Samtec website. [Ref 32]

21. Power Management

AC Adapter and Input Power Jack/Switch
The ML605 is powered from a 12V source that is connected through a 6-pin (2X3) rightangle Mini-Fit type connector J60. The AC-to-DC power supply included in the kit has a mating 6-pin plug. When the ML605 is installed into a table top or tower PC's PCIe slot, the ML605 is typically powered from the PC ATX power supply. One of the ATX hard disk type 4-pin power connectors is plugged into ML605 connector J25. The ML605 can be powered with the AC power adapter even when plugged into a PC PCIe motherboard slot; however, users are cautioned not to also connect an ATX 4-pin power connector to J25. See the caution notes below and in Figure 1-23, page 55. Caution! DO NOT plug a PC ATX power supply 6-pin connector into ML605 connector J60.
The ATX 6-pin connector has a different pinout than ML605 J60, and connecting the ATX 6-pin connector will damage the ML605 and void the board warranty.

Caution! DO NOT apply power to J60 and the 4-pin ATX disk drive connector J25 at the same
time as this will damage the ML605 board. Refer to Figure 1-23, page 55 for details.

The ML605 power can be turned on or off through the board mounted slide switch SW2. When the switch is in the on position, a green LED (DS25) is illuminated.

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Onboard Power Regulation

Figure 1-28 shows the ML605 onboard power supply architecture. The ML605 uses power solutions from Texas Instruments.
X-Ref Target - Figure 1-28

12V PWR Jack J25/J60

Power Supply

Linear Regulator TL1963 [email protected] max U8 Power Controller 1 UCD9240PFC

VCC5

U24 VCCINT

Switching Module PTD08A020W 1.00V@20A max U42

Switching Module PTD08A010W 2.50V@10A max U91

VCC2V5, FPGA_VCC2V5

Switching Module PTD08A020W 2.5V@20A max U43

VCCAUX

Linear Regulator TL1963A 1.8V@500mA max U79 Power Controller 2 UCD9240PFC

VCC1V8

U25 MGT_AVCC

Switching Regulator UCD7230RG 1.00V@6A max U35

Switching Regulator UCD7230RG 1.20V@6A max U36

MGT_AVTT

Switching Module PTD08A010W 1.5V@10A max U20

VCC1V5, FPGA_VCC1V5

Switching Module PTD08A010W 3.3V@10A max U21

VCC3V3

Sink/Source DDR Regulator

Linear Regulator TPS51200 0.75V@3A max U17

VTTDDR
UG534_28_060311

Figure 1-28:

ML605 Onboard Power Regulators

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Table 1-31:

Onboard Power System Devices

Reference Designator U24 U42 U43 U91 Description PMBus Controller - Core (Addr = 52) 20A 0.6V - 3.6V Adj. Switching Regulator 20A 0.6V - 3.6V Adj. Switching Regulator 10A 0.6V - 3.6V Adj. Switching Regulator VCCINT_FPGA VCC2V5_FPGA VCCAUX 1.00V 2.50V 2.50V Power Rail Net Name Power Rail Schematic Voltage Page 35 36 37 38

Device Type UCD9240PFC(1) PTD08A020W PTD08A020W PTD08A010W

UCD9240PFC(2) UCD7230RGWR UCD7230RGWR PTD08A010W PTD08A010W

U25 U35 U36 U20 U21

PMBus Controller - Aux (Addr = 53) 6A 0.6V - 3.6V Adj. Switching Regulator 6A 0.6V - 3.6V Adj. Switching Regulator 10A 0.6V - 3.6V Adj. Switching Regulator 10A 0.6V - 3.6V Adj. Switching Regulator MGT_AVCC MGT_AVTT VCC_1V5 VCC_3V3 1.00V 1.20V 1.50V 3.30V

40 41 42 43 44

TPS79518DCQR TPS51200DRCT TPS51200DRCT TL1963

Notes:

U79 U17 U17 U8

500 mA Fixed Linear Regulator 3A DDR3 VTERM Tracking Linear Regulator 10 mA Tracking Reference output 1.5A Fixed Linear Regulator

VCC_1V8 VTTDDR VTTVREF VCC5

1.80V 0.75V 0.75V 5.00V

45 45 45 35

1. See Table 1-32., part 1 (addr 52) 2. See Table 1-32., part 2 (addr 53)

Table 1-32:
Device

Power Rail Specifications (UCD9240 PMBus Controllers at Addresses 52 and 53)

Response Response Response Vout On Off Rail Schematic Vout PG On PG Off Rise Fall Over Delay Delay (ms) (ms) Fault Name Rail Name (V) (V) (V) (ms) (ms) (V) Rail #1 Rail #2 Rail #3 Rail #1 Rail #2 Rail #3 Rail #4 VCCINT VCC2V5 VCCAUX MGT _AVCC MGT _AVTT VCC1V5 _FPGA VCC3V3 1 2.5 2.5 1.025 1.25 1.5 3.3 0.925 2.313 2.325 0.948 1.156 1.388 3.052 0.9 2.25 2.25 0.923 5 2 1.125 1.35 2.97 10 5 10 5 0 0 20 5 10 1.375 Shut down 1.65 3.63 14.5 Shut down 80 Shut down 5 10 5 10 5 10 1.1 14 2.75 2.8 1.128 Shut down 9 Shut down 80 Shut down Iout Over Fault (A) Temp Over Fault (C)

Rail #

1 UCD9240 (Addr 52) 2 3 1

UCD9240 (Addr 53) 3 4

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Voltage and current monitoring and control are available for selected power rails through Texas Instruments Fusion Digital Power graphical user interface (GUI). Both onboard TI power controllers are wired to the same PMBus. The PMBus connector, J3, is provided for use with the TI USB Interface Adapter PMBus pod (TI part number EVM USB-TO-GPIO; refer to http://focus.ti.com/docs/toolsw/folders/print/usb-to-gpio.html). The ML605 board is shipped with a TI flyer containing information that allows the user to purchase this EVM at a discount. TI provides the Fusion Digital Power Designer software package (http://focus.ti.com/docs/toolsw/folders/print/fusion_digital_power_designer.html) which includes several tools capable of communicating with the UCD92xx series of controllers from a Windows-based host computer via the PMBus pod. The ML605 onboard connector J3 is wired for the TI EVM interface and provides access to the PMBUS and UCD9240s for monitoring purposes. This is the simplest and most convenient way to monitor the power rails. See Table 1-31 and Table 1-32. For details concerning the use of the Fusion software tool, refer to the documentation offered in the Fusion Digital Power Designer GUI help system (select Help Documentation and Help Center).

References
For more detailed information about this technology and the various power management controllers and regulator modules offered by Texas Instruments, visit http://www.ti.com/ww/en/analog/digital-power/index.html.

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22. System Monitor

The System Monitor provides information regarding the FPGA on-chip temperature and power supply conditions via JTAG and an internal FPGA interface. The System Monitor can also be used to monitor external analog signals via 17 external analog input channels. For more information regarding this functionality, which is featured on every Virtex-6 family member, see http://www.xilinx.com/systemmonitor. This section provides a brief overview of the System Monitor related functionality that is supported on the ML605.

Reference and Power Supply

The System Monitor has dedicated analog power supply pins and supports the use of an external 1.25V reference IC (U23) for the analog-to-digital conversion process. An option (using jumper J19) to select an on-chip reference is also provided; however, the highest accuracy over a temperature range of -40C to +125C is obtained using an external reference. Figure 1-29 illustrates the power supply and reference options on the ML605. For a more detailed discussion of these requirements, see the Virtex-6 FPGA System Monitor User Guide. [Ref 15]
X-Ref Target - Figure 1-29

VCC2V5

Analog Supply Filter

SYSMON_AVDD C190 X5R 6.3V 1UF C78 X5R 10V 0.1UF

J19 3 SYSMON_VREFP

VCC5

U23
REF3012 REF3012AIDBZT 1 IN GND C191 X5R 6.3V 1UF 3

AGND 1 C383 X5R 10V 0.1UF

2 OUT

1.25V

Ferrie Bead

C79 X5R 10V 0.1UF

AGND

GND

AGND

Jumper on pins 1-2 Default Setting: 1-2 Select External Reference 2-3 Select On-Chip Reference
UG534_29_081209

Figure 1-29:

System Monitor External Reference

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System Monitor Header (J35)

Figure 1-30 shows the pinout for the System Monitor 12-pin header. The header provides user access to the analog power supply (AVdd) and the 1.25V reference shown in Figure 1-29, page 71. Access to the FPGA thermal diode and dedicated analog input channel (Vp/Vn) is also provided on this header. The header can be used to connect user specific analog signals and sensors to the system monitor. The kelvin points for a 5 m current sensing shunt in the FPGA 1V Vccint core supply are also available on this header. By connecting header pins 9 to 11 and 10 to 12 using jumpers, the system monitor can be used to monitor the FPGA core current and power consumption. This can be used to collect useful power information about a particular design or implementation.
X-Ref Target - Figure 1-30

System Monitor Header J35

NC NC 1 3 5 1.25V Reference Anti-alias Filter Vccint_shunt_N
R232 100 1% 1/16W

2 4 6 8 10 12

FPGA Thermal Diode access FPGA_DX_P FPGA_DX_N

7 9 11

SYSMON_AVDD

Vccint_shunt_P

SYSMON_VN

SYSMON_VP

C169 X7R 16V 0.01UF

R233 100 1% 1/16W

AGND

Dedicated Analog Inputs

To Measure VCCINT Current: Jumper on 9-11, 10-12 Connect Vccint shunt to Vp,Vn
UG534_37 _081209

Figure 1-30:

System Monitor Header (J35)

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ML605 Board Power Monitor

In addition to monitoring the FPGA core supply power consumption, two auxiliary analog input channels (of the 16 that are available) are used to implement a power monitor for the entire ML605 board. The board power is monitored at the 12V power input connector. Figure 1-31 shows how the power monitor is implemented and connected to the System Monitor auxiliary input channels 12 and 13. A simple resistor divider is used to monitor the 12V supply voltage and to provide a reference voltage to an instrumentation amplifier (InAmp). The voltage on the auxiliary channel 12 is equal to supply voltage divided by 24 (~ 0.5V). The InAmp is used to amplify (by a factor of 50) the voltage dropped across a 2 m current sense shunt. The voltage at the output of the InAmp is proportional to the current. The voltage on auxiliary channel 13 = Current (amps) x 0.002 x 50. (e.g., 5A = 0.5V).
X-Ref Target - Figure 1-31

12V Supply Monitor

R1

2m 1%
R2 K1 K2

100nF
11.5k 0.5% ~0.5V V+

IN+

IN-

INA213
SC70-6 Package 50V/V
GND OUT

~470

1k

REF

VAUXP[13] Current Channel VAUXN[13]

499

0.5%

10nF

10nF

1k
~470

10nF

1k

VAUXP[12]
10nF

Voltage Channel VAUXN[12]

1k

UG534_38 _081209

Figure 1-31:

ML605 12V Power Monitor

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Fan Controller
In highly demanding situations, active thermal management in the form of a heat sink and fan may be required. In order to support this, drive circuitry for an external fan has been provided on the ML605. A fan with tach output can be connect at header J59 as shown in Figure 1-32. The fan PWM signal is generated by the FPGA and the tach input can be used to close the control loop and regulate the fan speed. Alternatively, the FPGA temperature as recorded by the System Monitor can be used to close the PWM control loop for the fan.
X-Ref Target - Figure 1-32

VCC12_P

J59
GND 12V Tach
VCC2V5
D16

1 2 3
1

R367 10.0K 1% 1/16W R368 10.0K 1% 1/16W

SM_FAN_TACH

1N4148

R358 4.75K 1%

R369 10.0K 1% 1/16W

2 Q24
0

NDT3055L
UG534_39 _081209

SM_FAN_PWM

Figure 1-32:

ML605 Fan Driver

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Detailed Description

FPGA Power Supply Margining

The PMBus (IIC), which provides access to the 2 x UDC9240 power controllers, can also be accessed via FPGA I/O in addition to a dedicated header (J3), see Figure 1-33. A full description of the UDC9240 functionality is outside the scope of this user guide. However, this useful feature can be used, for example, to margin the FPGA and board power supplies when evaluating a design. The System Monitor provides accurate measurements of the on-chip supply voltages as the FPGA supplies are margined. The PMBus (and fan) connections are shown in Figure 1-32.
X-Ref Target - Figure 1-33

TI_V3P3

PMBus Connector

J3
NC NC NC 1 3 5 7 9 2 4 6 8 10 NC NC

R301 100K 5%

R299 100K 5%

R300 100K 5%

UDC9240

PMBUS_ALERT PMBUS_DATA PMBUS_CLK PMBUS_CTRL

35 20 19 36

DGND1 9240
R335 1.0M 5%

AGND1

BANK 34 6vlx240tff1156
IO_L11N_SRCC_34_AJ9 IO_L11P_SRCC_34_AH9 IO_L10N_MRCC_34_AB10 IO_L10P_MRCC_34_AC10 IO_L9N_MRCC_34_M10 IO_L9P_MRCC_34_L10 AJ9 AH9 AB10 AC10 M10 L10 PMBUS_CTRL_LS PMBUS_ALERT_LS PMBUS_DATA_LS PMBUS_CLK_LS SM_FAN_TACH SM_FAN_PWM

UG534_35_081209

Figure 1-33: UDC9240 PMBus Access

System Monitor ML605 Demonstration Design

The various features described in this section are easily evaluated using a MicroBlaze based reference designed provided with the ML605 Evaluation Board. This reference design supports a UART based interface using a terminal program such as Hyperterminal to provide information on the FPGA power supplies, temperature, and power consumption. In addition, the UART interface can be used to margin the FPGA supplies over the PMBus. The System Monitor functionality can also be accessed at any time via JTAG using the ChipScope Pro Analyzer tool without design modifications or cores inserted into a user design. The ChipScope Pro Analyzer tool automatically connects to the System Monitor via a JTAG cable after a connection is established.

References
For more information on using the System Monitor and an overview of the tool support for this feature, see the Virtex-6 FPGA System Monitor User Guide. [Ref 15]

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Chapter 1: ML605 Evaluation Board

Configuration Options
The FPGA on the ML605 Evaluation Board can be configured by the following methods: 3. 128 Mb Platform Flash XL, page 22 4. 32 MB Linear BPI Flash, page 22 5. System ACE CF and CompactFlash Connector, page 26 6. USB JTAG, page 28

For more information, see the Virtex-6 FPGA Configuration User Guide at http://www.xilinx.com/support/documentation/user_guides/ug360.pdf. Table 1-33: Mode Switch S2 Settings
Configuration Mode Slave SelectMAP BPI Mode JTAG Mode Pins (M2,M1,M0) 110 010 101

With the mode set to JTAG 101, the ML605 will not attempt to boot or load a bitstream from either of the Flash devices. If a CompactFlash (CF) card is installed in the CF socket U73, System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1. With no CF card present, the ML605 can be configured via the onboard JTAG controller and USB download cable as described above. With the mode set to either Slave SelectMAP 110, or BPI Mode 010, the FPGA will attempt to configure itself from the selected Flash device as described in 3. 128 Mb Platform Flash XL, page 22. Note: S1 switch 4 is the System ACE controller enable switch. When ON, this switch allows the System ACE to boot at power-on if it finds a CF card present. In order to boot from BPI Flash U4 or Xilinx Platform Flash (U27) without System ACE contention, S1 switch 4 must be OFF.

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Appendix A

References
This section provides references to documentation supporting Virtex-6 FPGAs, tools, and IP. For additional information, see www.xilinx.com/support/documentation/index.htm. Documents supporting the ML605 Evaluation Board:
1. 2. 3. 4. 5. 6. 7. 8. 9. UG535, ML605 Reference Design User Guide UG525, Getting Started with the Xilinx Virtex-6 FPGA ML605 Evaluation Kit DS150, Virtex-6 Family Overview DS152, Viretx-6 FPGA Data Sheet: DC and Switching Characteristics UG360, Virtex-6 FPGA Configuration User Guide UG406, Virtex-6 FPGA Memory Interface Solutions User Guide UG361, Virtex-6 FPGA SelectIO Resources User Guide UG362, Virtex-6 FPGA User Guide: Clocking Resources UG363, Virtex-6 FPGA Memory Resources User Guide

10. UG364, Virtex-6 FPGA Configurable Logic Block User Guide 11. UG365, Virtex-6 FPGA Packaging and Pinout Specifications 12. UG366, Virtex-6 FPGA GTX Transceivers User Guide 13. UG369, Virtex-6 FPGA DSP48E1 Slice User Guide 14. DS186, Virtex-6 FPGA Memory Interface Solutions Data Sheet 15. UG370, Virtex-6 FPGA System Monitor User Guide 16. DS715, Virtex-6 FPGA Integrated Block v1.2 for PCI Express Data Sheet 17. DS617, Platform Flash XL High-Density Configuration and Storage Device Data Sheet 18. DS080, System ACE CompactFlash Solution Data Sheet 19. UG138, LogiCORE IP Tri-Mode Ethernet MAC v4.2 User Guide 20. DS581, XPS External Peripheral Controller (EPC) v1.02a Data Sheet 21. DS606, XPS IIC Bus Interface (v2.00a) Data Sheet

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Appendix A: References

Additional documentation:
22. Micron Technology, Inc., DDR3 SODIMM Specification (MT4JSF6464HY-1G1) 23. Winbond, Serial Flash Memory Data Sheet (W25Q64VSFIG) 24. Numonyx, Embedded Flash Memory Data Sheet (TE28F128J3D-75) 25. SiTime,Oscillator Data Sheet (SiT9102AI-243N25E200.00000) 26. MMD Components, MBH Series Data Sheet (MBH2100H-66.000 MHz) 27. PCI SIG, PCI Express Specifications 28. Marvell, Alaska Gigabit Ethernet Transceivers Product Page 29. Cypress Semiconductor, CY7C67300 Data Sheet 30. USB Implementers Forum, Inc., USB Specifications 31. ST Micro, M24C08 Data Sheet 32. Samtec, Inc.

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Appendix B

Default Switch and Jumper Settings

Table B-34:
REFDES
SW2 Board power slide-switch User GPIO 8-pole DIP switch 8 7 6 SW1 5 4 3 2 1 System ACE CF configuration and image select 4-pole DIP switch 4 S1 3 2 1 SysACE Mode = 1 (1) SysAce CFGAddr 2 = 0 SysAce CFGAddr 1 = 0 SysAce CFGAddr 0 = 0 off off off off off off off off off off off off

Default Switch Settings

Function/Type Default
off

FPGA mode, boot PROM select and FPGA CCLK select 6-pole DIP switch 6 5 S2 4 3 2 1 Notes:
1. S1 position 4 is the System ACE controller enable switch. When ON, this switch allows the System ACE to boot at power on if it finds a CF card present. In order to boot from BPI Flash or Xilinx Platform Flash without System ACE contention, S1 switch 4 must be OFF.

FLASH_A23 = 0 M2 = 0 M1 = 1 M[2:0] = 010 = Master BPI-Up M0 = 0 CS_SEL = 1 = boot from BPI Flash EXT_CCLK = 0

off off on off on off

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Appendix B: Default Switch and Jumper Settings

Table B-35:

Default Jumper Settings

Function System ACE CF Error LED Enable Default Jump 1-2

Jumper REFDES J69 GMII: J66 J67 J68 FMC JTAG Bypass: J18 J17 System Monitor: J19 J35 SFP Module: J54 J65 PCIe Lane Size: J42 1 lane Full BW SFP Enable

pins 1-2: GMII/MII to Cu pins 2-3: SGMII to Cu, no clk pins 1-2: GMII/MII to Cu pins 2-3: SGMII to Cu, no clk J66 pins 1-2, J68 ON: RGMII, modified MII in Cu

Jump 1 - 2 Jump 1 - 2 no jumper

exclude FMC LPC connector exclude FMC HPC connector

Jump 1 - 2 Jump 1 - 2

Test_mon_vrefp sourced by U23, REF3012 measure voltage across R-kelvin on VCCINT

Jump 1 - 2 Jump 9 - 11, Jump 10 - 12

Jump 1 - 2 Jump 1 - 2

Jump 1 - 2

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Appendix C

VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout
Figure C-34 shows the pinout of the FMC LPC connector. Pins marked NC are not connected.
X-Ref Target - Figure C-34

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

K NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

J NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

H VR EF _A_M2C PR SNT_M2C_L GND CLK0_M2C _P CLK0_M2C _N GND LA02_P LA02_N GND LA04_P LA04_N G ND LA07_P LA07_N G ND LA11_P LA11_N G ND LA15_P LA15_N G ND LA19_P LA19_N G ND LA21_P LA21_N G ND LA24_P LA24_N G ND LA28_P LA28_N G ND LA30_P LA30_N G ND LA32_P LA32_N G ND V ADJ

G GND C LK 1_M2C_P C LK 1_M2C_N GND GND LA00_P _C C LA00_N_C C GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ G ND

F NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

E D NC P G_C2M NC G ND NC G ND NC G BT CLK0_M2C _P NC G BT CLK0_M2C _N NC G ND NC G ND NC LA01_P _C C NC LA01_N_C C NC GND NC LA05_P NC LA05_N NC GND NC LA09_P NC LA09_N NC GND NC LA13_P NC LA13_N NC GND NC LA17_P _C C NC LA17_N_C C NC GND NC LA23_P NC LA23_N NC GND NC LA26_P NC LA26_N NC GND NC T CK NC TDI NC TDO NC 3P3VAUX NC TMS NC TR ST _L NC G A1 NC 3P 3V NC GND NC 3P3V NC GND NC 3P 3V

C G ND DP 0_C2M_P DP 0_C2M_N GND GND DP 0_M2C_P DP 0_M2C_N G ND G ND LA06_P LA06_N GND G ND LA10_P LA10_N G ND GND LA14_P LA14_N G ND G ND LA18_P _C C LA18_N_C C GND G ND LA27_P LA27_N G ND GND S CL S DA GND G ND GA0 12P0V GND 12P0V G ND 3P3V GND

B NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

A NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

Figure C-34:

FMC LPC Connector Pinout

For more information, refer to the VITA 57.1 FMC LPC Connections table (Table 1-30).

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82
X-Ref Target - Figure C-35

Figure C-35:

Appendix C: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout

Figure C-35 shows the pinout of the FMC HPC connector.

For more information, refer to the VITA 57.1 FMC HPC Connections table (Table 1-28).

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FMC HPC Connector Pinout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

K VR EF _B _M2C GND GND CLK2_M2C _P CLK2_M2C _N GND HA02_P HA02_N GND HA06_P HA06_N G ND HA10_P HA10_N G ND HA17_P _C C HA17_N_C C G ND HA21_P HA21_N G ND HA23_P HA23_N G ND HB00_P _C C HB00_N_C C G ND HB06_P _C C HB06_N_C C G ND HB10_P HB10_N G ND HB14_P HB14_N G ND HB17_P _C C HB17_N_C C G ND V IO_B _M2C

J GND C LK 3_M2C_P C LK 3_M2C_N GND GND HA03_P HA03_N GND HA07_P HA07_N GND HA11_P HA11_N GND HA14_P HA14_N G ND HA18_P HA18_N GND HA22_P HA22_N GND HB01_P HB01_N G ND HB07_P HB07_N G ND HB11_P HB11_N GND HB15_P HB15_N GND HB18_P HB18_N G ND VIO_B_M2C GND

H V RE F_A_M2C P RS NT _M2C _L G ND C LK 0_M2C_P C LK 0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N GND LA32_P LA32_N G ND V ADJ

G G ND CLK1_M2C _P CLK1_M2C _N G ND G ND LA00_P _C C LA00_N_C C GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ G ND

F PG _M2C GND GND HA00_P _C C HA00_N_C C G ND HA04_P HA04_N GND HA08_P HA08_N GND HA12_P HA12_N GND HA15_P HA15_N GND HA19_P HA19_N GND HB02_P HB02_N GND HB04_P HB04_N GND HB08_P HB08_N GND HB12_P HB12_N GND HB16_P HB16_N GND HB20_P HB20_N GND VADJ

E GND HA01_P _C C HA01_N_C C G ND G ND HA05_P HA05_N GND HA09_P HA09_N GND HA13_P HA13_N GND HA16_P HA16_N GND HA20_P HA20_N GND HB03_P HB03_N GND HB05_P HB05_N GND HB09_P HB09_N GND HB13_P HB13_N GND HB19_P HB19_N GND HB21_P HB21_N GND V ADJ GND

D P G_C2M G ND G ND GB TC LK 0_M2C_P GB TC LK 0_M2C_N GND GND LA01_P _C C LA01_N_C C GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P _C C LA17_N_C C GND LA23_P LA23_N GND LA26_P LA26_N GND T CK TDI TDO 3P3VAUX TMS TR ST _L G A1 3P 3V GND 3P3V G ND 3P3V

C G ND DP 0_C2M_P DP 0_C2M_N G ND G ND DP0_M2C _P DP0_M2C _N G ND G ND LA06_P LA06_N GND G ND LA10_P LA10_N G ND GND LA14_P LA14_N G ND G ND LA18_P _C C LA18_N_C C GND G ND LA27_P LA27_N G ND GND S CL S DA GND G ND GA0 12P0V GND 12P0V G ND 3P 3V G ND

B RE S1 G ND G ND DP 9_M2C_P DP 9_M2C_N GND GND DP 8_M2C_P DP 8_M2C_N GND GND DP7_M2C _P DP 7_M2C_N GND GND DP 6_M2C_P DP6_M2C _N GND GND GB TC LK 1_M2C_P GB TC LK 1_M2C_N G ND G ND DP9_C 2M_P DP 9_C2M_N GND GND DP 8_C2M_P DP8_C 2M_N GND GND DP7_C 2M_P DP 7_C2M_N G ND G ND DP6_C 2M_P DP6_C 2M_N GND GND RE S0

A GND DP 1_M2C_P DP 1_M2C_N G ND G ND DP2_M2C _P DP2_M2C _N G ND G ND DP3_M2C _P DP3_M2C _N GND G ND DP4_M2C _P DP4_M2C _N G ND GND DP5_M2C _P DP5_M2C _N G ND G ND DP 1_C2M_P DP 1_C2M_N GND G ND DP2_C 2M_P DP2_C 2M_N G ND GND DP3_C 2M_P DP3_C 2M_N GND G ND DP 4_C2M_P DP 4_C2M_N GND GND DP5_C 2M_P DP5_C 2M_N GND

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Appendix D

ML605 Master UCF

The UCF template is provided for designs that target the ML605. Net names provided in the constraints below correlate with net names on the ML605 schematic. On identifying the appropriate pins, the net names below should be replaced with net names in the user RTL. See the Constraints Guide for more information. Users can refer to the UCF files generated by tools such as MIG (Memory Interface Generator for memory interfaces) and BSB (Base System Builder) for more detailed information concerning the I/O standards required for each particular interface. The FMC connectors J63 and J64 are connected to 2.5V Vcco banks. Because each users FMC card implements customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each customer. The latest version of the UCF can be found on the ML605 board documentation website at http://www.xilinx.com/ml605.
NET NET ## NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "CLK_33MHZ_SYSACE" "CPU_RESET" "DDR3_A0" "DDR3_A1" "DDR3_A2" "DDR3_A3" "DDR3_A4" "DDR3_A5" "DDR3_A6" "DDR3_A7" "DDR3_A8" "DDR3_A9" "DDR3_A10" "DDR3_A11" "DDR3_A12" "DDR3_A13" "DDR3_A14" "DDR3_A15" "DDR3_BA0" "DDR3_BA1" "DDR3_BA2" "DDR3_CAS_B" "DDR3_CKE0" "DDR3_CKE1" "DDR3_CLK0_N" "DDR3_CLK0_P" "DDR3_CLK1_N" "DDR3_CLK1_P" "DDR3_D0" "DDR3_D1" "DDR3_D2" "DDR3_D3" "DDR3_D4" LOC = "AE16"; LOC = "H10"; LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = "L14"; "A16"; "B16"; "E16"; "D16"; "J17"; "A15"; "B15"; "G15"; "F15"; "M16"; "M15"; "H15"; "J15"; "D15"; "C15"; "K19"; "J19"; "L15"; "C17"; "M18"; "M17"; "H18"; "G18"; "L16"; "K16"; "J11"; "E13"; "F13"; "K11"; "L11"; ## 93 ## 2 ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 109 108 79 115 73 74 103 101 104 102 5 7 15 17 4 on U19 on SW10 pushbutton (active-High) on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1

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Appendix D: ML605 Master UCF

NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET

"DDR3_D5" "DDR3_D6" "DDR3_D7" "DDR3_D8" "DDR3_D9" "DDR3_D10" "DDR3_D11" "DDR3_D12" "DDR3_D13" "DDR3_D14" "DDR3_D15" "DDR3_D16" "DDR3_D17" "DDR3_D18" "DDR3_D19" "DDR3_D20" "DDR3_D21" "DDR3_D22" "DDR3_D23" "DDR3_D24" "DDR3_D25" "DDR3_D26" "DDR3_D27" "DDR3_D28" "DDR3_D29" "DDR3_D30" "DDR3_D31" "DDR3_D32" "DDR3_D33" "DDR3_D34" "DDR3_D35" "DDR3_D36" "DDR3_D37" "DDR3_D38" "DDR3_D39" "DDR3_D40" "DDR3_D41" "DDR3_D42" "DDR3_D43" "DDR3_D44" "DDR3_D45" "DDR3_D46" "DDR3_D47" "DDR3_D48" "DDR3_D49" "DDR3_D50" "DDR3_D51" "DDR3_D52" "DDR3_D53" "DDR3_D54" "DDR3_D55" "DDR3_D56" "DDR3_D57" "DDR3_D58" "DDR3_D59" "DDR3_D60" "DDR3_D61" "DDR3_D62" "DDR3_D63" "DDR3_DM0" "DDR3_DM1" "DDR3_DM2" "DDR3_DM3" "DDR3_DM4" "DDR3_DM5"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

"K13"; "K12"; "D11"; "M13"; "J14"; "B13"; "B12"; "G10"; "M11"; "C12"; "A11"; "G11"; "F11"; "D14"; "C14"; "G12"; "G13"; "F14"; "H14"; "C19"; "G20"; "E19"; "F20"; "A20"; "A21"; "E22"; "E23"; "G21"; "B21"; "A23"; "A24"; "C20"; "D20"; "J20"; "G22"; "D26"; "F26"; "B26"; "E26"; "C24"; "D25"; "D27"; "C25"; "C27"; "B28"; "D29"; "B27"; "G27"; "A28"; "E24"; "G25"; "F28"; "B31"; "H29"; "H28"; "B30"; "A30"; "E29"; "F29"; "E11"; "B11"; "E14"; "D19"; "B22"; "A26";

## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##

6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 11 28 46 63 136 153

on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on

J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1

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NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET ## NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET ## NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET

"DDR3_DM6" "DDR3_DM7" "DDR3_DQS0_N" "DDR3_DQS0_P" "DDR3_DQS1_N" "DDR3_DQS1_P" "DDR3_DQS2_N" "DDR3_DQS2_P" "DDR3_DQS3_N" "DDR3_DQS3_P" "DDR3_DQS4_N" "DDR3_DQS4_P" "DDR3_DQS5_N" "DDR3_DQS5_P" "DDR3_DQS6_N" "DDR3_DQS6_P" "DDR3_DQS7_N" "DDR3_DQS7_P" "DDR3_ODT0" "DDR3_ODT1" "DDR3_RAS_B" "DDR3_RESET_B" "DDR3_S0_B" "DDR3_S1_B" "DDR3_TEMP_EVENT" "DDR3_WE_B" "DVI_D0" "DVI_D1" "DVI_D2" "DVI_D3" "DVI_D4" "DVI_D5" "DVI_D6" "DVI_D7" "DVI_D8" "DVI_D9" "DVI_D10" "DVI_D11" "DVI_DE" "DVI_GPIO1_FMC_C2M_PG_LS" "DVI_H" "DVI_RESET_B_LS" "DVI_V" "DVI_XCLK_N" "DVI_XCLK_P" "FLASH_A0" "FLASH_A1" "FLASH_A2" "FLASH_A3" "FLASH_A4" "FLASH_A5" "FLASH_A6" "FLASH_A7" "FLASH_A8" "FLASH_A9" "FLASH_A10" "FLASH_A11" "FLASH_A12" "FLASH_A13" "FLASH_A14" "FLASH_A15" "FLASH_A16" "FLASH_A17"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

"A29"; "A31"; "E12"; "D12"; "J12"; "H12"; "A14"; "A13"; "H20"; "H19"; "C23"; "B23"; "A25"; "B25"; "G28"; "H27"; "D30"; "C30"; "F18"; "E17"; "L19"; "E18"; "K18"; "K17"; "D17"; "B17"; "AJ19"; "AH19"; "AM17"; "AM16"; "AD17"; "AE17"; "AK18"; "AK17"; "AE18"; "AF18"; "AL16"; "AK16"; "AD16"; "K9"; "AN17"; "AP17"; "AD15"; "AC17"; "AC18"; "AL8"; "AK8"; "AC9"; "AD10"; "C8"; "B8"; "E9"; "E8"; "A8"; "A9"; "D9"; "C9"; "D10"; "C10"; "F10"; "F9"; "AH8"; "AG8";

## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##

170 187 10 12 27 29 45 47 62 64 135 137 152 154 169 171 186 188 116 120 110 30 114 121 198 113 63 62 61 60 59 58 55 54 53 52 51 50 2 18 4 2 5 56 57 29 25 24 23 22 21 20 19 8 7 6 5 4 3 2 1 55 18

on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on

J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 U38 U38 U38 U38 U38 U38 U38 U38 U38 U38 U38 U38 U38 U32 U38 U32 U38 U38 U38 U4, U4, U4, U4, U4, U4, U4, U4, U4, U4, U4, U4, U4, U4, U4, U4, U4, U4, (thru series R111 47.5 (thru series R110 47.5 (thru series R109 47.5 (thru series R108 47.5 (thru series R107 47.5 (thru series R106 47.5 (thru series R105 47.5 (thru series R104 47.5 (thru series R103 47.5 (thru series R102 47.5 (thru series R101 47.5 (thru series R100 47.5 (thru series R112 47.5 (not wired to U38) (thru series R113 47.5 (DVI_RESET_B pin 13 on (thru series R114 47.5 ohm) ohm) ohm) ohm) ohm) ohm) ohm) ohm) ohm) ohm) ohm) ohm) ohm) ohm) U38) ohm)

A1 B1 C1 D1 D2 A2 C2 A3 B3 C3 D3 C4 A5 B5 C5 D7 D8 A7

on on on on on on on on on on on on on on on on on on

U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27

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NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET ## ## NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET

"FLASH_A18" "FLASH_A19" "FLASH_A20" "FLASH_A21" "FLASH_A22" "FLASH_A23" "FLASH_D0" "FLASH_D1" "FLASH_D2" "FLASH_D3" "FLASH_D4" "FLASH_D5" "FLASH_D6" "FLASH_D7" "FLASH_D8" "FLASH_D9" "FLASH_D10" "FLASH_D11" "FLASH_D12" "FLASH_D13" "FLASH_D14" "FLASH_D15" "FLASH_WAIT" "FPGA_FWE_B" "FPGA_FOE_B" "FPGA_CCLK" "PLATFLASH_L_B" "FPGA_FCS_B"

LOC = "AP9"; LOC = "AN9"; LOC = "AF10"; LOC = "AF9"; LOC = "AL9"; LOC = "AA23"; LOC = "AF24"; LOC = "AF25"; LOC = "W24"; LOC = "V24"; LOC = "H24"; LOC = "H25"; LOC = "P24"; LOC = "R24"; LOC = "G23"; LOC = "H23"; LOC = "N24"; LOC = "N23"; LOC = "F23"; LOC = "F24"; LOC = "L24"; LOC = "M23"; LOC = "J26"; LOC = "AF23"; LOC = "AA24"; LOC = "K8"; LOC = "AC23"; LOC = "Y24";

## 17 on U4, B7 on U27 ## 16 on U4, C7 on U27 ## 11 on U4, C8 on U27 ## 10 on U4, A8 on U27 ## 9 on U4, G1 on U27 ## 26 on U4 ## 34 on U4 (thru series R215 ## 36 on U4 (thru series R216 ## 39 on U4 (thru series R217 ## 41 on U4 (thru series R218 ## 47 on U4 (thru series R219 ## 49 on U4 (thru series R220 ## 51 on U4 (thru series R221 ## 53 on U4 (thru series R222 ## 35 on U4 (thru series R223 ## 37 on U4 (thru series R224 ## 40 on U4 (thru series R225 ## 42 on U4 (thru series R226 ## 48 on U4 (thru series R227 ## 50 on U4 (thru series R228 ## 52 on U4 (thru series R229 ## 54 on U4 (thru series R230 ## 56 on U4 ## 14 on U4, G8 on U27 ## 32 on U4, F8 on U27 ## F1 on U27 ## H1 on U27 ## 30 on U4, B4 on U27 (U10 and select either U4 or U27) ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## H5 H4 G3 G2 15 16 2 2 J3 J2 2 2 C3 C2 C7 C6 A23 A22 A3 A2 A27 A26 A7 A6 A31 A30 A11 A10 A35 A34 A15 A14 A39 A38 A19 on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on J64 J64 J64 J64 U83 U83 series series J64 J64 series series J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64

100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100

ohm), ohm), ohm), ohm), ohm), ohm), ohm), ohm), ohm), ohm), ohm), ohm), ohm), ohm), ohm), ohm),

F2 E2 G3 E4 E5 G5 G6 H7 E1 E3 F3 F4 F5 H5 G7 E7

on on on on on on on on on on on on on on on on

U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27 U27

switch S2.2 setting

"FMC_HPC_CLK0_M2C_N" "FMC_HPC_CLK0_M2C_P" "FMC_HPC_CLK1_M2C_N" "FMC_HPC_CLK1_M2C_P" "FMC_HPC_CLK2_M2C_IO_N" "FMC_HPC_CLK2_M2C_IO_P" "FMC_HPC_CLK2_M2C_MGT_C_N" "FMC_HPC_CLK2_M2C_MGT_C_P" "FMC_HPC_CLK3_M2C_IO_N" "FMC_HPC_CLK3_M2C_IO_P" "FMC_HPC_CLK3_M2C_MGT_C_N" "FMC_HPC_CLK3_M2C_MGT_C_P" "FMC_HPC_DP0_C2M_N" "FMC_HPC_DP0_C2M_P" "FMC_HPC_DP0_M2C_N" "FMC_HPC_DP0_M2C_P" "FMC_HPC_DP1_C2M_N" "FMC_HPC_DP1_C2M_P" "FMC_HPC_DP1_M2C_N" "FMC_HPC_DP1_M2C_P" "FMC_HPC_DP2_C2M_N" "FMC_HPC_DP2_C2M_P" "FMC_HPC_DP2_M2C_N" "FMC_HPC_DP2_M2C_P" "FMC_HPC_DP3_C2M_N" "FMC_HPC_DP3_C2M_P" "FMC_HPC_DP3_M2C_N" "FMC_HPC_DP3_M2C_P" "FMC_HPC_DP4_C2M_N" "FMC_HPC_DP4_C2M_P" "FMC_HPC_DP4_M2C_N" "FMC_HPC_DP4_M2C_P" "FMC_HPC_DP5_C2M_N" "FMC_HPC_DP5_C2M_P" "FMC_HPC_DP5_M2C_N"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

"K23"; "K24"; "AP21"; "AP20"; "AC30"; "AD30"; "AB5"; "AB6"; "AF34"; "AE34"; "AH5"; "AH6"; "AB2"; "AB1"; "AC4"; "AC3"; "AD2"; "AD1"; "AE4"; "AE3"; "AF2"; "AF1"; "AF6"; "AF5"; "AH2"; "AH1"; "AG4"; "AG3"; "AK2"; "AK1"; "AJ4"; "AJ3"; "AM2"; "AM1"; "AL4";

C399 0.1uF C398 0.1uF

C397 0.1uF C396 0.1uF

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"FMC_HPC_DP5_M2C_P" "FMC_HPC_DP6_C2M_N" "FMC_HPC_DP6_C2M_P" "FMC_HPC_DP6_M2C_N" "FMC_HPC_DP6_M2C_P" "FMC_HPC_DP7_C2M_N" "FMC_HPC_DP7_C2M_P" "FMC_HPC_DP7_M2C_N" "FMC_HPC_DP7_M2C_P" "FMC_HPC_GBTCLK0_M2C_N" "FMC_HPC_GBTCLK0_M2C_P" "FMC_HPC_GBTCLK1_M2C_N" "FMC_HPC_GBTCLK1_M2C_P" "FMC_HPC_HA00_CC_N" "FMC_HPC_HA00_CC_P" "FMC_HPC_HA01_CC_N" "FMC_HPC_HA01_CC_P" "FMC_HPC_HA02_N" "FMC_HPC_HA02_P" "FMC_HPC_HA03_N" "FMC_HPC_HA03_P" "FMC_HPC_HA04_N" "FMC_HPC_HA04_P" "FMC_HPC_HA05_N" "FMC_HPC_HA05_P" "FMC_HPC_HA06_N" "FMC_HPC_HA06_P" "FMC_HPC_HA07_N" "FMC_HPC_HA07_P" "FMC_HPC_HA08_N" "FMC_HPC_HA08_P" "FMC_HPC_HA09_N" "FMC_HPC_HA09_P" "FMC_HPC_HA10_N" "FMC_HPC_HA10_P" "FMC_HPC_HA11_N" "FMC_HPC_HA11_P" "FMC_HPC_HA12_N" "FMC_HPC_HA12_P" "FMC_HPC_HA13_N" "FMC_HPC_HA13_P" "FMC_HPC_HA14_N" "FMC_HPC_HA14_P" "FMC_HPC_HA15_N" "FMC_HPC_HA15_P" "FMC_HPC_HA16_N" "FMC_HPC_HA16_P" "FMC_HPC_HA17_CC_N" "FMC_HPC_HA17_CC_P" "FMC_HPC_HA18_N" "FMC_HPC_HA18_P" "FMC_HPC_HA19_N" "FMC_HPC_HA19_P" "FMC_HPC_HA20_N" "FMC_HPC_HA20_P" "FMC_HPC_HA21_N" "FMC_HPC_HA21_P" "FMC_HPC_HA22_N" "FMC_HPC_HA22_P" "FMC_HPC_HA23_N" "FMC_HPC_HA23_P" "FMC_HPC_HB00_CC_N" "FMC_HPC_HB00_CC_P" "FMC_HPC_HB01_N" "FMC_HPC_HB01_P"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

"AL3"; "AN4"; "AN3"; "AM6"; "AM5"; "AP2"; "AP1"; "AP6"; "AP5"; "AD5"; "AD6"; "AK5"; "AK6"; "AF33"; "AE33"; "AC29"; "AD29"; "AC25"; "AB25"; "Y26"; "AA25"; "AC28"; "AB28"; "AC27"; "AB27"; "AA29"; "AA28"; "AB26"; "AA26"; "AF31"; "AG31"; "AB31"; "AB30"; "AC34"; "AD34"; "AG32"; "AG33"; "AE32"; "AD32"; "AD31"; "AE31"; "AA31"; "AA30"; "AC32"; "AB32"; "AB33"; "AC33"; "W30"; "V30"; "T34"; "T33"; "U32"; "U33"; "V33"; "V32"; "U30"; "U31"; "V29"; "U28"; "U27"; "U26"; "AG30"; "AF30"; "AM32"; "AN32";

## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##

A18 B37 B36 B17 B16 B33 B32 B13 B12 D5 D4 B21 B20 F5 F4 E3 E2 K8 K7 J7 J6 F8 F7 E7 E6 K11 K10 J10 J9 F11 F10 E10 E9 K14 K13 J13 J12 F14 F13 E13 E12 J16 J15 F17 F16 E16 E15 K17 K16 J19 J18 F20 F19 E19 E18 K20 K19 J22 J21 K23 K22 K26 K25 J25 J24

on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on

J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64

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NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET

"FMC_HPC_HB02_N" "FMC_HPC_HB02_P" "FMC_HPC_HB03_N" "FMC_HPC_HB03_P" "FMC_HPC_HB04_N" "FMC_HPC_HB04_P" "FMC_HPC_HB05_N" "FMC_HPC_HB05_P" "FMC_HPC_HB06_CC_N" "FMC_HPC_HB06_CC_P" "FMC_HPC_HB07_N" "FMC_HPC_HB07_P" "FMC_HPC_HB08_N" "FMC_HPC_HB08_P" "FMC_HPC_HB09_N" "FMC_HPC_HB09_P" "FMC_HPC_HB10_N" "FMC_HPC_HB10_P" "FMC_HPC_HB11_N" "FMC_HPC_HB11_P" "FMC_HPC_HB12_N" "FMC_HPC_HB12_P" "FMC_HPC_HB13_N" "FMC_HPC_HB13_P" "FMC_HPC_HB14_N" "FMC_HPC_HB14_P" "FMC_HPC_HB15_N" "FMC_HPC_HB15_P" "FMC_HPC_HB16_N" "FMC_HPC_HB16_P" "FMC_HPC_HB17_CC_N" "FMC_HPC_HB17_CC_P" "FMC_HPC_HB18_N" "FMC_HPC_HB18_P" "FMC_HPC_HB19_N" "FMC_HPC_HB19_P" "FMC_HPC_LA00_CC_N" "FMC_HPC_LA00_CC_P" "FMC_HPC_LA01_CC_N" "FMC_HPC_LA01_CC_P" "FMC_HPC_LA02_N" "FMC_HPC_LA02_P" "FMC_HPC_LA03_N" "FMC_HPC_LA03_P" "FMC_HPC_LA04_N" "FMC_HPC_LA04_P" "FMC_HPC_LA05_N" "FMC_HPC_LA05_P" "FMC_HPC_LA06_N" "FMC_HPC_LA06_P" "FMC_HPC_LA07_N" "FMC_HPC_LA07_P" "FMC_HPC_LA08_N" "FMC_HPC_LA08_P" "FMC_HPC_LA09_N" "FMC_HPC_LA09_P" "FMC_HPC_LA10_N" "FMC_HPC_LA10_P" "FMC_HPC_LA11_N" "FMC_HPC_LA11_P" "FMC_HPC_LA12_N" "FMC_HPC_LA12_P" "FMC_HPC_LA13_N" "FMC_HPC_LA13_P" "FMC_HPC_LA14_N"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

"AP33"; "AP32"; "AM31"; "AL30"; "AL33"; "AM33"; "AN34"; "AN33"; "AE26"; "AF26"; "AH34"; "AJ34"; "AK32"; "AK33"; "AK34"; "AL34"; "AF29"; "AF28"; "AJ30"; "AJ29"; "AJ32"; "AJ31"; "AH32"; "AH33"; "AD27"; "AE27"; "AE29"; "AE28"; "AH30"; "AH29"; "AG28"; "AG27"; "AD26"; "AD25"; "AK31"; "AL31"; "AF21"; "AF20"; "AL19"; "AK19"; "AD20"; "AC20"; "AD19"; "AC19"; "AE19"; "AF19"; "AH22"; "AG22"; "AG21"; "AG20"; "AJ21"; "AK21"; "AJ22"; "AK22"; "AL18"; "AM18"; "AL20"; "AM20"; "AN22"; "AM22"; "AL21"; "AM21"; "AN18"; "AP19"; "AN20";

## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##

F23 F22 E22 E21 F26 F25 E25 E24 K29 K28 J28 J27 F29 F28 E28 E27 K32 K31 J31 J30 F32 F31 E31 E30 K35 K34 J34 J33 F35 F34 K38 K37 J37 J36 E34 E33 G7 G6 D9 D8 H8 H7 G10 G9 H11 H10 D12 D11 C11 C10 H14 H13 G13 G12 D15 D14 C15 C14 H17 H16 G16 G15 D18 D17 C19

on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on

J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64

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"FMC_HPC_LA14_P" "FMC_HPC_LA15_N" "FMC_HPC_LA15_P" "FMC_HPC_LA16_N" "FMC_HPC_LA16_P" "FMC_HPC_LA17_CC_N" "FMC_HPC_LA17_CC_P" "FMC_HPC_LA18_CC_N" "FMC_HPC_LA18_CC_P" "FMC_HPC_LA19_N" "FMC_HPC_LA19_P" "FMC_HPC_LA20_N" "FMC_HPC_LA20_P" "FMC_HPC_LA21_N" "FMC_HPC_LA21_P" "FMC_HPC_LA22_N" "FMC_HPC_LA22_P" "FMC_HPC_LA23_N" "FMC_HPC_LA23_P" "FMC_HPC_LA24_N" "FMC_HPC_LA24_P" "FMC_HPC_LA25_N" "FMC_HPC_LA25_P" "FMC_HPC_LA26_N" "FMC_HPC_LA26_P" "FMC_HPC_LA27_N" "FMC_HPC_LA27_P" "FMC_HPC_LA28_N" "FMC_HPC_LA28_P" "FMC_HPC_LA29_N" "FMC_HPC_LA29_P" "FMC_HPC_LA30_N" "FMC_HPC_LA30_P" "FMC_HPC_LA31_N" "FMC_HPC_LA31_P" "FMC_HPC_LA32_N" "FMC_HPC_LA32_P" "FMC_HPC_LA33_N" "FMC_HPC_LA33_P" "FMC_HPC_PG_M2C_LS" "FMC_HPC_PRSNT_M2C_L" "FMC_LPC_CLK0_M2C_N" "FMC_LPC_CLK0_M2C_P" "FMC_LPC_CLK1_M2C_N" "FMC_LPC_CLK1_M2C_P" "FMC_LPC_DP0_C2M_N" "FMC_LPC_DP0_C2M_P" "FMC_LPC_DP0_M2C_N" "FMC_LPC_DP0_M2C_P" "FMC_LPC_GBTCLK0_M2C_N" "FMC_LPC_GBTCLK0_M2C_P" "FMC_LPC_IIC_SCL_LS" "FMC_LPC_IIC_SDA_LS" "FMC_LPC_LA00_CC_N" "FMC_LPC_LA00_CC_P" "FMC_LPC_LA01_CC_N" "FMC_LPC_LA01_CC_P" "FMC_LPC_LA02_N" "FMC_LPC_LA02_P" "FMC_LPC_LA03_N" "FMC_LPC_LA03_P" "FMC_LPC_LA04_N" "FMC_LPC_LA04_P" "FMC_LPC_LA05_N"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

"AN19"; "AL23"; "AM23"; "AN23"; "AP22"; "AM27"; "AN27"; "AJ25"; "AH25"; "AN24"; "AN25"; "AL24"; "AK23"; "AP29"; "AN29"; "AP26"; "AP27"; "AM26"; "AL26"; "AM30"; "AN30"; "AM28"; "AN28"; "AL25"; "AM25"; "AP31"; "AP30"; "AJ27"; "AK27"; "AK28"; "AL28"; "AK24"; "AJ24"; "AK29"; "AL29"; "AG26"; "AG25"; "AH24"; "AH23"; "J27"; "AP25"; "B10"; "A10"; "G33"; "F33"; "D2"; "D1"; "G4"; "G3"; "M5"; "M6"; "AF13"; "AG13"; "K27"; "K26"; "E31"; "F31"; "H30"; "G31"; "J32"; "J31"; "J29"; "K28"; "H33";

## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##

C18 H20 H19 G19 G18 D21 D20 C23 C22 H23 H22 G22 G21 H26 H25 G25 G24 D24 D23 H29 H28 G28 G27 D27 D26 C27 C26 H32 H31 G31 G30 H35 H34 G34 G33 H38 H37 G37 G36 F1 H2 H5 H4 G3 G2 C3 C2 C7 C6 D5 D4 2 2 G7 G6 D9 D8 H8 H7 G10 G9 H11 H10 D12

on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on of of on on on on on on on on on on on

J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 Q26 Q27 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63

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Appendix D: ML605 Master UCF

NET "FMC_LPC_LA05_P" NET "FMC_LPC_LA06_N" NET "FMC_LPC_LA06_P" NET "FMC_LPC_LA07_N" NET "FMC_LPC_LA07_P" NET "FMC_LPC_LA08_N" NET "FMC_LPC_LA08_P" NET "FMC_LPC_LA09_N" NET "FMC_LPC_LA09_P" NET "FMC_LPC_LA10_N" NET "FMC_LPC_LA10_P" NET "FMC_LPC_LA11_N" NET "FMC_LPC_LA11_P" NET "FMC_LPC_LA12_N" NET "FMC_LPC_LA12_P" NET "FMC_LPC_LA13_N" NET "FMC_LPC_LA13_P" NET "FMC_LPC_LA14_N" NET "FMC_LPC_LA14_P" NET "FMC_LPC_LA15_N" NET "FMC_LPC_LA15_P" NET "FMC_LPC_LA16_N" NET "FMC_LPC_LA16_P" NET "FMC_LPC_LA17_CC_N" NET "FMC_LPC_LA17_CC_P" NET "FMC_LPC_LA18_CC_N" NET "FMC_LPC_LA18_CC_P" NET "FMC_LPC_LA19_N" NET "FMC_LPC_LA19_P" NET "FMC_LPC_LA20_N" NET "FMC_LPC_LA20_P" NET "FMC_LPC_LA21_N" NET "FMC_LPC_LA21_P" NET "FMC_LPC_LA22_N" NET "FMC_LPC_LA22_P" NET "FMC_LPC_LA23_N" NET "FMC_LPC_LA23_P" NET "FMC_LPC_LA24_N" NET "FMC_LPC_LA24_P" NET "FMC_LPC_LA25_N" NET "FMC_LPC_LA25_P" NET "FMC_LPC_LA26_N" NET "FMC_LPC_LA26_P" NET "FMC_LPC_LA27_N" NET "FMC_LPC_LA27_P" NET "FMC_LPC_LA28_N" NET "FMC_LPC_LA28_P" NET "FMC_LPC_LA29_N" NET "FMC_LPC_LA29_P" NET "FMC_LPC_LA30_N" NET "FMC_LPC_LA30_P" NET "FMC_LPC_LA31_N" NET "FMC_LPC_LA31_P" NET "FMC_LPC_LA32_N" NET "FMC_LPC_LA32_P" NET "FMC_LPC_LA33_N" NET "FMC_LPC_LA33_P" NET "FMC_LPC_PRSNT_M2C_L" ## ## NET "FPGA_CCLK" NET "FPGA_DONE" NET "FPGA_DX_N" NET "FPGA_DX_P" ## NET "FPGA_FCS_B" ## NET "FPGA_FOE_B"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

"H34"; "J34"; "K33"; "H32"; "G32"; "K29"; "J30"; "L26"; "L25"; "G30"; "F30"; "D32"; "D31"; "E33"; "E32"; "C34"; "D34"; "B34"; "C33"; "B32"; "C32"; "B33"; "A33"; "N29"; "N28"; "L30"; "L29"; "N30"; "M30"; "R29"; "P29"; "T26"; "R26"; "P27"; "N27"; "R27"; "R28"; "P32"; "N32"; "P30"; "P31"; "M32"; "L33"; "R32"; "R31"; "M33"; "N33"; "P34"; "N34"; "M27"; "M26"; "L31"; "M31"; "M25"; "N25"; "K31"; "K32"; "AD9"; "K8"; "R8"; "W17"; "W18"; "Y24"; "AA24";

## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##

D11 C11 C10 H14 H13 G13 G12 D15 D14 C15 C14 H17 H16 G16 G15 D18 D17 C19 C18 H20 H19 G19 G18 D21 D20 C23 C22 H23 H22 G22 G21 H26 H25 G25 G24 D24 D23 H29 H28 G28 G27 D27 D26 C27 C26 H32 H31 G31 G30 H35 H34 G34 G33 H38 H37 G37 G36 H2 SEE 2 4 2 SEE SEE

on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on

J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63

NET "FLASH_NN" GROUP on "DONE" LED DS13 on J35 on J35 NET "FLASH_NN" GROUP NET "FLASH_NN" GROUP

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## NET "FPGA_FWE_B" ## NET "FPGA_INIT_B" NET "FPGA_M0" NET "FPGA_M1" NET "FPGA_M2" NET "FPGA_PROG_B" NET "FPGA_TCK" NET "FPGA_TDI" NET "FPGA_TMS" NET "FPGA_VBATT" ## NET "GPIO_DIP_SW1" NET "GPIO_DIP_SW2" NET "GPIO_DIP_SW3" NET "GPIO_DIP_SW4" NET "GPIO_DIP_SW5" NET "GPIO_DIP_SW6" NET "GPIO_DIP_SW7" NET "GPIO_DIP_SW8" ## NET "GPIO_LED_0" NET "GPIO_LED_1" NET "GPIO_LED_2" NET "GPIO_LED_3" NET "GPIO_LED_4" NET "GPIO_LED_5" NET "GPIO_LED_6" NET "GPIO_LED_7" ## NET "GPIO_LED_C" NET "GPIO_LED_E" NET "GPIO_LED_N" NET "GPIO_LED_S" NET "GPIO_LED_W" ## NET "GPIO_SW_C" NET "GPIO_SW_E" NET "GPIO_SW_N" NET "GPIO_SW_S" NET "GPIO_SW_W" ## NET "IIC_SCL_DVI" NET "IIC_SCL_MAIN_LS" NET "IIC_SCL_SFP" NET "IIC_SDA_DVI" NET "IIC_SDA_MAIN_LS" NET "IIC_SDA_SFP" ## NET "LCD_DB4_LS" NET "LCD_DB5_LS" NET "LCD_DB6_LS" NET "LCD_DB7_LS" NET "LCD_E_LS" NET "LCD_RS_LS" NET "LCD_RW_LS" ## NET "P30_CS_SEL" ## NET "PCIE_100M_MGT0_N" NET "PCIE_100M_MGT0_P" NET "PCIE_250M_MGT1_N" NET "PCIE_250M_MGT1_P" NET "PCIE_PERST_B_LS" NET "PCIE_RX0_N"

LOC = "AF23"; LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = "P8"; "U8"; "W8"; "V8"; "L8"; "AE8"; "AD8"; "AF8"; "N8"; "D22"; "C22"; "L21"; "L20"; "C18"; "B18"; "K22"; "K21"; "AC22"; "AC24"; "AE22"; "AE23"; "AB23"; "AG23"; "AE24"; "AD24"; "AP24"; "AE21"; "AH27"; "AH28"; "AD21"; "G26"; "G17"; "A19"; "A18"; "H17"; "AN10"; "AK9"; "AA34"; "AP10"; "AE9"; "AA33"; "AD14"; "AK11"; "AJ11"; "AE12"; "AK12"; "T28"; "AC14";

## SEE NET "FLASH_NN" GROUP ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## 1 3 4 4 1 80 82 85 1 1 2 3 4 5 6 7 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 3 2 1 9 11 10 on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on Q14 ("INIT" LED DS31 driver) S2 DIP switch (active-High) S2 DIP switch (active-High) S2 DIP switch (active-High) SW4 pushbutton (active-Low) U19 U19 U19 B1 (battery + terminal) SW1 SW1 SW1 SW1 SW1 SW1 SW1 SW1 LED LED LED LED LED LED LED LED LED LED LED LED LED SW9 SW7 SW5 SW6 SW8 DIP DIP DIP DIP DIP DIP DIP DIP switch switch switch switch switch switch switch switch 1 2 3 4 5 6 7 8 on on on on on on on on (active-High) (active-High) (active-High) (active-High) (active-High) (active-High) (active-High) (active-High) J62 J62 J62 J62 J62 J62 J62 J62

DS12, DS11, DS9, DS10, DS15, DS14, DS22, DS21, DS16 DS19 DS20 DS18 DS17

pushbutton pushbutton pushbutton pushbutton pushbutton

(active-High) (active-High) (active-High) (active-High) (active-High)

Q5, 15 on U38 Q19 Q23 Q6, 14 on U38 Q20 Q21 J41 J41 J41 J41 J41 J41 J41

LOC = "AJ12"; LOC LOC LOC LOC LOC LOC = = = = = = "P5"; "P6"; "V5"; "V6"; "AE13"; "J4";

## 2 ## ## ## ## ## ## 15 16 18 17 4 B15

on S2 DIP switch (active-High),1 on U10 on on on on on on U14 U14 U9 U9 U32 P1

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NET "PCIE_RX0_P" NET "PCIE_RX1_N" NET "PCIE_RX1_P" NET "PCIE_RX2_N" NET "PCIE_RX2_P" NET "PCIE_RX3_N" NET "PCIE_RX3_P" NET "PCIE_RX4_N" NET "PCIE_RX4_P" NET "PCIE_RX5_N" NET "PCIE_RX5_P" NET "PCIE_RX6_N" NET "PCIE_RX6_P" NET "PCIE_RX7_N" NET "PCIE_RX7_P" NET "PCIE_TX0_N" NET "PCIE_TX0_P" NET "PCIE_TX1_N" NET "PCIE_TX1_P" NET "PCIE_TX2_N" NET "PCIE_TX2_P" NET "PCIE_TX3_N" NET "PCIE_TX3_P" NET "PCIE_TX4_N" NET "PCIE_TX4_P" NET "PCIE_TX5_N" NET "PCIE_TX5_P" NET "PCIE_TX6_N" NET "PCIE_TX6_P" NET "PCIE_TX7_N" NET "PCIE_TX7_P" NET "PCIE_WAKE_B_LS" ## NET "PHY_COL" NET "PHY_CRS" NET "PHY_INT" NET "PHY_MDC" NET "PHY_MDIO" NET "PHY_RESET" NET "PHY_RXCLK" NET "PHY_RXCTL_RXDV" NET "PHY_RXD0" NET "PHY_RXD1" NET "PHY_RXD2" NET "PHY_RXD3" NET "PHY_RXD4" NET "PHY_RXD5" NET "PHY_RXD6" NET "PHY_RXD7" NET "PHY_RXER" NET "PHY_TXCLK" NET "PHY_TXCTL_TXEN" NET "PHY_TXC_GTXCLK" NET "PHY_TXD0" NET "PHY_TXD1" NET "PHY_TXD2" NET "PHY_TXD3" NET "PHY_TXD4" NET "PHY_TXD5" NET "PHY_TXD6" NET "PHY_TXD7" NET "PHY_TXER" ## ## NET "PLATFLASH_L_B" ##

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

"J3"; "K6"; "K5"; "L4"; "L3"; "N4"; "N3"; "R4"; "R3"; "U4"; "U3"; "W4"; "W3"; "AA4"; "AA3"; "F2"; "F1"; "H2"; "H1"; "K2"; "K1"; "M2"; "M1"; "P2"; "P1"; "T2"; "T1"; "V2"; "V1"; "Y2"; "Y1"; "AD22"; "AK13"; "AL13"; "AH14"; "AP14"; "AN14"; "AH13"; "AP11"; "AM13"; "AN13"; "AF14"; "AE14"; "AN12"; "AM12"; "AD11"; "AC12"; "AC13"; "AG12"; "AD12"; "AJ10"; "AH12"; "AM11"; "AL11"; "AG10"; "AG11"; "AL10"; "AM10"; "AE11"; "AF11"; "AH10";

## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##

B14 B20 B19 B24 B23 B28 B27 B34 B33 B38 B37 B42 B41 B46 B45 A17 A16 A22 A21 A26 A25 A30 A29 A36 A35 A40 A39 A44 A43 A48 A47 B11 114 115 32 35 33 36 7 4 3 128 126 125 124 123 121 120 9 10 16 14 18 19 20 24 25 26 28 29 13

on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on

P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80

LOC = "AC23";

## SEE NET "FLASH_NN" GROUP

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NET NET NET NET ## NET NET NET NET NET NET ## NET NET NET NET NET NET ## NET NET NET NET NET NET ## NET NET ## NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET ## NET NET ## NET NET NET NET ## NET NET NET NET NET NET

"PMBUS_ALERT_LS" "PMBUS_CLK_LS" "PMBUS_CTRL_LS" "PMBUS_DATA_LS" "SFP_LOS" "SFP_RX_N" "SFP_RX_P" "SFP_TX_DISABLE_FPGA" "SFP_TX_N" "SFP_TX_P" "SGMIICLK_QO_N" "SGMIICLK_QO_P" "SGMII_RX_N" "SGMII_RX_P" "SGMII_TX_N" "SGMII_TX_P" "SMA_REFCLK_N" "SMA_REFCLK_P" "SMA_RX_N" "SMA_RX_P" "SMA_TX_N" "SMA_TX_P" "SM_FAN_PWM" "SM_FAN_TACH" "SYSACE_CFGTDI" "SYSACE_D0" "SYSACE_D1" "SYSACE_D2" "SYSACE_D3" "SYSACE_D4" "SYSACE_D5" "SYSACE_D6" "SYSACE_D7" "SYSACE_MPA00" "SYSACE_MPA01" "SYSACE_MPA02" "SYSACE_MPA03" "SYSACE_MPA04" "SYSACE_MPA05" "SYSACE_MPA06" "SYSACE_MPBRDY" "SYSACE_MPCE" "SYSACE_MPIRQ" "SYSACE_MPOE" "SYSACE_MPWE" "SYSCLK_N" "SYSCLK_P" "USB_1_CTS" "USB_1_RTS" "USB_1_RX" "USB_1_TX" "USB_A0_LS" "USB_A1_LS" "USB_CS_B_LS" "USB_D0_LS" "USB_D1_LS" "USB_D2_LS"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = =

"AH9"; "AC10"; "AJ9"; "AB10"; "V23"; "E4"; "E3"; "AP12"; "C4"; "C3"; "H5"; "H6"; "B6"; "B5"; "A4"; "A3"; "F5"; "F6"; "D6"; "D5"; "B2"; "B1";

## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##

2 2 2 2 8 12 13 1 19 18 2 2 1 1 1 1 1 1 1 1 1 1

on on on on on on on on on on on on on on on on on on on on on on

Q15 Q18 Q16 Q17 P4 P4 P4 Q22 P4 P4 series series series series series series C55 0.1uF C56 0.1uF C163 0.01uF C162 0.01uF C164 0.01uF C165 0.01uF 0.1uF 0.1uF 0.1uF 0.1uF

series C61 series C62 series C57 series C58 J27 SMA J26 SMA

LOC = "L10"; LOC = "M10"; LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = = = = = = "AC8"; "AM15"; "AJ17"; "AJ16"; "AP16"; "AG16"; "AH15"; "AF16"; "AN15"; "AC15"; "AP15"; "AG17"; "AH17"; "AG15"; "AF15"; "AK14"; "AJ15"; "AJ14"; "L9"; "AL15"; "AL14";

## 1 ## 2 ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## 81 66 65 63 62 61 60 59 58 70 69 68 67 45 44 43 39 42 41 77 76

on Q24 on R368 on on on on on on on on on on on on on on on on on on on on on U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19

LOC = "H9"; LOC = "J9"; LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = "T24"; "T23"; "J25"; "J24"; "Y32"; "W26"; "W27"; "R33"; "R34"; "T30";

## 5 ## 4 ## ## ## ## ## ## ## ## ## ## 22 23 24 25 14 2 18 8 14 6

on U11, 5 on U89 (DNP) on U11, 4 on U89 (DNP) on on on on on on on on on on U34 U34 U34 U34 U30 U29 U29 U31 U31 U31

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NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET ## NET NET NET NET NET ## NET NET NET NET

"USB_D3_LS" "USB_D4_LS" "USB_D5_LS" "USB_D6_LS" "USB_D7_LS" "USB_D8_LS" "USB_D9_LS" "USB_D10_LS" "USB_D11_LS" "USB_D12_LS" "USB_D13_LS" "USB_D14_LS" "USB_D15_LS" "USB_INT_LS" "USB_RD_B_LS" "USB_RESET_B_LS" "USB_WR_B_LS" "USER_CLOCK" "USER_SMA_CLOCK_N" "USER_SMA_CLOCK_P" "USER_SMA_GPIO_N" "USER_SMA_GPIO_P" "VAUX_CURR_N" "VAUX_CURR_P" "VAUX_VOLT_N" "VAUX_VOLT_P"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = =

"T31"; "T29"; "V28"; "V27"; "U25"; "Y28"; "W32"; "W31"; "Y29"; "W29"; "Y34"; "Y33"; "Y31"; "Y27"; "W25"; "T25"; "V25"; "U23"; "M22"; "L23"; "W34"; "V34"; "P26"; "P25"; "M28"; "L28";

## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##

16 4 18 2 12 14 8 12 2 18 4 16 6 6 16 8 4 5 1 1 1 1 1 1 1 1

on on on on on on on on on on on on on on on on on on on on on on on on on on

U31 U31 U31 U31 U30 U29 U29 U29 U30 U30 U30 U30 U30 U29 U29 U30 U29 X5 J55 J58 J56 J57

SMA SMA SMA SMA R373 R370 R371 R372 1.00K 1.00K 1.00K 1.00K

series series series series

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