D.Sarith (Mtech), B.M.Manjunatha: ISSN: 2320 - 8791

Download as pdf or txt
Download as pdf or txt
You are on page 1of 11

IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 6, Dec-Jan, 2014

ISSN: 2320 - 8791 www.ijreat.org

PFC Applications based on new AcAc-Dc Bridgeless Cuk Rectifiers


D.Sarith(Mtech)1, B.M.Manjunatha2
Rajiv Gandhi Memorial College of Engineering& Technology, Nandyal, Kurnool(Dt), Andhra Pradesh

Abstract
Three new bridgeless single-phase acdc power factor correction (PFC) rectifiers based on Cuk topology are proposed. without an input diode bridge and the presence of only two semiconductor switches in the current flowing path during each interval of the switching cycle result in less conduction losses and an improved thermal management compared to the conventional Cuk PFC rectifier. The proposed topologies are designed to work in discontinuous conduction mode (DCM) to achieve al-most a unity power factor and least value of harmonic distortion in the input current. The DCM operation gives additional advantages such as zero-currents turn-ON and turn-OFF in the power switches, output diode, and simple control circuitry. The comparisons between the proposed and conventional Cuk PFC rectifiers are performed based on circuit by using MATHLAB/SIMULATIONS.

con-siderable research efforts have been directed toward designing bridgeless PFC circuits, where the number of semiconductors generating losses is reduced by essentially eliminating the full-bridge input diode rectifier. A bridgeless PFC rectifier allows the current to flow through a minimum number of switching de-vices compared to the conventional PFC rectifier. Accordingly, the converter conduction losses can be significantly reduced and higher efficiency can be obtained, as well as cost savings. Recently, several bridgeless PFC rectifiers have been introduced to improve the rectifier power density and/or reduce noise emis-sions via softswitching techniques or coupled magnetic topologies [1][9]. On the other hand, the bridgeless boost rectifier [10][17] has the same major practical drawbacks as the conventional boost converter such as the dc output voltage is higher than the peak input voltage, lack of galvanic isolation, and high start-up inrush currents. Therefore, for low-output voltage applications, such as telecommunication or computer industry, an additional converter or an isolation transformer is required to step-down the voltage. To overcome these drawbacks, several bridgeless topologies, which are suitable for step-up/step-down applications have been recently introduced in [18][21]. However, the proposed topology in [18] still suffers from having three semiconduc-tors in the current conduction path during each switching cycle. In [19][22], a bridgeless PFC rectifier based on the single-ended primary-inductance converter (SEPIC)topology is pre-sented. Similar to the boost converter, the SEPIC converter has the disadvantage of discontinuous output current resulting in a relatively high output ripple. A bridgeless buck PFC rectifier was recently proposed in [23], [24] for step-down applications. However, the input line current cannot follow the input volt-age around the zero crossings of the input line voltage; besides, the output to input voltage ratio is limited to half. Also, buck PFC converter results in an increased total harmonic distortion (THD) and a reduced power factor [24].

Index TermsBridgeless rectifier, Cuk converter, low conduc-tion


losses, power factor correction (PFC), rectifier, total harmonic distortion (THD).

I. INTRODUCTION
POWER supplies with active power factor correction (PFC) techniques are becoming necessary for many types of elec-tronic equipment to meet harmonic regulations and standards, such as the IEC 61000-3-2. Most of the PFC rectifiers utilize a boost converter at their front end. However, a conventional PFC scheme has lower efficiency due to significant losses in the diode bridge. A conventional PFC Cuk rectifier is shown in Fig. 1; the current flows through two rectifier bridge diodes and the power switch (Q) during the switch ON-time, and through two rectifier bridge diodes and the output diode (Do ) during the switch OFF-time. Thus, during each switching cycle, the current flows through three power semiconductor devices. As a result, a significant conduction loss, caused by the forward volt-age drop across the bridge diode, would degrade the converters efficiency, especially at a low line input voltage.

Fig. 1. Conventional Cuk PFC rectifier.

In an effort to maximize the power supply efficiency,

www.ijreat.org
Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org)

IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 6, Dec-Jan, Dec 2014

ISSN: 2320 - 8791 www.ijreat.org

Fig. 2. Proposed bridgeless Cuk PFC rectifiers. (a) Type 1. (b) Type 2. Fig. 3. Equivalent circuits for the type-1 1 rectifier. (a) During positive half-line half period. (b) During negative half-line line period of the input voltage.

The Cuk converter offers several advantages in PFC appli applications, such as easy implementation of transformer isolation, natural protection against inrush current occurring at start start-up or overload current, lower input current ripple, and less electro-magnetic magnetic interference (EMI) associated with the discontinuous conduction n mode (DCM) topology [23] [23]. Unlike the SEPIC converter, the Cuk converter has both continuous input and out-put put currents with a low current ripple. Thus, for applications, which require a low current ripple at the input and output ports of the converter, the Cuk converter seems to be a potential can-didate didate in the basic converter topologies. In this paper, three topologies of bridgeless Cuk PFC rectifiers are proposed. The proposed roposed rectifiers are compared based on efficiency, components count, harmonics, gain capability, and driver circuit.

2. PROPOSED BRIDGELESS CUK PFC RECTIFIERS


The three proposed bridgeless Cuk PFC rectifiers are shown in Fig. 2. The proposed topologies are formed by connecting two dcdc Cuk converters, one for each half-line line period (T/2) of the input voltage. It should be mentioned here that the topology of Fig. 2(a) was listed in [20] as a new converter topology but not analyzed. The operational circuits during the positive and negative half-line line period for the proposed bridgeless Cuk recti-fiers of Fig. 2(a)(c) (c) are shown in Figs. 35, 5, respectively. Note that by referring to Figs. 3 35, there are one or two semiconduc-tor(s) tor(s) in the current flowing) in the current flowing path;

Fig. 4. Equivalent circuits for type-3 rectifier. (a) During positive half-line period. (b) During negative half-line line period of the input voltage voltag

www.ijreat.org
Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org)

IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 6, Dec-Jan, 2014

ISSN: 2320 - 8791 www.ijreat.org


hence, the current stresses in the active and passive switches are further reduced and the cir-cuit efficiency is improved compared to the conventional Cuk rectifier. In addition, Fig. 2(a) and (c) shows that one rail of the output voltage bus is always connected to the input ac line through the slowrecovery diodes Dp and Dn or directly as in the case of the topology of Fig. 2(b). Thus, the proposed topologies do not suffer from the high common-mode EMI noise emission problem and have common-mode EMI performance similar to the conventional PFC topologies. Consequently, the proposed topologies appear to be promising candidates for commercial PFC products. The proposed bridgeless rectifiers of Fig. 2 utilize two power switches (Q1 and Q2 ). However, the two power switches can be driven by the same control signal, which significantly sim-plifies the control circuitry. Compared to the conventional Cuk topology, the structure of the proposed topologies utilizes one additional inductor, which is often described as a disadvantage in terms of size and cost. However, a better thermal performance can be achieved with the two inductors compared to a single in-ductor. It should be mentioned here that the three inductors in the proposed topologies can be coupled on the same magnetic core allowing considerable size and cost reduction. Addition-ally, the near zero-ripple-current condition at the input or out-put port of the rectifier can be achieved without compromising performance.

(1)

Due to the symmetry of the circuit, it is sufficient to analyze the circuit during the positive half cycle of the input voltage. Moreover, the operation of the proposed rectifiers of Fig. 2 will be described assuming that the three inductors are operating in DCM. By operating the rectifier in DCM, several advantages can be gained. These advantages include natural near-unity power factor, the power switches are turned ON at zero current, and the output diodes (Do 1 and Do 2 ) are turned OFF at zero cur-rent. Thus, the losses due to the turn-ON switching and the reverse recovery of the output diodes are considerably reduced. Conversely, DCM operation significantly increases the conduc-tion losses due to the increased current stress through circuit components. As a result, this leads to one disadvantage of the DCM operation, which limits its use to low-power applications (<300 W) [28]. Similar to the conventional Cuk converter, the circuit operation in DCM can be divided into three distinct operating stages during one switching period Ts . Equivalent circuits over a switching period Ts in the positive half-line period of Fig. 5(a) is shown in Fig. 6. Fig. 7 shows the theoretical DCM waveforms over one switching cycle during the positive half cycle of the input voltage. The topological stages of type 2 over a switching cycle can be briefly described as follows.
Stage 1[t0 , t1 ], [Fig. 6(a)]: This stage starts when the switch Q1 is turned ON. Diode Dp is forward biased by the inductor current iL 1 . As a result, the diode Dn is reverse biased by the input voltage. The output diode Do 1 is reverse biased by the reverse voltage (vac + Vo ), while Do 2 is reverse biased by the output voltage Vo . In this stage, the currents through inductors L1 and Lo 1 increase linearly with the input voltage, while the current through Lo 2 is zero due to the constant voltage across C2. The inductor currents of L1 and Lo 1 during this stage

3.PRINCIPLE OF OPERATION AND THEORETICAL ANALYSIS


3.1. Principle of Operation
The proposed bridgeless type-3 Cuk rectifier of Fig. 2(c) will be considered in this study. Type 1 is similar to type 3, except forthe

output stage stresses. The SEPIC version of type 2 has been analyzed in [19]. The analysis assumes that the converter is op-erating at a steady state in addition to the following assumptions: pure sinusoidal input voltage, ideal lossless components, and all capacitors are large enough such that their switching voltage ripples are negligible during the switching period Ts . Moreover, the output filter capacitor Co (Co 1 and Co 2 for topology 2) has a large capacitance such that the voltage across it is constant over the entire line period. Referring to Fig. 5(a), during the positive half-line cycle, the first dcdc Cuk circuit, L1 Q1 C1 Lo 1 Do 1 , is active through diode Dp , which connects the input ac source to the output. During the negative half-line cycle, as shown in Fig. 5(b), the second dcdc Cuk circuit, L2 Q2 -C2 Lo 2 Do 2 , is active through diode Dn , which connects the input ac source to the output. As a result, the average voltage across capacitor C1 during the line cycle can be expressed as follows:

are given by

www.ijreat.org
Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org)

IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 6, Dec-Jan, 2014

ISSN: 2320 - 8791 www.ijreat.org

Fig. 5. Topological stages over one switching period Ts for the converter of Fig. 4(a). (a) Switch Q1 is ON. (b) Switch Q1 is OFF. (c) DCM.

Accordingly, the peak current through the active switch Q1 is given by


Fig 6.Theorital DCM wave forms during one switching period T2 ,for the converter of Fig.5(a).

where Vm is the peak amplitude of the input voltage vac , D1 is the switch duty cycle, and Le is the parallel combination of inductors L1 and Lo 1 . Stage 2[t1 , t2 ] [Fig. 6(b)]: This stage starts when the switch Q1 is turned OFF and the diode Do 1 is turned ON simultaneously providing a path for the inductor currents iL 1 and iL o 1 . The diode Dp remains conducting to provide a path for iL 1 . Diode Do 2 remains reverse biased during this interval. This interval ends when iD o 1 reaches zero and Do 1 becomes reverse biased. Note that the diode Do 1 is switched OFF at zero current. Similarly, the inductor currents of L1 and Lo 1 during this stage can be represented as follows:

Stage 3[t2 , t3 ] [Fig. 6(c)]: During this interval, only the diode Dp conducts to provide a path for iL 1 . Accordingly, the inductors in this interval behave as constant current sources. Hence, the voltage across the three inductors is zero. The capacitor C1 is being charged by the inductor current iL1This period ends when Q1 is turned ON. By applying inductor volt-second across L1 and Lo 1 , the normalized length of the second stage period can be expressed as follows:

where is the line angular frequency, and M is the voltage conversion ratio (M = Vo /Vm ).

, n= 1,o 1

(4)

Since the diode Dp continuously conducts throughout the entire switching period, the average voltage across C2 is equal to the output voltage Vo . As a result, a negligible ac current will

www.ijreat.org
Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org)

IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 6, Dec-Jan, 2014

ISSN: 2320 - 8791 www.ijreat.org


flow through C2 and Lo 2 . Therefore, the current through L2 during the positive half cycle of the input voltage is equal to the negative current through the body diode of Q2 . It should be noted that the body diode of the inactive switch Q2 is always conducting current during the positive half cycle of the input voltage. This is due to the low impedance of the input inductors (L1 and L2 ) at the line frequency. Therefore, the input diode Dp and body diode of Q2 appear in parallel configuration to share the return current. A large portion of the return current

Similar to the conventional Cuk PFC rectifier, (7) shows that the input port of the proposed rectifier obeys Ohms law. Thus, the input current is sinusoidal and in phase with the input voltage. Hence, the power stage circuit of the converter of Fig. 5 can be represented by its large signal averaged model shown in Fig. 8. This model can be implemented in a simulation program to predict the steady state and large signal dynamic characteristics of the real circuit. Furthermore, the averaged model can greatly reduce the long computation time when it is implemented in simulation software.Evaluating (6) by using (7) and applying the power balance between the input and output ports, the desired voltage conversion ratio is

(9)
It should be noted that the voltage gain in (9) is also valid for the other two proposed topologies. However, the effective inductance (Le ) varies from one topology to another.
Fig. 7. Large signal model of the topology in Fig. 5.

will pass through the diode that has a lower voltage drop. The efficiency of the converter can be slightly improved by using synchronous rectification to turn ON the switch Q2 during the positive half cycle of the input voltage, which eliminates its body-diode conduction.

3.3. Boundaries Between Continuous Conduction Mode and DCM


Referring to the diode Do 1 current waveform in Fig. 7, the DCM operation mode requires that the sum of the switch duty cycle and the normalized switch-OFF time length be less than one, i.e.,

3.2. Voltage Conversion Ratio M


The voltage conversion ratio M in terms of the converter parameters can be obtained by applying the power balance principle. The average input power can be expressed as follows:

Substituting (5) into (10) and using (8) and (9), the following condition for DCM is obtained:

(11)
where the dimensionless conduction parameter Ke is defined as follows:

where the notation < > x represents the average value over the interval x. Note that the input current in the positive half of the line cycle is the same as the inductor current L1 . From Fig. 7, it can be shown that the average input current over a switching cycle is given by
It is clear from (11) that the value of Ke -crit depends on the line angle (t). Hence, the minimum and maximum values of Ke -crit is given by

and =
where the quantity Re is defined as the emulated input resistance of the converter, and is given by respectively. Therefore, for values of Ke < Ke -crit min, the converter always operates in DCM, and it operates in the continuous conduction mode (CCM) for values of Ke > Ke -crit max. However for values of Ke -crit min < Ke < Ke -crit max, the

www.ijreat.org
Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org)

IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 6, Dec-Jan, 2014

ISSN: 2320 - 8791 www.ijreat.org


converter operates in both modes: CCM near the peak value of the input line voltage and DCM near the zero crossing of the input line voltage. the average output inductor current over one switching cycle and it is given by

3.4. Capacitor Selection


The energy transfer capacitors C1 and C2 are important elements in the proposed Cuk topologies since their values greatly influence the quality of input line current. Capacitors C1 and C2 must be chosen such that their steady-state voltages follow the shape of the rectified input ac line voltage wave form plus the output voltage with minimum switching voltage ripple as possible. Also the values of C1 and C2 should not cause low-frequency oscillations with the converter inductors. In a practical design ,the energy transfer capacitors C1 and C2 are determined based on inductors L1 , Lo values (assuming L1 = L2 and Lo 1 = Lo 2 =Lo ) such that the resonant frequency (fr) during DCM stage is higher than the line frequency (fl ) and well below the switching frequency(fs ). thus

=
Substituting (17) into (16) and evaluating (16),the capacitor ripple equation is obtain as follows:

4. COMPARISON STUDY BETWEEN THE PROPOSED AND CONVENTIONAL CUK CONVERTERS


The proposed topologies are compared with respect to their components count, efficiency, driver circuitry complexity, THD, and voltage gain range. To ensure a fair comparison, the inductance values in all topologies are selected such that Ke = 0.9 Kcrit at an operating point of an output power of 300 W. Moreover, an equivalent series resistor (ESR) of 20 m and 12 m is placed in series with all the inductors and capacitors, respectively. Furthermore, PSPICE actual semiconductor models have been used to simu-late the switches. Table I shows the details of the components used in the simulation. The converters were simulated for an output voltage of 48 V under a minimum nominal input voltage of 120 Vrm s condition The simulated efficiency presented in Fig. 8, includes conduction and switching losses of the semiconductor devices, inductors copper losses, capacitors ESR losses, as well as gate drive losses. Table II presents a comparison between topologies of interest. It should be noted that type 2 has the lowest number of semiconductor devices in the current conduction path How-ever, it has two disadvantages: floating switch and a step-up voltage gain greater than 2. The floating switch requires a more complex driver circuitry and typically causes higher electro-

Where

(15)
On the other hand, the output capacitor C0 needs to be sufficiently large to store minimum energy required for balancing the difference between the time varying input power and constant load power. The low-frequency peakpeak output voltage TABLE-1 Components used in simulation

Fig:8 shows efficiency comparision between type1,type2

www.ijreat.org
Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org)

IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 6, Dec-Jan, Dec 2014

ISSN: 2320 - 8791 www.ijreat.org


TABLE-2 COMPARISON BETWEEN CONVENTIONAL AND BRIDGELESS CUK RECTIFIERS IN DCM MODE magnetic emissions. The gain range is limited by the blocking voltage of Do 2 during the positive half cycle of the input line signal similar to the topology discussed in [19]. This disadvan-tage tage can be minimized by implementing input/output galvanic isolation; however, wever, components with higher blocking voltage capability are needed. Type 1 also has the advantage of a lower component count, but a higher high current peak. Whereas, type 2 has a higher component count, but lower stresses. In conclusion, the converter of choice cho is an application dependent. It is evident from Fig.8 that the efficiency fficiency of type1 topology is higher than that of the conventional PFC Cuk rectifier for the provided output power levels.It should be mentioned here that the discrepancies in efficiencies es between type 2and 2 the conventional Cuk PFC rectifiers become more pronounced as

Fig. 9. Simulated waveforms for type-3 3 rectifier of Fig. 2(c) in DCM. (va c = 100 Vr m s , Vo = 48 V, Po u t = 150 W

the power level increases. In this case, it is preferred to operate the converter in CCM region instead of DCM. Fig. 9 also shows input current THD as a function of output power. It is evident from Fig. 9 that both the proposed and the conventional l Cuk rectifier exhibit extremely low THD (<1% for Pout > 100 W) when they are designed to operate in DCM. Note that, by refer-ring ring to Fig. 9, the THD of the converters under study becomes independent of the output power for a power level greater than 100 W.

5. . SIMULATION AND EXPERIMENTAL RESULTS


The type-3 3 converter of Fig. 2(c) has been simulated using PSPICE for the following input and output data specifications: vac = 100 Vrm s , Vo = 48 V, Pout = 150 W, and fs = 50 kHz.

The circuit components used in the simulation are the same s as those in Table I. Fig. 9 shows the simulated voltage and curcur rent waveforms at full-load load condition. It can be observed from Fig. 9(a) (a) that the input line current is in phase with the input voltage. Fig. 9(b) (b) shows the current through the slow diodes Dp and Dn . Fig.9(c) (c) shows the inductors currents waveforms over one line period. Fig. 9(d) (d) shows the simulated output inductor currents over one line period, whereas the switching waveforms of the inductors currents at peak input voltage are illustrated in Fig. 10(e), which correctly demonstrate the DCM operating mode. The active switches currents and the interme-diate capacitors Voltages waveforms are depicted in Fig. 10(f) and (g), respectively. respectiv A prototype of type-2 converter has been built to validate the theoretical results as well as the simulation previously

www.ijreat.org
Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org)

IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 6, Dec-Jan, 2014

ISSN: 2320 - 8791 www.ijreat.org


described. The circuit parameters were all the same as those for the sim-ulation. The input voltage and current are shown in Fig. 12(a). Fig. 12(b) presents the currents through diodes Dp and Dn . Note that the current through Dp enters into DCM before the end of the positive cycle of the line. This occurs because the body diode of Q2 provides an additional path to the current. Fig. 12(c) illustrates the switching waveforms of the inductors currents near peak input voltage, which correctly demonstrates the DCM operating mode. Fig. 12(d) shows the voltage across the intermediate capacitors C1 and C2 along with the input volt-age vac . It is clear from Fig. 12(d) that (1) is fully fulfilled. Finally, Fig. 12(e) and (f) presents the switches (Q1 and Q2 ) as well as output stage diodes (Do 1 and Do 2 ) currents over the line period, respectively. It is evident from Fig. 13(e) and (f) that the switches (Q1 , Do 1 ) and (Q2 , Do 2 ) conduct in alternate half-line cycles, as predicted by the analysis in this study. A very good agreement can be seen between simulation and experimental results. The measured efficiency is about 93.2% at full rated load. In order to compare the differences between type-1 and type-2 topologies, a prototype of type-1 has also been built and tested with the same specifications and circuit parameters as for type 2. It should be mentioned here that type-1 topology requires two switches with unidirectional current capabilities. Accord-ingly, a low voltage drop with very low reverse leakage current Schottky barrier diode (type MBR40250 with VF = 0.75 V at 10 A) is connected in series with the power MOSFETs to prevent any current from flowing through the MOSFET body diode. Fig. 13(a) shows the measured input phase voltage and the input current of the proposed type-1 converter at full load. The low-frequency current envelopes of the three inductors are shown in Fig. 13(b). It is evident that the current envelope of L1 during positive half line cycle (L2 during negative half line cycle) follows a perfect sinusoidal envelope. Fig. 13(c) illus-trates switching waveforms of the inductors currents near peak input voltage, which correctly demonstrates the DCM operating mode. Fig. 13(d) illustrates the switching current waveforms of the switch Q1 and the input diode Dp . Note that the peak switch current fulfills the theoretical predicted results shown in Table II. The lowfrequency current envelopes of the three diodes Dp , Dn , and Do over a few line cycles are depicted in Fig. 13(e). It is evident from Fig. 13(e) that the two input diodes (Dp and Dn ) conduct in alternate half line cycles as expected. Likewise, Fig. 13(f) shows the voltage across the intermediate capacitors C1 and C2 . It is clear from Fig. 14(f) that during positive half line cycle, vC 1 closely tracks the positive portion of the input ac voltage (vac ) plus the output voltage (Vo ), while the voltage across C2 remains nearly constant and it is equal to Vo . The measured efficiency for type-1 topology came close to 92% at full rated load. Compared to type 2, the reduction in efficiency in type-1 topology is mainly due to the increased conduction losses introduced by the extra diodes connected in series with Q1 and Q2 . It is worth mentioning here that using the
newly available reverse-blocking isolated gate bipolar transistor instead of using a power MOSFET with series-connected diode

Fig:10, Simulated diagram type-1

Fig:11, Simulated diagram type-2


Above fig:11 and fig:12 shows MATHLAB/SIMULATED of type-1 and type-2 presents very low ON-state characteristics, which

lead to low conduction losses in a converter that requires reverse-blocking voltage switches.

www.ijreat.org
Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org)

IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 6, Dec-Jan, 2014

ISSN: 2320 - 8791 www.ijreat.org


(vac = 100 Vrms , Vo = 48V, Pout = 150

W). Fig. 12. Experimental waveforms for type-2 rectifier of Fig. 2(c) in DCM. Fig. 13. Experimental waveforms for type-1 rectifier of Fig. 2(a) in DCM. (vac = 100 Vrms , Vo = 48V, Pout = 150 W)

www.ijreat.org
Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org)

IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 6, Dec-Jan, 2014

ISSN: 2320 - 8791 www.ijreat.org


.

Finally, though the input voltage is not a pure sinusoidal waveform and contains about 1% THD, the measured THD of the input line current waveform illustrated in Figs. 12(a) and 13(a) is below 2%.

6. CONCLUSION
Three single-phase acdc bridgeless rectifiers based on Cuk topology are presented and discussed in this paper. The valid-ity and performance of the proposed topologies are verified by simulation and experimental results. Due to the lower conduction and switching losses, the proposed topologies can further improve the conversion efficiency when compared with the conventional Cuk PFC rectifier. Namely, to maintain the same efficiency, the proposed circuits can operate with a higher switching frequency. Thus, additional reduction in the size of the PFC inductor and EMI filter could be achieved. The proposed bridgeless topologies can improve the efficiency by approximately 1.4% compared to the conventional PFC Cuk rectifier. The performance of two types of the proposed topologies was verified on a 150 W experimental prototype. The measured efficiency of the prototype rectifier at 100 Vrm s line and full load is above 93% with THD below 2%. Experimental results are observed to be in good agreement with simulation results.

REFERENCES
[1] R. Martinez and P. N. Enjeti, A high performance single phase rectifierwith input power factor correction,IEEE Trans. Power Electron., vol. 11,no. 2, pp. 311317, Mar. 1996. [2] A. R. Prasad, P. D. Ziogas, and S. Manias, An active power factor correction technique for three-phase diode rectifiers,IEEE Trans. Power Electron., vol. 6, no. 1, pp. 83 92, Jan. 1991. [3] Y. Jang and M. M. Jovanovic, A bridgeless PFC boost rectifier with optimized magnetic utilization,IEEE Trans. Power Electron, vol. 24, no. 1, pp. 8593, Jan. 2009. [4] M. A. Al-Saffar, E. H. Ismail, and A. J. Sabzali, Integratedbuckboost quadratic buck PFC rectifier for universal input applicationsI,EEE Trans. Power Electron., vol. 24, no. 12, Dec. 2009. [5] C. Jingquan, D. Maksimovic, and R. Erickson, A new low-stress buckboost converter for universal-input PPC applications, inProc.16th IEEEAPEC Conf,Mar.2001,vol. 1, pp. 343349. [6] H. Wei and I. Batarseh, Comparison of basic converter topologies forpower factor correction, inProc. IEEE Southeastcon, Apr. 2426, 1998,pp. 348353. [7] P. F. de Melo, R. Gules, E. F. R. Romaneli, and R. C .Annunziato, Amodified SEPIC converter for high power factor rectifier and universalinput voltage applications, IEEE Trans. Power Electron., vol. 25, no. 2,Feb. 2010 [8] E. H. Ismail, Bridgeless SEPIC rectifier with unity power factor and reduced conduction losses, IEEE Trans. Ind. Electron., vol. 56, no. 4,pp. 11471157, Apr. 2009.

[9] R. Martinez and P. N. Enjeti, A high performance singlephase AC to DCrectifier with input power factor correction, IEEE Trans. Power Electron.,vol. 11, no. 2, pp. 311317, Mar. 1996. [10] O. Gracia, J. A. Cobos, R. Prieto, and J. Uceda, Single phase power factor correction: A survey,IEEE Trans. Power Electron., vol. 18, no. 3, pp. 749755, May 2003. [11] A. F. Souza and I. Barbi, High power factor rectifier with reduced conduction and commutation losses, inProc. INTELEC, Jun. 1999, pp. 18. [12] C. M. Wang, A novel zero-voltage switching PWM boost rectifier with high power factor and low conduction losses, inProc. INTELEC, Oct. 2003, pp. 224229 [13]L. Huber, Y. Jang, and M. M. Jovanovic, Performance evaluation of bridgeless PFC boost rectifiers, inProc. IEEE Appl. Power Electron.Conf., Feb. 2007, pp. 165171 [14] D.M. Mitchell, "AC-DC Converter having an improved power factor",U.S. Patent4,412,277, Oct. 25, 1983. [15] Huber, Laszlo; Jang, Yungtaek; Jovanovic, Milan M.,"Performance Evaluation of Bridgeless PFC Boost Rectifiers" IEEE Transactions on Power Electronics, vol. 23, no 3, pp.1381-1390, May 2008. [16] D. Tollik and A. Pietkiewicz, Comparative analysis of 1-phase active power factor correction topologies, in Proc. Int. Telecommunication Energy Conf., Oct. 1992, pp. 517 523. [17] A. F. Souza and I. Barbi, High power factor rectifier with reduced conduction and commutation losses, in Proc. Int. Telecommunication Energy Conf., Jun. 1999. [18] Woo-Young Choi, Jung-Min Kwon, Eung-Ho Kim, Jong-Jae Lee, and Bong-Hwan Kwon, Bridgeless BoostRectifier with Low Conduction Losses and Reduced Diode Reverse-Recovery Problems IEEE Transactions on Industrial Electronics, vol. 54, no.2, pp.769-780, April 2007. [19] Ismail EH. Bridgeless SEPIC Rectifier With Unity Power Factor and Reduced Conduction Losses, IEEE Transactions on Industrial Electronics; vol 56, no.4, pp.11471157, April 2009. [20] R. Redl and L. Balogh, RMS, dc, peak, and harmonic currents in high-frequency power-factor correctors with capacitive energy storage,in Proc. IEEE Appl. Power Electron. Conf. (APEC) Proc., Feb. 1992,pp. 533540. [21] L. Huber, L. Gang, and M. M. Jovanovi c, DesignOriented analysis and performance evaluation of buck PFC front-end, IEEE Trans. Power Electron., vol. 25, no. 1, pp. 8594, Jan. 2010. [22] G. Spiazzi, Analysis of buck converters used as power factor preregulators, inProc. IEEE Power Electron. Spec. Conf. (PESC) Rec., Jun. 1997,pp. 564570. [23] V. Grigore and J. Kyyr a, High power factor rectifier based on buck converter operating in discontinuous capacitor voltage mode, IEEE Trans.Power Electron., vol. 15, no. 6, pp. 12411249, Nov. 2000 [24] Gao Chao, Luo Shiguo, Research of alleviating switch voltage stress in single stage PFC converters, Acta Scienti arum Universitatis Sunyatseni, 2002, vol. 41, no. 5, pp. 34-37.

www.ijreat.org
Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org)

10

IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 6, Dec-Jan, 2014

ISSN: 2320 - 8791 www.ijreat.org

B.M.Manjunatha was born in 1981 in India. He received the B.E from Vijaya Nagara Engg. College, Affiliated to Visweswara Technological University (VTU), Belgaum, India in 2004. Master of Technology from J.N.T.U, Hyderabad in 2008. Currently working as Assistant Professor in the Department of Electrical& Electronics Engineering, R.G.M. College of Engineering & Technology, Nandyal, Andhra Pradesh. His areas of interests are in Special Electrical Machines and Drives. Ms.D.Saritha was born in Nellore, A.P. She is M.tech Student in Department of EEE at Rajiv Gandhi Memorial College of Engineering & Technology,Nandyal,Kurnool,A.P.Her research interests are in the areas of

Transient Stability of Power System and FACTS devices.

*********Energy is not to be wasted away, use it in a better way*******

www.ijreat.org
Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org)

11

You might also like